1/* SPDX-License-Identifier: GPL-2.0+ */
2/*
3 * Copyright (c) Aspeed Technology Inc.
4 */
5#ifndef _ASM_ARCH_SDRAM_AST2600_H
6#define _ASM_ARCH_SDRAM_AST2600_H
7
8/* keys for unlocking HW */
9#define SDRAM_UNLOCK_KEY		0xFC600309
10#define SDRAM_VIDEO_UNLOCK_KEY		0x00440003
11
12/* Fixed priority DRAM Requests mask */
13#define REQ_PRI_VGA_HW_CURSOR_R         0
14#define REQ_PRI_VGA_CRT_R               1
15#define REQ_PRI_SOC_DISPLAY_CTRL_R      2
16#define REQ_PRI_PCIE_BUS1_RW            3
17#define REQ_PRI_VIDEO_HIGH_PRI_W        4
18#define REQ_PRI_CPU_RW                  5
19#define REQ_PRI_SLI_RW                  6
20#define REQ_PRI_PCIE_BUS2_RW            7
21#define REQ_PRI_USB2_0_HUB_EHCI1_DMA_RW 8
22#define REQ_PRI_USB2_0_DEV_EHCI2_DMA_RW 9
23#define REQ_PRI_USB1_1_UHCI_HOST_RW     10
24#define REQ_PRI_AHB_BUS_RW              11
25#define REQ_PRI_CM3_DATA_RW             12
26#define REQ_PRI_CM3_INST_R              13
27#define REQ_PRI_MAC0_DMA_RW             14
28#define REQ_PRI_MAC1_DMA_RW             15
29#define REQ_PRI_SDIO_DMA_RW             16
30#define REQ_PRI_PILOT_ENGINE_RW         17
31#define REQ_PRI_XDMA1_RW                18
32#define REQ_PRI_MCTP1_RW                19
33#define REQ_PRI_VIDEO_FLAG_RW           20
34#define REQ_PRI_VIDEO_LOW_PRI_W         21
35#define REQ_PRI_2D_ENGINE_DATA_RW       22
36#define REQ_PRI_ENC_ENGINE_RW           23
37#define REQ_PRI_MCTP2_RW                24
38#define REQ_PRI_XDMA2_RW                25
39#define REQ_PRI_ECC_RSA_RW              26
40
41#define MCR30_RESET_DLL_DELAY_EN	BIT(4)
42#define MCR30_MODE_REG_SEL_SHIFT	1
43#define MCR30_MODE_REG_SEL_MASK		GENMASK(3, 1)
44#define MCR30_SET_MODE_REG		BIT(0)
45
46#define MCR30_SET_MR(mr) ((mr << MCR30_MODE_REG_SEL_SHIFT) | MCR30_SET_MODE_REG)
47
48#define MCR34_SELF_REFRESH_STATUS_MASK	GENMASK(30, 28)
49
50#define MCR34_ODT_DELAY_SHIFT		12
51#define MCR34_ODT_DELAY_MASK		GENMASK(15, 12)
52#define MCR34_ODT_EXT_SHIFT		10
53#define MCR34_ODT_EXT_MASK		GENMASK(11, 10)
54#define MCR34_ODT_AUTO_ON		BIT(9)
55#define MCR34_ODT_EN			BIT(8)
56#define MCR34_RESETN_DIS		BIT(7)
57#define MCR34_MREQI_DIS			BIT(6)
58#define MCR34_MREQ_BYPASS_DIS		BIT(5)
59#define MCR34_RGAP_CTRL_EN		BIT(4)
60#define MCR34_CKE_OUT_IN_SELF_REF_DIS	BIT(3)
61#define MCR34_FOURCE_SELF_REF_EN	BIT(2)
62#define MCR34_AUTOPWRDN_EN		BIT(1)
63#define MCR34_CKE_EN			BIT(0)
64
65#define MCR38_RW_MAX_GRANT_CNT_RQ_SHIFT	16
66#define MCR38_RW_MAX_GRANT_CNT_RQ_MASK	GENMASK(20, 16)
67
68/* default request queued limitation mask (0xFFBBFFF4) */
69#define MCR3C_DEFAULT_MASK                                                     \
70	~(REQ_PRI_VGA_HW_CURSOR_R | REQ_PRI_VGA_CRT_R | REQ_PRI_PCIE_BUS1_RW | \
71	  REQ_PRI_XDMA1_RW | REQ_PRI_2D_ENGINE_DATA_RW)
72
73#define MCR50_RESET_ALL_INTR		BIT(31)
74#define SDRAM_CONF_ECC_AUTO_SCRUBBING	BIT(9)
75#define SDRAM_CONF_SCRAMBLE		BIT(8)
76#define SDRAM_CONF_ECC_EN		BIT(7)
77#define SDRAM_CONF_DUALX8		BIT(5)
78#define SDRAM_CONF_DDR4			BIT(4)
79#define SDRAM_CONF_VGA_SIZE_SHIFT	2
80#define SDRAM_CONF_VGA_SIZE_MASK	GENMASK(3, 2)
81#define SDRAM_CONF_CAP_SHIFT		0
82#define SDRAM_CONF_CAP_MASK		GENMASK(1, 0)
83
84#define SDRAM_CONF_CAP_256M		0
85#define SDRAM_CONF_CAP_512M		1
86#define SDRAM_CONF_CAP_1024M		2
87#define SDRAM_CONF_CAP_2048M		3
88#define SDRAM_CONF_ECC_SETUP		(SDRAM_CONF_ECC_AUTO_SCRUBBING | SDRAM_CONF_ECC_EN)
89
90#define SDRAM_MISC_DDR4_TREFRESH	(1 << 3)
91
92#define SDRAM_PHYCTRL0_PLL_LOCKED	BIT(4)
93#define SDRAM_PHYCTRL0_NRST		BIT(2)
94#define SDRAM_PHYCTRL0_INIT		BIT(0)
95
96/* MCR0C */
97#define SDRAM_REFRESH_PERIOD_ZQCS_SHIFT	16
98#define SDRAM_REFRESH_PERIOD_ZQCS_MASK	GENMASK(31, 16)
99#define SDRAM_REFRESH_PERIOD_SHIFT	8
100#define SDRAM_REFRESH_PERIOD_MASK	GENMASK(15, 8)
101#define SDRAM_REFRESH_ZQCS_EN		BIT(7)
102#define SDRAM_RESET_DLL_ZQCL_EN		BIT(6)
103#define SDRAM_LOW_PRI_REFRESH_EN	BIT(5)
104#define SDRAM_FORCE_PRECHARGE_EN	BIT(4)
105#define SDRAM_REFRESH_EN		BIT(0)
106
107/* MCR14 */
108#define SDRAM_WL_SETTING		GENMASK(23, 20)
109#define SDRAM_CL_SETTING		GENMASK(19, 16)
110
111#define SDRAM_TEST_LEN_SHIFT		4
112#define SDRAM_TEST_LEN_MASK		0xfffff
113#define SDRAM_TEST_START_ADDR_SHIFT	24
114#define SDRAM_TEST_START_ADDR_MASK	0x3f
115
116#define SDRAM_TEST_EN			(1 << 0)
117#define SDRAM_TEST_MODE_SHIFT		1
118#define SDRAM_TEST_MODE_MASK		(0x3 << SDRAM_TEST_MODE_SHIFT)
119#define SDRAM_TEST_MODE_WO		(0x0 << SDRAM_TEST_MODE_SHIFT)
120#define SDRAM_TEST_MODE_RB		(0x1 << SDRAM_TEST_MODE_SHIFT)
121#define SDRAM_TEST_MODE_RW		(0x2 << SDRAM_TEST_MODE_SHIFT)
122
123#define SDRAM_TEST_GEN_MODE_SHIFT	3
124#define SDRAM_TEST_GEN_MODE_MASK	(7 << SDRAM_TEST_GEN_MODE_SHIFT)
125#define SDRAM_TEST_TWO_MODES		(1 << 6)
126#define SDRAM_TEST_ERRSTOP		(1 << 7)
127#define SDRAM_TEST_DONE			(1 << 12)
128#define SDRAM_TEST_FAIL			(1 << 13)
129
130#define SDRAM_AC_TRFC_SHIFT		0
131#define SDRAM_AC_TRFC_MASK		0xff
132
133#define SDRAM_ECC_RANGE_ADDR_MASK	GENMASK(30, 20)
134#define SDRAM_ECC_RANGE_ADDR_SHIFT	20
135
136#ifndef __ASSEMBLY__
137struct ast2600_sdrammc_regs {
138	u32 protection_key;		/* offset 0x00 */
139	u32 config;			/* offset 0x04 */
140	u32 gm_protection_key;		/* offset 0x08 */
141	u32 refresh_timing;		/* offset 0x0C */
142	u32 ac_timing[4];		/* offset 0x10 ~ 0x1C */
143	u32 mr01_mode_setting;		/* offset 0x20 */
144	u32 mr23_mode_setting;		/* offset 0x24 */
145	u32 mr45_mode_setting;		/* offset 0x28 */
146	u32 mr6_mode_setting;		/* offset 0x2C */
147	u32 mode_setting_control;	/* offset 0x30 */
148	u32 power_ctrl;			/* offset 0x34 */
149	u32 arbitration_ctrl;		/* offset 0x38 */
150	u32 req_limit_mask;		/* offset 0x3C */
151	u32 max_grant_len[4];		/* offset 0x40 ~ 0x4C */
152	u32 intr_ctrl;			/* offset 0x50 */
153	u32 ecc_range_ctrl;		/* offset 0x54 */
154	u32 first_ecc_err_addr;		/* offset 0x58 */
155	u32 last_ecc_err_addr;		/* offset 0x5C */
156	u32 phy_ctrl[4];		/* offset 0x60 ~ 0x6C */
157	u32 ecc_test_ctrl;		/* offset 0x70 */
158	u32 test_addr;			/* offset 0x74 */
159	u32 test_fail_dq_bit;		/* offset 0x78 */
160	u32 test_init_val;		/* offset 0x7C */
161	u32 req_input_ctrl;		/* offset 0x80 */
162	u32 req_high_pri_ctrl;		/* offset 0x84 */
163	u32 reserved0[6];		/* offset 0x88 ~ 0x9C */
164};
165#endif  /* __ASSEMBLY__ */
166
167#endif  /* _ASM_ARCH_SDRAM_AST2600_H */
168