1// SPDX-License-Identifier: GPL-2.0+ 2/************************************************************************** 3Intel Pro 1000 for ppcboot/das-u-boot 4Drivers are port from Intel's Linux driver e1000-4.3.15 5and from Etherboot pro 1000 driver by mrakes at vivato dot net 6tested on both gig copper and gig fiber boards 7***************************************************************************/ 8/******************************************************************************* 9 10 11 Copyright(c) 1999 - 2002 Intel Corporation. All rights reserved. 12 13 14 Contact Information: 15 Linux NICS <linux.nics@intel.com> 16 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 17 18*******************************************************************************/ 19/* 20 * Copyright (C) Archway Digital Solutions. 21 * 22 * written by Chrsitopher Li <cli at arcyway dot com> or <chrisl at gnuchina dot org> 23 * 2/9/2002 24 * 25 * Copyright (C) Linux Networx. 26 * Massive upgrade to work with the new intel gigabit NICs. 27 * <ebiederman at lnxi dot com> 28 * 29 * Copyright 2011 Freescale Semiconductor, Inc. 30 */ 31 32#include <common.h> 33#include <command.h> 34#include <cpu_func.h> 35#include <dm.h> 36#include <errno.h> 37#include <log.h> 38#include <malloc.h> 39#include <memalign.h> 40#include <net.h> 41#include <pci.h> 42#include <linux/delay.h> 43#include "e1000.h" 44#include <asm/cache.h> 45 46#define TOUT_LOOP 100000 47 48#define E1000_DEFAULT_PCI_PBA 0x00000030 49#define E1000_DEFAULT_PCIE_PBA 0x000a0026 50 51/* NIC specific static variables go here */ 52 53/* Intel i210 needs the DMA descriptor rings aligned to 128b */ 54#define E1000_BUFFER_ALIGN 128 55 56/* 57 * TODO(sjg@chromium.org): Even with driver model we share these buffers. 58 * Concurrent receiving on multiple active Ethernet devices will not work. 59 * Normally U-Boot does not support this anyway. To fix it in this driver, 60 * move these buffers and the tx/rx pointers to struct e1000_hw. 61 */ 62DEFINE_ALIGN_BUFFER(struct e1000_tx_desc, tx_base, 16, E1000_BUFFER_ALIGN); 63DEFINE_ALIGN_BUFFER(struct e1000_rx_desc, rx_base, 16, E1000_BUFFER_ALIGN); 64DEFINE_ALIGN_BUFFER(unsigned char, packet, 4096, E1000_BUFFER_ALIGN); 65 66static int tx_tail; 67static int rx_tail, rx_last; 68static int num_cards; /* Number of E1000 devices seen so far */ 69 70static struct pci_device_id e1000_supported[] = { 71 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82542) }, 72 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82543GC_FIBER) }, 73 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82543GC_COPPER) }, 74 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82544EI_COPPER) }, 75 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82544EI_FIBER) }, 76 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82544GC_COPPER) }, 77 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82544GC_LOM) }, 78 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82540EM) }, 79 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82545EM_COPPER) }, 80 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82545GM_COPPER) }, 81 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82546EB_COPPER) }, 82 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82545EM_FIBER) }, 83 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82546EB_FIBER) }, 84 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82546GB_COPPER) }, 85 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82540EM_LOM) }, 86 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82541ER) }, 87 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82541GI_LF) }, 88 /* E1000 PCIe card */ 89 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_COPPER) }, 90 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_FIBER) }, 91 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_SERDES) }, 92 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_QUAD_COPPER) }, 93 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571PT_QUAD_COPPER) }, 94 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_QUAD_FIBER) }, 95 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_QUAD_COPPER_LOWPROFILE) }, 96 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_SERDES_DUAL) }, 97 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_SERDES_QUAD) }, 98 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82572EI_COPPER) }, 99 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82572EI_FIBER) }, 100 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82572EI_SERDES) }, 101 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82572EI) }, 102 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82573E) }, 103 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82573E_IAMT) }, 104 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82573L) }, 105 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82574L) }, 106 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82546GB_QUAD_COPPER_KSP3) }, 107 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80003ES2LAN_COPPER_DPT) }, 108 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80003ES2LAN_SERDES_DPT) }, 109 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80003ES2LAN_COPPER_SPT) }, 110 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80003ES2LAN_SERDES_SPT) }, 111 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_UNPROGRAMMED) }, 112 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I211_UNPROGRAMMED) }, 113 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_COPPER) }, 114 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I211_COPPER) }, 115 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_COPPER_FLASHLESS) }, 116 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_SERDES) }, 117 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_SERDES_FLASHLESS) }, 118 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_1000BASEKX) }, 119 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I225_UNPROGRAMMED) }, 120 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I225_IT) }, 121 122 {} 123}; 124 125/* Function forward declarations */ 126static int e1000_setup_link(struct e1000_hw *hw); 127static int e1000_setup_fiber_link(struct e1000_hw *hw); 128static int e1000_setup_copper_link(struct e1000_hw *hw); 129static int e1000_phy_setup_autoneg(struct e1000_hw *hw); 130static void e1000_config_collision_dist(struct e1000_hw *hw); 131static int e1000_config_mac_to_phy(struct e1000_hw *hw); 132static int e1000_config_fc_after_link_up(struct e1000_hw *hw); 133static int e1000_check_for_link(struct e1000_hw *hw); 134static int e1000_wait_autoneg(struct e1000_hw *hw); 135static int e1000_get_speed_and_duplex(struct e1000_hw *hw, uint16_t * speed, 136 uint16_t * duplex); 137static int e1000_read_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, 138 uint16_t * phy_data); 139static int e1000_write_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, 140 uint16_t phy_data); 141static int32_t e1000_phy_hw_reset(struct e1000_hw *hw); 142static int e1000_phy_reset(struct e1000_hw *hw); 143static int e1000_detect_gig_phy(struct e1000_hw *hw); 144static void e1000_set_media_type(struct e1000_hw *hw); 145 146static int32_t e1000_swfw_sync_acquire(struct e1000_hw *hw, uint16_t mask); 147static void e1000_swfw_sync_release(struct e1000_hw *hw, uint16_t mask); 148static int32_t e1000_check_phy_reset_block(struct e1000_hw *hw); 149 150#ifndef CONFIG_E1000_NO_NVM 151static void e1000_put_hw_eeprom_semaphore(struct e1000_hw *hw); 152static int32_t e1000_get_hw_eeprom_semaphore(struct e1000_hw *hw); 153static int32_t e1000_read_eeprom(struct e1000_hw *hw, uint16_t offset, 154 uint16_t words, 155 uint16_t *data); 156/****************************************************************************** 157 * Raises the EEPROM's clock input. 158 * 159 * hw - Struct containing variables accessed by shared code 160 * eecd - EECD's current value 161 *****************************************************************************/ 162void e1000_raise_ee_clk(struct e1000_hw *hw, uint32_t * eecd) 163{ 164 /* Raise the clock input to the EEPROM (by setting the SK bit), and then 165 * wait 50 microseconds. 166 */ 167 *eecd = *eecd | E1000_EECD_SK; 168 E1000_WRITE_REG(hw, EECD, *eecd); 169 E1000_WRITE_FLUSH(hw); 170 udelay(50); 171} 172 173/****************************************************************************** 174 * Lowers the EEPROM's clock input. 175 * 176 * hw - Struct containing variables accessed by shared code 177 * eecd - EECD's current value 178 *****************************************************************************/ 179void e1000_lower_ee_clk(struct e1000_hw *hw, uint32_t * eecd) 180{ 181 /* Lower the clock input to the EEPROM (by clearing the SK bit), and then 182 * wait 50 microseconds. 183 */ 184 *eecd = *eecd & ~E1000_EECD_SK; 185 E1000_WRITE_REG(hw, EECD, *eecd); 186 E1000_WRITE_FLUSH(hw); 187 udelay(50); 188} 189 190/****************************************************************************** 191 * Shift data bits out to the EEPROM. 192 * 193 * hw - Struct containing variables accessed by shared code 194 * data - data to send to the EEPROM 195 * count - number of bits to shift out 196 *****************************************************************************/ 197static void 198e1000_shift_out_ee_bits(struct e1000_hw *hw, uint16_t data, uint16_t count) 199{ 200 uint32_t eecd; 201 uint32_t mask; 202 203 /* We need to shift "count" bits out to the EEPROM. So, value in the 204 * "data" parameter will be shifted out to the EEPROM one bit at a time. 205 * In order to do this, "data" must be broken down into bits. 206 */ 207 mask = 0x01 << (count - 1); 208 eecd = E1000_READ_REG(hw, EECD); 209 eecd &= ~(E1000_EECD_DO | E1000_EECD_DI); 210 do { 211 /* A "1" is shifted out to the EEPROM by setting bit "DI" to a "1", 212 * and then raising and then lowering the clock (the SK bit controls 213 * the clock input to the EEPROM). A "0" is shifted out to the EEPROM 214 * by setting "DI" to "0" and then raising and then lowering the clock. 215 */ 216 eecd &= ~E1000_EECD_DI; 217 218 if (data & mask) 219 eecd |= E1000_EECD_DI; 220 221 E1000_WRITE_REG(hw, EECD, eecd); 222 E1000_WRITE_FLUSH(hw); 223 224 udelay(50); 225 226 e1000_raise_ee_clk(hw, &eecd); 227 e1000_lower_ee_clk(hw, &eecd); 228 229 mask = mask >> 1; 230 231 } while (mask); 232 233 /* We leave the "DI" bit set to "0" when we leave this routine. */ 234 eecd &= ~E1000_EECD_DI; 235 E1000_WRITE_REG(hw, EECD, eecd); 236} 237 238/****************************************************************************** 239 * Shift data bits in from the EEPROM 240 * 241 * hw - Struct containing variables accessed by shared code 242 *****************************************************************************/ 243static uint16_t 244e1000_shift_in_ee_bits(struct e1000_hw *hw, uint16_t count) 245{ 246 uint32_t eecd; 247 uint32_t i; 248 uint16_t data; 249 250 /* In order to read a register from the EEPROM, we need to shift 'count' 251 * bits in from the EEPROM. Bits are "shifted in" by raising the clock 252 * input to the EEPROM (setting the SK bit), and then reading the 253 * value of the "DO" bit. During this "shifting in" process the 254 * "DI" bit should always be clear. 255 */ 256 257 eecd = E1000_READ_REG(hw, EECD); 258 259 eecd &= ~(E1000_EECD_DO | E1000_EECD_DI); 260 data = 0; 261 262 for (i = 0; i < count; i++) { 263 data = data << 1; 264 e1000_raise_ee_clk(hw, &eecd); 265 266 eecd = E1000_READ_REG(hw, EECD); 267 268 eecd &= ~(E1000_EECD_DI); 269 if (eecd & E1000_EECD_DO) 270 data |= 1; 271 272 e1000_lower_ee_clk(hw, &eecd); 273 } 274 275 return data; 276} 277 278/****************************************************************************** 279 * Returns EEPROM to a "standby" state 280 * 281 * hw - Struct containing variables accessed by shared code 282 *****************************************************************************/ 283void e1000_standby_eeprom(struct e1000_hw *hw) 284{ 285 struct e1000_eeprom_info *eeprom = &hw->eeprom; 286 uint32_t eecd; 287 288 eecd = E1000_READ_REG(hw, EECD); 289 290 if (eeprom->type == e1000_eeprom_microwire) { 291 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK); 292 E1000_WRITE_REG(hw, EECD, eecd); 293 E1000_WRITE_FLUSH(hw); 294 udelay(eeprom->delay_usec); 295 296 /* Clock high */ 297 eecd |= E1000_EECD_SK; 298 E1000_WRITE_REG(hw, EECD, eecd); 299 E1000_WRITE_FLUSH(hw); 300 udelay(eeprom->delay_usec); 301 302 /* Select EEPROM */ 303 eecd |= E1000_EECD_CS; 304 E1000_WRITE_REG(hw, EECD, eecd); 305 E1000_WRITE_FLUSH(hw); 306 udelay(eeprom->delay_usec); 307 308 /* Clock low */ 309 eecd &= ~E1000_EECD_SK; 310 E1000_WRITE_REG(hw, EECD, eecd); 311 E1000_WRITE_FLUSH(hw); 312 udelay(eeprom->delay_usec); 313 } else if (eeprom->type == e1000_eeprom_spi) { 314 /* Toggle CS to flush commands */ 315 eecd |= E1000_EECD_CS; 316 E1000_WRITE_REG(hw, EECD, eecd); 317 E1000_WRITE_FLUSH(hw); 318 udelay(eeprom->delay_usec); 319 eecd &= ~E1000_EECD_CS; 320 E1000_WRITE_REG(hw, EECD, eecd); 321 E1000_WRITE_FLUSH(hw); 322 udelay(eeprom->delay_usec); 323 } 324} 325 326/*************************************************************************** 327* Description: Determines if the onboard NVM is FLASH or EEPROM. 328* 329* hw - Struct containing variables accessed by shared code 330****************************************************************************/ 331static bool e1000_is_onboard_nvm_eeprom(struct e1000_hw *hw) 332{ 333 uint32_t eecd = 0; 334 335 DEBUGFUNC(); 336 337 if (hw->mac_type == e1000_ich8lan) 338 return false; 339 340 if (hw->mac_type == e1000_82573 || hw->mac_type == e1000_82574) { 341 eecd = E1000_READ_REG(hw, EECD); 342 343 /* Isolate bits 15 & 16 */ 344 eecd = ((eecd >> 15) & 0x03); 345 346 /* If both bits are set, device is Flash type */ 347 if (eecd == 0x03) 348 return false; 349 } 350 return true; 351} 352 353/****************************************************************************** 354 * Prepares EEPROM for access 355 * 356 * hw - Struct containing variables accessed by shared code 357 * 358 * Lowers EEPROM clock. Clears input pin. Sets the chip select pin. This 359 * function should be called before issuing a command to the EEPROM. 360 *****************************************************************************/ 361int32_t e1000_acquire_eeprom(struct e1000_hw *hw) 362{ 363 struct e1000_eeprom_info *eeprom = &hw->eeprom; 364 uint32_t eecd, i = 0; 365 366 DEBUGFUNC(); 367 368 if (e1000_swfw_sync_acquire(hw, E1000_SWFW_EEP_SM)) 369 return -E1000_ERR_SWFW_SYNC; 370 eecd = E1000_READ_REG(hw, EECD); 371 372 if (hw->mac_type != e1000_82573 && hw->mac_type != e1000_82574) { 373 /* Request EEPROM Access */ 374 if (hw->mac_type > e1000_82544) { 375 eecd |= E1000_EECD_REQ; 376 E1000_WRITE_REG(hw, EECD, eecd); 377 eecd = E1000_READ_REG(hw, EECD); 378 while ((!(eecd & E1000_EECD_GNT)) && 379 (i < E1000_EEPROM_GRANT_ATTEMPTS)) { 380 i++; 381 udelay(5); 382 eecd = E1000_READ_REG(hw, EECD); 383 } 384 if (!(eecd & E1000_EECD_GNT)) { 385 eecd &= ~E1000_EECD_REQ; 386 E1000_WRITE_REG(hw, EECD, eecd); 387 DEBUGOUT("Could not acquire EEPROM grant\n"); 388 return -E1000_ERR_EEPROM; 389 } 390 } 391 } 392 393 /* Setup EEPROM for Read/Write */ 394 395 if (eeprom->type == e1000_eeprom_microwire) { 396 /* Clear SK and DI */ 397 eecd &= ~(E1000_EECD_DI | E1000_EECD_SK); 398 E1000_WRITE_REG(hw, EECD, eecd); 399 400 /* Set CS */ 401 eecd |= E1000_EECD_CS; 402 E1000_WRITE_REG(hw, EECD, eecd); 403 } else if (eeprom->type == e1000_eeprom_spi) { 404 /* Clear SK and CS */ 405 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK); 406 E1000_WRITE_REG(hw, EECD, eecd); 407 udelay(1); 408 } 409 410 return E1000_SUCCESS; 411} 412 413/****************************************************************************** 414 * Sets up eeprom variables in the hw struct. Must be called after mac_type 415 * is configured. Additionally, if this is ICH8, the flash controller GbE 416 * registers must be mapped, or this will crash. 417 * 418 * hw - Struct containing variables accessed by shared code 419 *****************************************************************************/ 420static int32_t e1000_init_eeprom_params(struct e1000_hw *hw) 421{ 422 struct e1000_eeprom_info *eeprom = &hw->eeprom; 423 uint32_t eecd; 424 int32_t ret_val = E1000_SUCCESS; 425 uint16_t eeprom_size; 426 427 if (hw->mac_type == e1000_igb) 428 eecd = E1000_READ_REG(hw, I210_EECD); 429 else 430 eecd = E1000_READ_REG(hw, EECD); 431 432 DEBUGFUNC(); 433 434 switch (hw->mac_type) { 435 case e1000_82542_rev2_0: 436 case e1000_82542_rev2_1: 437 case e1000_82543: 438 case e1000_82544: 439 eeprom->type = e1000_eeprom_microwire; 440 eeprom->word_size = 64; 441 eeprom->opcode_bits = 3; 442 eeprom->address_bits = 6; 443 eeprom->delay_usec = 50; 444 eeprom->use_eerd = false; 445 eeprom->use_eewr = false; 446 break; 447 case e1000_82540: 448 case e1000_82545: 449 case e1000_82545_rev_3: 450 case e1000_82546: 451 case e1000_82546_rev_3: 452 eeprom->type = e1000_eeprom_microwire; 453 eeprom->opcode_bits = 3; 454 eeprom->delay_usec = 50; 455 if (eecd & E1000_EECD_SIZE) { 456 eeprom->word_size = 256; 457 eeprom->address_bits = 8; 458 } else { 459 eeprom->word_size = 64; 460 eeprom->address_bits = 6; 461 } 462 eeprom->use_eerd = false; 463 eeprom->use_eewr = false; 464 break; 465 case e1000_82541: 466 case e1000_82541_rev_2: 467 case e1000_82547: 468 case e1000_82547_rev_2: 469 if (eecd & E1000_EECD_TYPE) { 470 eeprom->type = e1000_eeprom_spi; 471 eeprom->opcode_bits = 8; 472 eeprom->delay_usec = 1; 473 if (eecd & E1000_EECD_ADDR_BITS) { 474 eeprom->page_size = 32; 475 eeprom->address_bits = 16; 476 } else { 477 eeprom->page_size = 8; 478 eeprom->address_bits = 8; 479 } 480 } else { 481 eeprom->type = e1000_eeprom_microwire; 482 eeprom->opcode_bits = 3; 483 eeprom->delay_usec = 50; 484 if (eecd & E1000_EECD_ADDR_BITS) { 485 eeprom->word_size = 256; 486 eeprom->address_bits = 8; 487 } else { 488 eeprom->word_size = 64; 489 eeprom->address_bits = 6; 490 } 491 } 492 eeprom->use_eerd = false; 493 eeprom->use_eewr = false; 494 break; 495 case e1000_82571: 496 case e1000_82572: 497 eeprom->type = e1000_eeprom_spi; 498 eeprom->opcode_bits = 8; 499 eeprom->delay_usec = 1; 500 if (eecd & E1000_EECD_ADDR_BITS) { 501 eeprom->page_size = 32; 502 eeprom->address_bits = 16; 503 } else { 504 eeprom->page_size = 8; 505 eeprom->address_bits = 8; 506 } 507 eeprom->use_eerd = false; 508 eeprom->use_eewr = false; 509 break; 510 case e1000_82573: 511 case e1000_82574: 512 eeprom->type = e1000_eeprom_spi; 513 eeprom->opcode_bits = 8; 514 eeprom->delay_usec = 1; 515 if (eecd & E1000_EECD_ADDR_BITS) { 516 eeprom->page_size = 32; 517 eeprom->address_bits = 16; 518 } else { 519 eeprom->page_size = 8; 520 eeprom->address_bits = 8; 521 } 522 if (e1000_is_onboard_nvm_eeprom(hw) == false) { 523 eeprom->use_eerd = true; 524 eeprom->use_eewr = true; 525 526 eeprom->type = e1000_eeprom_flash; 527 eeprom->word_size = 2048; 528 529 /* Ensure that the Autonomous FLASH update bit is cleared due to 530 * Flash update issue on parts which use a FLASH for NVM. */ 531 eecd &= ~E1000_EECD_AUPDEN; 532 E1000_WRITE_REG(hw, EECD, eecd); 533 } 534 break; 535 case e1000_80003es2lan: 536 eeprom->type = e1000_eeprom_spi; 537 eeprom->opcode_bits = 8; 538 eeprom->delay_usec = 1; 539 if (eecd & E1000_EECD_ADDR_BITS) { 540 eeprom->page_size = 32; 541 eeprom->address_bits = 16; 542 } else { 543 eeprom->page_size = 8; 544 eeprom->address_bits = 8; 545 } 546 eeprom->use_eerd = true; 547 eeprom->use_eewr = false; 548 break; 549 case e1000_igb: 550 /* i210 has 4k of iNVM mapped as EEPROM */ 551 eeprom->type = e1000_eeprom_invm; 552 eeprom->opcode_bits = 8; 553 eeprom->delay_usec = 1; 554 eeprom->page_size = 32; 555 eeprom->address_bits = 16; 556 eeprom->use_eerd = true; 557 eeprom->use_eewr = false; 558 break; 559 default: 560 break; 561 } 562 563 if (eeprom->type == e1000_eeprom_spi || 564 eeprom->type == e1000_eeprom_invm) { 565 /* eeprom_size will be an enum [0..8] that maps 566 * to eeprom sizes 128B to 567 * 32KB (incremented by powers of 2). 568 */ 569 if (hw->mac_type <= e1000_82547_rev_2) { 570 /* Set to default value for initial eeprom read. */ 571 eeprom->word_size = 64; 572 ret_val = e1000_read_eeprom(hw, EEPROM_CFG, 1, 573 &eeprom_size); 574 if (ret_val) 575 return ret_val; 576 eeprom_size = (eeprom_size & EEPROM_SIZE_MASK) 577 >> EEPROM_SIZE_SHIFT; 578 /* 256B eeprom size was not supported in earlier 579 * hardware, so we bump eeprom_size up one to 580 * ensure that "1" (which maps to 256B) is never 581 * the result used in the shifting logic below. */ 582 if (eeprom_size) 583 eeprom_size++; 584 } else { 585 eeprom_size = (uint16_t)((eecd & 586 E1000_EECD_SIZE_EX_MASK) >> 587 E1000_EECD_SIZE_EX_SHIFT); 588 } 589 590 eeprom->word_size = 1 << (eeprom_size + EEPROM_WORD_SIZE_SHIFT); 591 } 592 return ret_val; 593} 594 595/****************************************************************************** 596 * Polls the status bit (bit 1) of the EERD to determine when the read is done. 597 * 598 * hw - Struct containing variables accessed by shared code 599 *****************************************************************************/ 600static int32_t 601e1000_poll_eerd_eewr_done(struct e1000_hw *hw, int eerd) 602{ 603 uint32_t attempts = 100000; 604 uint32_t i, reg = 0; 605 int32_t done = E1000_ERR_EEPROM; 606 607 for (i = 0; i < attempts; i++) { 608 if (eerd == E1000_EEPROM_POLL_READ) { 609 if (hw->mac_type == e1000_igb) 610 reg = E1000_READ_REG(hw, I210_EERD); 611 else 612 reg = E1000_READ_REG(hw, EERD); 613 } else { 614 if (hw->mac_type == e1000_igb) 615 reg = E1000_READ_REG(hw, I210_EEWR); 616 else 617 reg = E1000_READ_REG(hw, EEWR); 618 } 619 620 if (reg & E1000_EEPROM_RW_REG_DONE) { 621 done = E1000_SUCCESS; 622 break; 623 } 624 udelay(5); 625 } 626 627 return done; 628} 629 630/****************************************************************************** 631 * Reads a 16 bit word from the EEPROM using the EERD register. 632 * 633 * hw - Struct containing variables accessed by shared code 634 * offset - offset of word in the EEPROM to read 635 * data - word read from the EEPROM 636 * words - number of words to read 637 *****************************************************************************/ 638static int32_t 639e1000_read_eeprom_eerd(struct e1000_hw *hw, 640 uint16_t offset, 641 uint16_t words, 642 uint16_t *data) 643{ 644 uint32_t i, eerd = 0; 645 int32_t error = 0; 646 647 for (i = 0; i < words; i++) { 648 eerd = ((offset+i) << E1000_EEPROM_RW_ADDR_SHIFT) + 649 E1000_EEPROM_RW_REG_START; 650 651 if (hw->mac_type == e1000_igb) 652 E1000_WRITE_REG(hw, I210_EERD, eerd); 653 else 654 E1000_WRITE_REG(hw, EERD, eerd); 655 656 error = e1000_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_READ); 657 658 if (error) 659 break; 660 661 if (hw->mac_type == e1000_igb) { 662 data[i] = (E1000_READ_REG(hw, I210_EERD) >> 663 E1000_EEPROM_RW_REG_DATA); 664 } else { 665 data[i] = (E1000_READ_REG(hw, EERD) >> 666 E1000_EEPROM_RW_REG_DATA); 667 } 668 669 } 670 671 return error; 672} 673 674void e1000_release_eeprom(struct e1000_hw *hw) 675{ 676 uint32_t eecd; 677 678 DEBUGFUNC(); 679 680 eecd = E1000_READ_REG(hw, EECD); 681 682 if (hw->eeprom.type == e1000_eeprom_spi) { 683 eecd |= E1000_EECD_CS; /* Pull CS high */ 684 eecd &= ~E1000_EECD_SK; /* Lower SCK */ 685 686 E1000_WRITE_REG(hw, EECD, eecd); 687 688 udelay(hw->eeprom.delay_usec); 689 } else if (hw->eeprom.type == e1000_eeprom_microwire) { 690 /* cleanup eeprom */ 691 692 /* CS on Microwire is active-high */ 693 eecd &= ~(E1000_EECD_CS | E1000_EECD_DI); 694 695 E1000_WRITE_REG(hw, EECD, eecd); 696 697 /* Rising edge of clock */ 698 eecd |= E1000_EECD_SK; 699 E1000_WRITE_REG(hw, EECD, eecd); 700 E1000_WRITE_FLUSH(hw); 701 udelay(hw->eeprom.delay_usec); 702 703 /* Falling edge of clock */ 704 eecd &= ~E1000_EECD_SK; 705 E1000_WRITE_REG(hw, EECD, eecd); 706 E1000_WRITE_FLUSH(hw); 707 udelay(hw->eeprom.delay_usec); 708 } 709 710 /* Stop requesting EEPROM access */ 711 if (hw->mac_type > e1000_82544) { 712 eecd &= ~E1000_EECD_REQ; 713 E1000_WRITE_REG(hw, EECD, eecd); 714 } 715 716 e1000_swfw_sync_release(hw, E1000_SWFW_EEP_SM); 717} 718 719/****************************************************************************** 720 * Reads a 16 bit word from the EEPROM. 721 * 722 * hw - Struct containing variables accessed by shared code 723 *****************************************************************************/ 724static int32_t 725e1000_spi_eeprom_ready(struct e1000_hw *hw) 726{ 727 uint16_t retry_count = 0; 728 uint8_t spi_stat_reg; 729 730 DEBUGFUNC(); 731 732 /* Read "Status Register" repeatedly until the LSB is cleared. The 733 * EEPROM will signal that the command has been completed by clearing 734 * bit 0 of the internal status register. If it's not cleared within 735 * 5 milliseconds, then error out. 736 */ 737 retry_count = 0; 738 do { 739 e1000_shift_out_ee_bits(hw, EEPROM_RDSR_OPCODE_SPI, 740 hw->eeprom.opcode_bits); 741 spi_stat_reg = (uint8_t)e1000_shift_in_ee_bits(hw, 8); 742 if (!(spi_stat_reg & EEPROM_STATUS_RDY_SPI)) 743 break; 744 745 udelay(5); 746 retry_count += 5; 747 748 e1000_standby_eeprom(hw); 749 } while (retry_count < EEPROM_MAX_RETRY_SPI); 750 751 /* ATMEL SPI write time could vary from 0-20mSec on 3.3V devices (and 752 * only 0-5mSec on 5V devices) 753 */ 754 if (retry_count >= EEPROM_MAX_RETRY_SPI) { 755 DEBUGOUT("SPI EEPROM Status error\n"); 756 return -E1000_ERR_EEPROM; 757 } 758 759 return E1000_SUCCESS; 760} 761 762/****************************************************************************** 763 * Reads a 16 bit word from the EEPROM. 764 * 765 * hw - Struct containing variables accessed by shared code 766 * offset - offset of word in the EEPROM to read 767 * data - word read from the EEPROM 768 *****************************************************************************/ 769static int32_t 770e1000_read_eeprom(struct e1000_hw *hw, uint16_t offset, 771 uint16_t words, uint16_t *data) 772{ 773 struct e1000_eeprom_info *eeprom = &hw->eeprom; 774 uint32_t i = 0; 775 776 DEBUGFUNC(); 777 778 /* If eeprom is not yet detected, do so now */ 779 if (eeprom->word_size == 0) 780 e1000_init_eeprom_params(hw); 781 782 /* A check for invalid values: offset too large, too many words, 783 * and not enough words. 784 */ 785 if ((offset >= eeprom->word_size) || 786 (words > eeprom->word_size - offset) || 787 (words == 0)) { 788 DEBUGOUT("\"words\" parameter out of bounds." 789 "Words = %d, size = %d\n", offset, eeprom->word_size); 790 return -E1000_ERR_EEPROM; 791 } 792 793 /* EEPROM's that don't use EERD to read require us to bit-bang the SPI 794 * directly. In this case, we need to acquire the EEPROM so that 795 * FW or other port software does not interrupt. 796 */ 797 if (e1000_is_onboard_nvm_eeprom(hw) == true && 798 hw->eeprom.use_eerd == false) { 799 800 /* Prepare the EEPROM for bit-bang reading */ 801 if (e1000_acquire_eeprom(hw) != E1000_SUCCESS) 802 return -E1000_ERR_EEPROM; 803 } 804 805 /* Eerd register EEPROM access requires no eeprom aquire/release */ 806 if (eeprom->use_eerd == true) 807 return e1000_read_eeprom_eerd(hw, offset, words, data); 808 809 /* Set up the SPI or Microwire EEPROM for bit-bang reading. We have 810 * acquired the EEPROM at this point, so any returns should relase it */ 811 if (eeprom->type == e1000_eeprom_spi) { 812 uint16_t word_in; 813 uint8_t read_opcode = EEPROM_READ_OPCODE_SPI; 814 815 if (e1000_spi_eeprom_ready(hw)) { 816 e1000_release_eeprom(hw); 817 return -E1000_ERR_EEPROM; 818 } 819 820 e1000_standby_eeprom(hw); 821 822 /* Some SPI eeproms use the 8th address bit embedded in 823 * the opcode */ 824 if ((eeprom->address_bits == 8) && (offset >= 128)) 825 read_opcode |= EEPROM_A8_OPCODE_SPI; 826 827 /* Send the READ command (opcode + addr) */ 828 e1000_shift_out_ee_bits(hw, read_opcode, eeprom->opcode_bits); 829 e1000_shift_out_ee_bits(hw, (uint16_t)(offset*2), 830 eeprom->address_bits); 831 832 /* Read the data. The address of the eeprom internally 833 * increments with each byte (spi) being read, saving on the 834 * overhead of eeprom setup and tear-down. The address 835 * counter will roll over if reading beyond the size of 836 * the eeprom, thus allowing the entire memory to be read 837 * starting from any offset. */ 838 for (i = 0; i < words; i++) { 839 word_in = e1000_shift_in_ee_bits(hw, 16); 840 data[i] = (word_in >> 8) | (word_in << 8); 841 } 842 } else if (eeprom->type == e1000_eeprom_microwire) { 843 for (i = 0; i < words; i++) { 844 /* Send the READ command (opcode + addr) */ 845 e1000_shift_out_ee_bits(hw, 846 EEPROM_READ_OPCODE_MICROWIRE, 847 eeprom->opcode_bits); 848 e1000_shift_out_ee_bits(hw, (uint16_t)(offset + i), 849 eeprom->address_bits); 850 851 /* Read the data. For microwire, each word requires 852 * the overhead of eeprom setup and tear-down. */ 853 data[i] = e1000_shift_in_ee_bits(hw, 16); 854 e1000_standby_eeprom(hw); 855 } 856 } 857 858 /* End this read operation */ 859 e1000_release_eeprom(hw); 860 861 return E1000_SUCCESS; 862} 863 864/****************************************************************************** 865 * e1000_write_eeprom_srwr - Write to Shadow Ram using EEWR 866 * @hw: pointer to the HW structure 867 * @offset: offset within the Shadow Ram to be written to 868 * @words: number of words to write 869 * @data: 16 bit word(s) to be written to the Shadow Ram 870 * 871 * Writes data to Shadow Ram at offset using EEWR register. 872 * 873 * If e1000_update_eeprom_checksum_i210 is not called after this function, the 874 * Shadow Ram will most likely contain an invalid checksum. 875 *****************************************************************************/ 876static int32_t e1000_write_eeprom_srwr(struct e1000_hw *hw, uint16_t offset, 877 uint16_t words, uint16_t *data) 878{ 879 struct e1000_eeprom_info *eeprom = &hw->eeprom; 880 uint32_t i, k, eewr = 0; 881 uint32_t attempts = 100000; 882 int32_t ret_val = 0; 883 884 /* A check for invalid values: offset too large, too many words, 885 * too many words for the offset, and not enough words. 886 */ 887 if ((offset >= eeprom->word_size) || 888 (words > (eeprom->word_size - offset)) || (words == 0)) { 889 DEBUGOUT("nvm parameter(s) out of bounds\n"); 890 ret_val = -E1000_ERR_EEPROM; 891 goto out; 892 } 893 894 for (i = 0; i < words; i++) { 895 eewr = ((offset + i) << E1000_EEPROM_RW_ADDR_SHIFT) 896 | (data[i] << E1000_EEPROM_RW_REG_DATA) | 897 E1000_EEPROM_RW_REG_START; 898 899 E1000_WRITE_REG(hw, I210_EEWR, eewr); 900 901 for (k = 0; k < attempts; k++) { 902 if (E1000_EEPROM_RW_REG_DONE & 903 E1000_READ_REG(hw, I210_EEWR)) { 904 ret_val = 0; 905 break; 906 } 907 udelay(5); 908 } 909 910 if (ret_val) { 911 DEBUGOUT("Shadow RAM write EEWR timed out\n"); 912 break; 913 } 914 } 915 916out: 917 return ret_val; 918} 919 920/****************************************************************************** 921 * e1000_pool_flash_update_done_i210 - Pool FLUDONE status. 922 * @hw: pointer to the HW structure 923 * 924 *****************************************************************************/ 925static int32_t e1000_pool_flash_update_done_i210(struct e1000_hw *hw) 926{ 927 int32_t ret_val = -E1000_ERR_EEPROM; 928 uint32_t i, reg; 929 930 for (i = 0; i < E1000_FLUDONE_ATTEMPTS; i++) { 931 reg = E1000_READ_REG(hw, EECD); 932 if (reg & E1000_EECD_FLUDONE_I210) { 933 ret_val = 0; 934 break; 935 } 936 udelay(5); 937 } 938 939 return ret_val; 940} 941 942/****************************************************************************** 943 * e1000_update_flash_i210 - Commit EEPROM to the flash 944 * @hw: pointer to the HW structure 945 * 946 *****************************************************************************/ 947static int32_t e1000_update_flash_i210(struct e1000_hw *hw) 948{ 949 int32_t ret_val = 0; 950 uint32_t flup; 951 952 ret_val = e1000_pool_flash_update_done_i210(hw); 953 if (ret_val == -E1000_ERR_EEPROM) { 954 DEBUGOUT("Flash update time out\n"); 955 goto out; 956 } 957 958 flup = E1000_READ_REG(hw, EECD) | E1000_EECD_FLUPD_I210; 959 E1000_WRITE_REG(hw, EECD, flup); 960 961 ret_val = e1000_pool_flash_update_done_i210(hw); 962 if (ret_val) 963 DEBUGOUT("Flash update time out\n"); 964 else 965 DEBUGOUT("Flash update complete\n"); 966 967out: 968 return ret_val; 969} 970 971/****************************************************************************** 972 * e1000_update_eeprom_checksum_i210 - Update EEPROM checksum 973 * @hw: pointer to the HW structure 974 * 975 * Updates the EEPROM checksum by reading/adding each word of the EEPROM 976 * up to the checksum. Then calculates the EEPROM checksum and writes the 977 * value to the EEPROM. Next commit EEPROM data onto the Flash. 978 *****************************************************************************/ 979static int32_t e1000_update_eeprom_checksum_i210(struct e1000_hw *hw) 980{ 981 int32_t ret_val = 0; 982 uint16_t checksum = 0; 983 uint16_t i, nvm_data; 984 985 /* Read the first word from the EEPROM. If this times out or fails, do 986 * not continue or we could be in for a very long wait while every 987 * EEPROM read fails 988 */ 989 ret_val = e1000_read_eeprom_eerd(hw, 0, 1, &nvm_data); 990 if (ret_val) { 991 DEBUGOUT("EEPROM read failed\n"); 992 goto out; 993 } 994 995 if (!(e1000_get_hw_eeprom_semaphore(hw))) { 996 /* Do not use hw->nvm.ops.write, hw->nvm.ops.read 997 * because we do not want to take the synchronization 998 * semaphores twice here. 999 */ 1000 1001 for (i = 0; i < EEPROM_CHECKSUM_REG; i++) { 1002 ret_val = e1000_read_eeprom_eerd(hw, i, 1, &nvm_data); 1003 if (ret_val) { 1004 e1000_put_hw_eeprom_semaphore(hw); 1005 DEBUGOUT("EEPROM Read Error while updating checksum.\n"); 1006 goto out; 1007 } 1008 checksum += nvm_data; 1009 } 1010 checksum = (uint16_t)EEPROM_SUM - checksum; 1011 ret_val = e1000_write_eeprom_srwr(hw, EEPROM_CHECKSUM_REG, 1, 1012 &checksum); 1013 if (ret_val) { 1014 e1000_put_hw_eeprom_semaphore(hw); 1015 DEBUGOUT("EEPROM Write Error while updating checksum.\n"); 1016 goto out; 1017 } 1018 1019 e1000_put_hw_eeprom_semaphore(hw); 1020 1021 ret_val = e1000_update_flash_i210(hw); 1022 } else { 1023 ret_val = -E1000_ERR_SWFW_SYNC; 1024 } 1025 1026out: 1027 return ret_val; 1028} 1029 1030/****************************************************************************** 1031 * Verifies that the EEPROM has a valid checksum 1032 * 1033 * hw - Struct containing variables accessed by shared code 1034 * 1035 * Reads the first 64 16 bit words of the EEPROM and sums the values read. 1036 * If the the sum of the 64 16 bit words is 0xBABA, the EEPROM's checksum is 1037 * valid. 1038 *****************************************************************************/ 1039static int e1000_validate_eeprom_checksum(struct e1000_hw *hw) 1040{ 1041 uint16_t i, checksum, checksum_reg, *buf; 1042 1043 DEBUGFUNC(); 1044 1045 /* Allocate a temporary buffer */ 1046 buf = malloc(sizeof(buf[0]) * (EEPROM_CHECKSUM_REG + 1)); 1047 if (!buf) { 1048 E1000_ERR(hw, "Unable to allocate EEPROM buffer!\n"); 1049 return -E1000_ERR_EEPROM; 1050 } 1051 1052 /* Read the EEPROM */ 1053 if (e1000_read_eeprom(hw, 0, EEPROM_CHECKSUM_REG + 1, buf) < 0) { 1054 E1000_ERR(hw, "Unable to read EEPROM!\n"); 1055 return -E1000_ERR_EEPROM; 1056 } 1057 1058 /* Compute the checksum */ 1059 checksum = 0; 1060 for (i = 0; i < EEPROM_CHECKSUM_REG; i++) 1061 checksum += buf[i]; 1062 checksum = ((uint16_t)EEPROM_SUM) - checksum; 1063 checksum_reg = buf[i]; 1064 1065 /* Verify it! */ 1066 if (checksum == checksum_reg) 1067 return 0; 1068 1069 /* Hrm, verification failed, print an error */ 1070 E1000_ERR(hw, "EEPROM checksum is incorrect!\n"); 1071 E1000_ERR(hw, " ...register was 0x%04hx, calculated 0x%04hx\n", 1072 checksum_reg, checksum); 1073 1074 return -E1000_ERR_EEPROM; 1075} 1076#endif /* CONFIG_E1000_NO_NVM */ 1077 1078/***************************************************************************** 1079 * Set PHY to class A mode 1080 * Assumes the following operations will follow to enable the new class mode. 1081 * 1. Do a PHY soft reset 1082 * 2. Restart auto-negotiation or force link. 1083 * 1084 * hw - Struct containing variables accessed by shared code 1085 ****************************************************************************/ 1086static int32_t 1087e1000_set_phy_mode(struct e1000_hw *hw) 1088{ 1089#ifndef CONFIG_E1000_NO_NVM 1090 int32_t ret_val; 1091 uint16_t eeprom_data; 1092 1093 DEBUGFUNC(); 1094 1095 if ((hw->mac_type == e1000_82545_rev_3) && 1096 (hw->media_type == e1000_media_type_copper)) { 1097 ret_val = e1000_read_eeprom(hw, EEPROM_PHY_CLASS_WORD, 1098 1, &eeprom_data); 1099 if (ret_val) 1100 return ret_val; 1101 1102 if ((eeprom_data != EEPROM_RESERVED_WORD) && 1103 (eeprom_data & EEPROM_PHY_CLASS_A)) { 1104 ret_val = e1000_write_phy_reg(hw, 1105 M88E1000_PHY_PAGE_SELECT, 0x000B); 1106 if (ret_val) 1107 return ret_val; 1108 ret_val = e1000_write_phy_reg(hw, 1109 M88E1000_PHY_GEN_CONTROL, 0x8104); 1110 if (ret_val) 1111 return ret_val; 1112 1113 hw->phy_reset_disable = false; 1114 } 1115 } 1116#endif 1117 return E1000_SUCCESS; 1118} 1119 1120#ifndef CONFIG_E1000_NO_NVM 1121/*************************************************************************** 1122 * 1123 * Obtaining software semaphore bit (SMBI) before resetting PHY. 1124 * 1125 * hw: Struct containing variables accessed by shared code 1126 * 1127 * returns: - E1000_ERR_RESET if fail to obtain semaphore. 1128 * E1000_SUCCESS at any other case. 1129 * 1130 ***************************************************************************/ 1131static int32_t 1132e1000_get_software_semaphore(struct e1000_hw *hw) 1133{ 1134 int32_t timeout = hw->eeprom.word_size + 1; 1135 uint32_t swsm; 1136 1137 DEBUGFUNC(); 1138 1139 if (hw->mac_type != e1000_80003es2lan && hw->mac_type != e1000_igb) 1140 return E1000_SUCCESS; 1141 1142 while (timeout) { 1143 swsm = E1000_READ_REG(hw, SWSM); 1144 /* If SMBI bit cleared, it is now set and we hold 1145 * the semaphore */ 1146 if (!(swsm & E1000_SWSM_SMBI)) 1147 break; 1148 mdelay(1); 1149 timeout--; 1150 } 1151 1152 if (!timeout) { 1153 DEBUGOUT("Driver can't access device - SMBI bit is set.\n"); 1154 return -E1000_ERR_RESET; 1155 } 1156 1157 return E1000_SUCCESS; 1158} 1159#endif 1160 1161/*************************************************************************** 1162 * This function clears HW semaphore bits. 1163 * 1164 * hw: Struct containing variables accessed by shared code 1165 * 1166 * returns: - None. 1167 * 1168 ***************************************************************************/ 1169static void 1170e1000_put_hw_eeprom_semaphore(struct e1000_hw *hw) 1171{ 1172#ifndef CONFIG_E1000_NO_NVM 1173 uint32_t swsm; 1174 1175 DEBUGFUNC(); 1176 1177 if (!hw->eeprom_semaphore_present) 1178 return; 1179 1180 swsm = E1000_READ_REG(hw, SWSM); 1181 if (hw->mac_type == e1000_80003es2lan || hw->mac_type == e1000_igb) { 1182 /* Release both semaphores. */ 1183 swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI); 1184 } else 1185 swsm &= ~(E1000_SWSM_SWESMBI); 1186 E1000_WRITE_REG(hw, SWSM, swsm); 1187#endif 1188} 1189 1190/*************************************************************************** 1191 * 1192 * Using the combination of SMBI and SWESMBI semaphore bits when resetting 1193 * adapter or Eeprom access. 1194 * 1195 * hw: Struct containing variables accessed by shared code 1196 * 1197 * returns: - E1000_ERR_EEPROM if fail to access EEPROM. 1198 * E1000_SUCCESS at any other case. 1199 * 1200 ***************************************************************************/ 1201static int32_t 1202e1000_get_hw_eeprom_semaphore(struct e1000_hw *hw) 1203{ 1204#ifndef CONFIG_E1000_NO_NVM 1205 int32_t timeout; 1206 uint32_t swsm; 1207 1208 DEBUGFUNC(); 1209 1210 if (!hw->eeprom_semaphore_present) 1211 return E1000_SUCCESS; 1212 1213 if (hw->mac_type == e1000_80003es2lan || hw->mac_type == e1000_igb) { 1214 /* Get the SW semaphore. */ 1215 if (e1000_get_software_semaphore(hw) != E1000_SUCCESS) 1216 return -E1000_ERR_EEPROM; 1217 } 1218 1219 /* Get the FW semaphore. */ 1220 timeout = hw->eeprom.word_size + 1; 1221 while (timeout) { 1222 swsm = E1000_READ_REG(hw, SWSM); 1223 swsm |= E1000_SWSM_SWESMBI; 1224 E1000_WRITE_REG(hw, SWSM, swsm); 1225 /* if we managed to set the bit we got the semaphore. */ 1226 swsm = E1000_READ_REG(hw, SWSM); 1227 if (swsm & E1000_SWSM_SWESMBI) 1228 break; 1229 1230 udelay(50); 1231 timeout--; 1232 } 1233 1234 if (!timeout) { 1235 /* Release semaphores */ 1236 e1000_put_hw_eeprom_semaphore(hw); 1237 DEBUGOUT("Driver can't access the Eeprom - " 1238 "SWESMBI bit is set.\n"); 1239 return -E1000_ERR_EEPROM; 1240 } 1241#endif 1242 return E1000_SUCCESS; 1243} 1244 1245/* Take ownership of the PHY */ 1246static int32_t 1247e1000_swfw_sync_acquire(struct e1000_hw *hw, uint16_t mask) 1248{ 1249 uint32_t swfw_sync = 0; 1250 uint32_t swmask = mask; 1251 uint32_t fwmask = mask << 16; 1252 int32_t timeout = 200; 1253 1254 DEBUGFUNC(); 1255 while (timeout) { 1256 if (e1000_get_hw_eeprom_semaphore(hw)) 1257 return -E1000_ERR_SWFW_SYNC; 1258 1259 swfw_sync = E1000_READ_REG(hw, SW_FW_SYNC); 1260 if (!(swfw_sync & (fwmask | swmask))) 1261 break; 1262 1263 /* firmware currently using resource (fwmask) */ 1264 /* or other software thread currently using resource (swmask) */ 1265 e1000_put_hw_eeprom_semaphore(hw); 1266 mdelay(5); 1267 timeout--; 1268 } 1269 1270 if (!timeout) { 1271 DEBUGOUT("Driver can't access resource, SW_FW_SYNC timeout.\n"); 1272 return -E1000_ERR_SWFW_SYNC; 1273 } 1274 1275 swfw_sync |= swmask; 1276 E1000_WRITE_REG(hw, SW_FW_SYNC, swfw_sync); 1277 1278 e1000_put_hw_eeprom_semaphore(hw); 1279 return E1000_SUCCESS; 1280} 1281 1282static void e1000_swfw_sync_release(struct e1000_hw *hw, uint16_t mask) 1283{ 1284 uint32_t swfw_sync = 0; 1285 1286 DEBUGFUNC(); 1287 while (e1000_get_hw_eeprom_semaphore(hw)) 1288 ; /* Empty */ 1289 1290 swfw_sync = E1000_READ_REG(hw, SW_FW_SYNC); 1291 swfw_sync &= ~mask; 1292 E1000_WRITE_REG(hw, SW_FW_SYNC, swfw_sync); 1293 1294 e1000_put_hw_eeprom_semaphore(hw); 1295} 1296 1297static bool e1000_is_second_port(struct e1000_hw *hw) 1298{ 1299 switch (hw->mac_type) { 1300 case e1000_80003es2lan: 1301 case e1000_82546: 1302 case e1000_82571: 1303 if (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1) 1304 return true; 1305 /* Fallthrough */ 1306 default: 1307 return false; 1308 } 1309} 1310 1311#ifndef CONFIG_E1000_NO_NVM 1312/****************************************************************************** 1313 * Reads the adapter's MAC address from the EEPROM 1314 * 1315 * hw - Struct containing variables accessed by shared code 1316 * enetaddr - buffering where the MAC address will be stored 1317 *****************************************************************************/ 1318static int e1000_read_mac_addr_from_eeprom(struct e1000_hw *hw, 1319 unsigned char enetaddr[6]) 1320{ 1321 uint16_t offset; 1322 uint16_t eeprom_data; 1323 int i; 1324 1325 for (i = 0; i < NODE_ADDRESS_SIZE; i += 2) { 1326 offset = i >> 1; 1327 if (e1000_read_eeprom(hw, offset, 1, &eeprom_data) < 0) { 1328 DEBUGOUT("EEPROM Read Error\n"); 1329 return -E1000_ERR_EEPROM; 1330 } 1331 enetaddr[i] = eeprom_data & 0xff; 1332 enetaddr[i + 1] = (eeprom_data >> 8) & 0xff; 1333 } 1334 1335 return 0; 1336} 1337 1338/****************************************************************************** 1339 * Reads the adapter's MAC address from the RAL/RAH registers 1340 * 1341 * hw - Struct containing variables accessed by shared code 1342 * enetaddr - buffering where the MAC address will be stored 1343 *****************************************************************************/ 1344static int e1000_read_mac_addr_from_regs(struct e1000_hw *hw, 1345 unsigned char enetaddr[6]) 1346{ 1347 uint16_t offset, tmp; 1348 uint32_t reg_data = 0; 1349 int i; 1350 1351 if (hw->mac_type != e1000_igb) 1352 return -E1000_ERR_MAC_TYPE; 1353 1354 for (i = 0; i < NODE_ADDRESS_SIZE; i += 2) { 1355 offset = i >> 1; 1356 1357 if (offset == 0) 1358 reg_data = E1000_READ_REG_ARRAY(hw, RA, 0); 1359 else if (offset == 1) 1360 reg_data >>= 16; 1361 else if (offset == 2) 1362 reg_data = E1000_READ_REG_ARRAY(hw, RA, 1); 1363 tmp = reg_data & 0xffff; 1364 1365 enetaddr[i] = tmp & 0xff; 1366 enetaddr[i + 1] = (tmp >> 8) & 0xff; 1367 } 1368 1369 return 0; 1370} 1371 1372/****************************************************************************** 1373 * Reads the adapter's MAC address from the EEPROM and inverts the LSB for the 1374 * second function of dual function devices 1375 * 1376 * hw - Struct containing variables accessed by shared code 1377 * enetaddr - buffering where the MAC address will be stored 1378 *****************************************************************************/ 1379static int e1000_read_mac_addr(struct e1000_hw *hw, unsigned char enetaddr[6]) 1380{ 1381 int ret_val; 1382 1383 if (hw->mac_type == e1000_igb) { 1384 /* i210 preloads MAC address into RAL/RAH registers */ 1385 ret_val = e1000_read_mac_addr_from_regs(hw, enetaddr); 1386 } else { 1387 ret_val = e1000_read_mac_addr_from_eeprom(hw, enetaddr); 1388 } 1389 if (ret_val) 1390 return ret_val; 1391 1392 /* Invert the last bit if this is the second device */ 1393 if (e1000_is_second_port(hw)) 1394 enetaddr[5] ^= 1; 1395 1396 return 0; 1397} 1398#endif 1399 1400/****************************************************************************** 1401 * Initializes receive address filters. 1402 * 1403 * hw - Struct containing variables accessed by shared code 1404 * 1405 * Places the MAC address in receive address register 0 and clears the rest 1406 * of the receive addresss registers. Clears the multicast table. Assumes 1407 * the receiver is in reset when the routine is called. 1408 *****************************************************************************/ 1409static void 1410e1000_init_rx_addrs(struct e1000_hw *hw, unsigned char enetaddr[6]) 1411{ 1412 uint32_t i; 1413 uint32_t addr_low; 1414 uint32_t addr_high; 1415 1416 DEBUGFUNC(); 1417 1418 /* Setup the receive address. */ 1419 DEBUGOUT("Programming MAC Address into RAR[0]\n"); 1420 addr_low = (enetaddr[0] | 1421 (enetaddr[1] << 8) | 1422 (enetaddr[2] << 16) | (enetaddr[3] << 24)); 1423 1424 addr_high = (enetaddr[4] | (enetaddr[5] << 8) | E1000_RAH_AV); 1425 1426 E1000_WRITE_REG_ARRAY(hw, RA, 0, addr_low); 1427 E1000_WRITE_REG_ARRAY(hw, RA, 1, addr_high); 1428 1429 /* Zero out the other 15 receive addresses. */ 1430 DEBUGOUT("Clearing RAR[1-15]\n"); 1431 for (i = 1; i < E1000_RAR_ENTRIES; i++) { 1432 E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0); 1433 E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0); 1434 } 1435} 1436 1437/****************************************************************************** 1438 * Clears the VLAN filer table 1439 * 1440 * hw - Struct containing variables accessed by shared code 1441 *****************************************************************************/ 1442static void 1443e1000_clear_vfta(struct e1000_hw *hw) 1444{ 1445 uint32_t offset; 1446 1447 for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) 1448 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, 0); 1449} 1450 1451/****************************************************************************** 1452 * Set the mac type member in the hw struct. 1453 * 1454 * hw - Struct containing variables accessed by shared code 1455 *****************************************************************************/ 1456int32_t 1457e1000_set_mac_type(struct e1000_hw *hw) 1458{ 1459 DEBUGFUNC(); 1460 1461 switch (hw->device_id) { 1462 case E1000_DEV_ID_82542: 1463 switch (hw->revision_id) { 1464 case E1000_82542_2_0_REV_ID: 1465 hw->mac_type = e1000_82542_rev2_0; 1466 break; 1467 case E1000_82542_2_1_REV_ID: 1468 hw->mac_type = e1000_82542_rev2_1; 1469 break; 1470 default: 1471 /* Invalid 82542 revision ID */ 1472 return -E1000_ERR_MAC_TYPE; 1473 } 1474 break; 1475 case E1000_DEV_ID_82543GC_FIBER: 1476 case E1000_DEV_ID_82543GC_COPPER: 1477 hw->mac_type = e1000_82543; 1478 break; 1479 case E1000_DEV_ID_82544EI_COPPER: 1480 case E1000_DEV_ID_82544EI_FIBER: 1481 case E1000_DEV_ID_82544GC_COPPER: 1482 case E1000_DEV_ID_82544GC_LOM: 1483 hw->mac_type = e1000_82544; 1484 break; 1485 case E1000_DEV_ID_82540EM: 1486 case E1000_DEV_ID_82540EM_LOM: 1487 case E1000_DEV_ID_82540EP: 1488 case E1000_DEV_ID_82540EP_LOM: 1489 case E1000_DEV_ID_82540EP_LP: 1490 hw->mac_type = e1000_82540; 1491 break; 1492 case E1000_DEV_ID_82545EM_COPPER: 1493 case E1000_DEV_ID_82545EM_FIBER: 1494 hw->mac_type = e1000_82545; 1495 break; 1496 case E1000_DEV_ID_82545GM_COPPER: 1497 case E1000_DEV_ID_82545GM_FIBER: 1498 case E1000_DEV_ID_82545GM_SERDES: 1499 hw->mac_type = e1000_82545_rev_3; 1500 break; 1501 case E1000_DEV_ID_82546EB_COPPER: 1502 case E1000_DEV_ID_82546EB_FIBER: 1503 case E1000_DEV_ID_82546EB_QUAD_COPPER: 1504 hw->mac_type = e1000_82546; 1505 break; 1506 case E1000_DEV_ID_82546GB_COPPER: 1507 case E1000_DEV_ID_82546GB_FIBER: 1508 case E1000_DEV_ID_82546GB_SERDES: 1509 case E1000_DEV_ID_82546GB_PCIE: 1510 case E1000_DEV_ID_82546GB_QUAD_COPPER: 1511 case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3: 1512 hw->mac_type = e1000_82546_rev_3; 1513 break; 1514 case E1000_DEV_ID_82541EI: 1515 case E1000_DEV_ID_82541EI_MOBILE: 1516 case E1000_DEV_ID_82541ER_LOM: 1517 hw->mac_type = e1000_82541; 1518 break; 1519 case E1000_DEV_ID_82541ER: 1520 case E1000_DEV_ID_82541GI: 1521 case E1000_DEV_ID_82541GI_LF: 1522 case E1000_DEV_ID_82541GI_MOBILE: 1523 hw->mac_type = e1000_82541_rev_2; 1524 break; 1525 case E1000_DEV_ID_82547EI: 1526 case E1000_DEV_ID_82547EI_MOBILE: 1527 hw->mac_type = e1000_82547; 1528 break; 1529 case E1000_DEV_ID_82547GI: 1530 hw->mac_type = e1000_82547_rev_2; 1531 break; 1532 case E1000_DEV_ID_82571EB_COPPER: 1533 case E1000_DEV_ID_82571EB_FIBER: 1534 case E1000_DEV_ID_82571EB_SERDES: 1535 case E1000_DEV_ID_82571EB_SERDES_DUAL: 1536 case E1000_DEV_ID_82571EB_SERDES_QUAD: 1537 case E1000_DEV_ID_82571EB_QUAD_COPPER: 1538 case E1000_DEV_ID_82571PT_QUAD_COPPER: 1539 case E1000_DEV_ID_82571EB_QUAD_FIBER: 1540 case E1000_DEV_ID_82571EB_QUAD_COPPER_LOWPROFILE: 1541 hw->mac_type = e1000_82571; 1542 break; 1543 case E1000_DEV_ID_82572EI_COPPER: 1544 case E1000_DEV_ID_82572EI_FIBER: 1545 case E1000_DEV_ID_82572EI_SERDES: 1546 case E1000_DEV_ID_82572EI: 1547 hw->mac_type = e1000_82572; 1548 break; 1549 case E1000_DEV_ID_82573E: 1550 case E1000_DEV_ID_82573E_IAMT: 1551 case E1000_DEV_ID_82573L: 1552 hw->mac_type = e1000_82573; 1553 break; 1554 case E1000_DEV_ID_82574L: 1555 hw->mac_type = e1000_82574; 1556 break; 1557 case E1000_DEV_ID_80003ES2LAN_COPPER_SPT: 1558 case E1000_DEV_ID_80003ES2LAN_SERDES_SPT: 1559 case E1000_DEV_ID_80003ES2LAN_COPPER_DPT: 1560 case E1000_DEV_ID_80003ES2LAN_SERDES_DPT: 1561 hw->mac_type = e1000_80003es2lan; 1562 break; 1563 case E1000_DEV_ID_ICH8_IGP_M_AMT: 1564 case E1000_DEV_ID_ICH8_IGP_AMT: 1565 case E1000_DEV_ID_ICH8_IGP_C: 1566 case E1000_DEV_ID_ICH8_IFE: 1567 case E1000_DEV_ID_ICH8_IFE_GT: 1568 case E1000_DEV_ID_ICH8_IFE_G: 1569 case E1000_DEV_ID_ICH8_IGP_M: 1570 hw->mac_type = e1000_ich8lan; 1571 break; 1572 case PCI_DEVICE_ID_INTEL_I210_UNPROGRAMMED: 1573 case PCI_DEVICE_ID_INTEL_I211_UNPROGRAMMED: 1574 case PCI_DEVICE_ID_INTEL_I210_COPPER: 1575 case PCI_DEVICE_ID_INTEL_I211_COPPER: 1576 case PCI_DEVICE_ID_INTEL_I210_COPPER_FLASHLESS: 1577 case PCI_DEVICE_ID_INTEL_I210_SERDES: 1578 case PCI_DEVICE_ID_INTEL_I210_SERDES_FLASHLESS: 1579 case PCI_DEVICE_ID_INTEL_I210_1000BASEKX: 1580 case PCI_DEVICE_ID_INTEL_I225_UNPROGRAMMED: 1581 case PCI_DEVICE_ID_INTEL_I225_IT: 1582 hw->mac_type = e1000_igb; 1583 break; 1584 default: 1585 /* Should never have loaded on this device */ 1586 return -E1000_ERR_MAC_TYPE; 1587 } 1588 return E1000_SUCCESS; 1589} 1590 1591/****************************************************************************** 1592 * Reset the transmit and receive units; mask and clear all interrupts. 1593 * 1594 * hw - Struct containing variables accessed by shared code 1595 *****************************************************************************/ 1596void 1597e1000_reset_hw(struct e1000_hw *hw) 1598{ 1599 uint32_t ctrl; 1600 uint32_t ctrl_ext; 1601 uint32_t manc; 1602 uint32_t pba = 0; 1603 uint32_t reg; 1604 1605 DEBUGFUNC(); 1606 1607 /* get the correct pba value for both PCI and PCIe*/ 1608 if (hw->mac_type < e1000_82571) 1609 pba = E1000_DEFAULT_PCI_PBA; 1610 else 1611 pba = E1000_DEFAULT_PCIE_PBA; 1612 1613 /* For 82542 (rev 2.0), disable MWI before issuing a device reset */ 1614 if (hw->mac_type == e1000_82542_rev2_0) { 1615 DEBUGOUT("Disabling MWI on 82542 rev 2.0\n"); 1616 dm_pci_write_config16(hw->pdev, PCI_COMMAND, 1617 hw->pci_cmd_word & ~PCI_COMMAND_INVALIDATE); 1618 } 1619 1620 /* Clear interrupt mask to stop board from generating interrupts */ 1621 DEBUGOUT("Masking off all interrupts\n"); 1622 if (hw->mac_type == e1000_igb) 1623 E1000_WRITE_REG(hw, I210_IAM, 0); 1624 E1000_WRITE_REG(hw, IMC, 0xffffffff); 1625 1626 /* Disable the Transmit and Receive units. Then delay to allow 1627 * any pending transactions to complete before we hit the MAC with 1628 * the global reset. 1629 */ 1630 E1000_WRITE_REG(hw, RCTL, 0); 1631 E1000_WRITE_REG(hw, TCTL, E1000_TCTL_PSP); 1632 E1000_WRITE_FLUSH(hw); 1633 1634 if (hw->mac_type == e1000_igb) { 1635 E1000_WRITE_REG(hw, RXPBS, I210_RXPBSIZE_DEFAULT); 1636 E1000_WRITE_REG(hw, TXPBS, I210_TXPBSIZE_DEFAULT); 1637 } 1638 1639 /* The tbi_compatibility_on Flag must be cleared when Rctl is cleared. */ 1640 hw->tbi_compatibility_on = false; 1641 1642 /* Delay to allow any outstanding PCI transactions to complete before 1643 * resetting the device 1644 */ 1645 mdelay(10); 1646 1647 /* Issue a global reset to the MAC. This will reset the chip's 1648 * transmit, receive, DMA, and link units. It will not effect 1649 * the current PCI configuration. The global reset bit is self- 1650 * clearing, and should clear within a microsecond. 1651 */ 1652 DEBUGOUT("Issuing a global reset to MAC\n"); 1653 ctrl = E1000_READ_REG(hw, CTRL); 1654 1655 E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_RST)); 1656 1657 /* Force a reload from the EEPROM if necessary */ 1658 if (hw->mac_type == e1000_igb) { 1659 mdelay(20); 1660 reg = E1000_READ_REG(hw, STATUS); 1661 if (reg & E1000_STATUS_PF_RST_DONE) 1662 DEBUGOUT("PF OK\n"); 1663 reg = E1000_READ_REG(hw, I210_EECD); 1664 if (reg & E1000_EECD_AUTO_RD) 1665 DEBUGOUT("EEC OK\n"); 1666 } else if (hw->mac_type < e1000_82540) { 1667 /* Wait for reset to complete */ 1668 udelay(10); 1669 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); 1670 ctrl_ext |= E1000_CTRL_EXT_EE_RST; 1671 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); 1672 E1000_WRITE_FLUSH(hw); 1673 /* Wait for EEPROM reload */ 1674 mdelay(2); 1675 } else { 1676 /* Wait for EEPROM reload (it happens automatically) */ 1677 mdelay(4); 1678 /* Dissable HW ARPs on ASF enabled adapters */ 1679 manc = E1000_READ_REG(hw, MANC); 1680 manc &= ~(E1000_MANC_ARP_EN); 1681 E1000_WRITE_REG(hw, MANC, manc); 1682 } 1683 1684 /* Clear interrupt mask to stop board from generating interrupts */ 1685 DEBUGOUT("Masking off all interrupts\n"); 1686 if (hw->mac_type == e1000_igb) 1687 E1000_WRITE_REG(hw, I210_IAM, 0); 1688 E1000_WRITE_REG(hw, IMC, 0xffffffff); 1689 1690 /* Clear any pending interrupt events. */ 1691 E1000_READ_REG(hw, ICR); 1692 1693 /* If MWI was previously enabled, reenable it. */ 1694 if (hw->mac_type == e1000_82542_rev2_0) { 1695 dm_pci_write_config16(hw->pdev, PCI_COMMAND, hw->pci_cmd_word); 1696 } 1697 if (hw->mac_type != e1000_igb) 1698 E1000_WRITE_REG(hw, PBA, pba); 1699} 1700 1701/****************************************************************************** 1702 * 1703 * Initialize a number of hardware-dependent bits 1704 * 1705 * hw: Struct containing variables accessed by shared code 1706 * 1707 * This function contains hardware limitation workarounds for PCI-E adapters 1708 * 1709 *****************************************************************************/ 1710static void 1711e1000_initialize_hardware_bits(struct e1000_hw *hw) 1712{ 1713 if ((hw->mac_type >= e1000_82571) && 1714 (!hw->initialize_hw_bits_disable)) { 1715 /* Settings common to all PCI-express silicon */ 1716 uint32_t reg_ctrl, reg_ctrl_ext; 1717 uint32_t reg_tarc0, reg_tarc1; 1718 uint32_t reg_tctl; 1719 uint32_t reg_txdctl, reg_txdctl1; 1720 1721 /* link autonegotiation/sync workarounds */ 1722 reg_tarc0 = E1000_READ_REG(hw, TARC0); 1723 reg_tarc0 &= ~((1 << 30)|(1 << 29)|(1 << 28)|(1 << 27)); 1724 1725 /* Enable not-done TX descriptor counting */ 1726 reg_txdctl = E1000_READ_REG(hw, TXDCTL); 1727 reg_txdctl |= E1000_TXDCTL_COUNT_DESC; 1728 E1000_WRITE_REG(hw, TXDCTL, reg_txdctl); 1729 1730 reg_txdctl1 = E1000_READ_REG(hw, TXDCTL1); 1731 reg_txdctl1 |= E1000_TXDCTL_COUNT_DESC; 1732 E1000_WRITE_REG(hw, TXDCTL1, reg_txdctl1); 1733 1734 1735 switch (hw->mac_type) { 1736 case e1000_igb: /* IGB is cool */ 1737 return; 1738 case e1000_82571: 1739 case e1000_82572: 1740 /* Clear PHY TX compatible mode bits */ 1741 reg_tarc1 = E1000_READ_REG(hw, TARC1); 1742 reg_tarc1 &= ~((1 << 30)|(1 << 29)); 1743 1744 /* link autonegotiation/sync workarounds */ 1745 reg_tarc0 |= ((1 << 26)|(1 << 25)|(1 << 24)|(1 << 23)); 1746 1747 /* TX ring control fixes */ 1748 reg_tarc1 |= ((1 << 26)|(1 << 25)|(1 << 24)); 1749 1750 /* Multiple read bit is reversed polarity */ 1751 reg_tctl = E1000_READ_REG(hw, TCTL); 1752 if (reg_tctl & E1000_TCTL_MULR) 1753 reg_tarc1 &= ~(1 << 28); 1754 else 1755 reg_tarc1 |= (1 << 28); 1756 1757 E1000_WRITE_REG(hw, TARC1, reg_tarc1); 1758 break; 1759 case e1000_82573: 1760 case e1000_82574: 1761 reg_ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); 1762 reg_ctrl_ext &= ~(1 << 23); 1763 reg_ctrl_ext |= (1 << 22); 1764 1765 /* TX byte count fix */ 1766 reg_ctrl = E1000_READ_REG(hw, CTRL); 1767 reg_ctrl &= ~(1 << 29); 1768 1769 E1000_WRITE_REG(hw, CTRL_EXT, reg_ctrl_ext); 1770 E1000_WRITE_REG(hw, CTRL, reg_ctrl); 1771 break; 1772 case e1000_80003es2lan: 1773 /* improve small packet performace for fiber/serdes */ 1774 if ((hw->media_type == e1000_media_type_fiber) 1775 || (hw->media_type == 1776 e1000_media_type_internal_serdes)) { 1777 reg_tarc0 &= ~(1 << 20); 1778 } 1779 1780 /* Multiple read bit is reversed polarity */ 1781 reg_tctl = E1000_READ_REG(hw, TCTL); 1782 reg_tarc1 = E1000_READ_REG(hw, TARC1); 1783 if (reg_tctl & E1000_TCTL_MULR) 1784 reg_tarc1 &= ~(1 << 28); 1785 else 1786 reg_tarc1 |= (1 << 28); 1787 1788 E1000_WRITE_REG(hw, TARC1, reg_tarc1); 1789 break; 1790 case e1000_ich8lan: 1791 /* Reduce concurrent DMA requests to 3 from 4 */ 1792 if ((hw->revision_id < 3) || 1793 ((hw->device_id != E1000_DEV_ID_ICH8_IGP_M_AMT) && 1794 (hw->device_id != E1000_DEV_ID_ICH8_IGP_M))) 1795 reg_tarc0 |= ((1 << 29)|(1 << 28)); 1796 1797 reg_ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); 1798 reg_ctrl_ext |= (1 << 22); 1799 E1000_WRITE_REG(hw, CTRL_EXT, reg_ctrl_ext); 1800 1801 /* workaround TX hang with TSO=on */ 1802 reg_tarc0 |= ((1 << 27)|(1 << 26)|(1 << 24)|(1 << 23)); 1803 1804 /* Multiple read bit is reversed polarity */ 1805 reg_tctl = E1000_READ_REG(hw, TCTL); 1806 reg_tarc1 = E1000_READ_REG(hw, TARC1); 1807 if (reg_tctl & E1000_TCTL_MULR) 1808 reg_tarc1 &= ~(1 << 28); 1809 else 1810 reg_tarc1 |= (1 << 28); 1811 1812 /* workaround TX hang with TSO=on */ 1813 reg_tarc1 |= ((1 << 30)|(1 << 26)|(1 << 24)); 1814 1815 E1000_WRITE_REG(hw, TARC1, reg_tarc1); 1816 break; 1817 default: 1818 break; 1819 } 1820 1821 E1000_WRITE_REG(hw, TARC0, reg_tarc0); 1822 } 1823} 1824 1825/****************************************************************************** 1826 * Performs basic configuration of the adapter. 1827 * 1828 * hw - Struct containing variables accessed by shared code 1829 * 1830 * Assumes that the controller has previously been reset and is in a 1831 * post-reset uninitialized state. Initializes the receive address registers, 1832 * multicast table, and VLAN filter table. Calls routines to setup link 1833 * configuration and flow control settings. Clears all on-chip counters. Leaves 1834 * the transmit and receive units disabled and uninitialized. 1835 *****************************************************************************/ 1836static int 1837e1000_init_hw(struct e1000_hw *hw, unsigned char enetaddr[6]) 1838{ 1839 uint32_t ctrl; 1840 uint32_t i; 1841 int32_t ret_val; 1842 uint16_t pcix_cmd_word; 1843 uint16_t pcix_stat_hi_word; 1844 uint16_t cmd_mmrbc; 1845 uint16_t stat_mmrbc; 1846 uint32_t mta_size; 1847 uint32_t reg_data; 1848 uint32_t ctrl_ext; 1849 DEBUGFUNC(); 1850 /* force full DMA clock frequency for 10/100 on ICH8 A0-B0 */ 1851 if ((hw->mac_type == e1000_ich8lan) && 1852 ((hw->revision_id < 3) || 1853 ((hw->device_id != E1000_DEV_ID_ICH8_IGP_M_AMT) && 1854 (hw->device_id != E1000_DEV_ID_ICH8_IGP_M)))) { 1855 reg_data = E1000_READ_REG(hw, STATUS); 1856 reg_data &= ~0x80000000; 1857 E1000_WRITE_REG(hw, STATUS, reg_data); 1858 } 1859 /* Do not need initialize Identification LED */ 1860 1861 /* Set the media type and TBI compatibility */ 1862 e1000_set_media_type(hw); 1863 1864 /* Must be called after e1000_set_media_type 1865 * because media_type is used */ 1866 e1000_initialize_hardware_bits(hw); 1867 1868 /* Disabling VLAN filtering. */ 1869 DEBUGOUT("Initializing the IEEE VLAN\n"); 1870 /* VET hardcoded to standard value and VFTA removed in ICH8 LAN */ 1871 if (hw->mac_type != e1000_ich8lan) { 1872 if (hw->mac_type < e1000_82545_rev_3) 1873 E1000_WRITE_REG(hw, VET, 0); 1874 e1000_clear_vfta(hw); 1875 } 1876 1877 /* For 82542 (rev 2.0), disable MWI and put the receiver into reset */ 1878 if (hw->mac_type == e1000_82542_rev2_0) { 1879 DEBUGOUT("Disabling MWI on 82542 rev 2.0\n"); 1880 dm_pci_write_config16(hw->pdev, PCI_COMMAND, 1881 hw-> 1882 pci_cmd_word & ~PCI_COMMAND_INVALIDATE); 1883 E1000_WRITE_REG(hw, RCTL, E1000_RCTL_RST); 1884 E1000_WRITE_FLUSH(hw); 1885 mdelay(5); 1886 } 1887 1888 /* Setup the receive address. This involves initializing all of the Receive 1889 * Address Registers (RARs 0 - 15). 1890 */ 1891 e1000_init_rx_addrs(hw, enetaddr); 1892 1893 /* For 82542 (rev 2.0), take the receiver out of reset and enable MWI */ 1894 if (hw->mac_type == e1000_82542_rev2_0) { 1895 E1000_WRITE_REG(hw, RCTL, 0); 1896 E1000_WRITE_FLUSH(hw); 1897 mdelay(1); 1898 dm_pci_write_config16(hw->pdev, PCI_COMMAND, hw->pci_cmd_word); 1899 } 1900 1901 /* Zero out the Multicast HASH table */ 1902 DEBUGOUT("Zeroing the MTA\n"); 1903 mta_size = E1000_MC_TBL_SIZE; 1904 if (hw->mac_type == e1000_ich8lan) 1905 mta_size = E1000_MC_TBL_SIZE_ICH8LAN; 1906 for (i = 0; i < mta_size; i++) { 1907 E1000_WRITE_REG_ARRAY(hw, MTA, i, 0); 1908 /* use write flush to prevent Memory Write Block (MWB) from 1909 * occuring when accessing our register space */ 1910 E1000_WRITE_FLUSH(hw); 1911 } 1912 1913 switch (hw->mac_type) { 1914 case e1000_82545_rev_3: 1915 case e1000_82546_rev_3: 1916 case e1000_igb: 1917 break; 1918 default: 1919 /* Workaround for PCI-X problem when BIOS sets MMRBC incorrectly. */ 1920 if (hw->bus_type == e1000_bus_type_pcix) { 1921 dm_pci_read_config16(hw->pdev, PCIX_COMMAND_REGISTER, 1922 &pcix_cmd_word); 1923 dm_pci_read_config16(hw->pdev, PCIX_STATUS_REGISTER_HI, 1924 &pcix_stat_hi_word); 1925 cmd_mmrbc = 1926 (pcix_cmd_word & PCIX_COMMAND_MMRBC_MASK) >> 1927 PCIX_COMMAND_MMRBC_SHIFT; 1928 stat_mmrbc = 1929 (pcix_stat_hi_word & PCIX_STATUS_HI_MMRBC_MASK) >> 1930 PCIX_STATUS_HI_MMRBC_SHIFT; 1931 if (stat_mmrbc == PCIX_STATUS_HI_MMRBC_4K) 1932 stat_mmrbc = PCIX_STATUS_HI_MMRBC_2K; 1933 if (cmd_mmrbc > stat_mmrbc) { 1934 pcix_cmd_word &= ~PCIX_COMMAND_MMRBC_MASK; 1935 pcix_cmd_word |= stat_mmrbc << PCIX_COMMAND_MMRBC_SHIFT; 1936 dm_pci_write_config16(hw->pdev, PCIX_COMMAND_REGISTER, 1937 pcix_cmd_word); 1938 } 1939 } 1940 break; 1941 } 1942 1943 /* More time needed for PHY to initialize */ 1944 if (hw->mac_type == e1000_ich8lan) 1945 mdelay(15); 1946 if (hw->mac_type == e1000_igb) 1947 mdelay(15); 1948 1949 /* Call a subroutine to configure the link and setup flow control. */ 1950 ret_val = e1000_setup_link(hw); 1951 1952 /* Set the transmit descriptor write-back policy */ 1953 if (hw->mac_type > e1000_82544) { 1954 ctrl = E1000_READ_REG(hw, TXDCTL); 1955 ctrl = 1956 (ctrl & ~E1000_TXDCTL_WTHRESH) | 1957 E1000_TXDCTL_FULL_TX_DESC_WB; 1958 E1000_WRITE_REG(hw, TXDCTL, ctrl); 1959 } 1960 1961 /* Set the receive descriptor write back policy */ 1962 if (hw->mac_type >= e1000_82571) { 1963 ctrl = E1000_READ_REG(hw, RXDCTL); 1964 ctrl = 1965 (ctrl & ~E1000_RXDCTL_WTHRESH) | 1966 E1000_RXDCTL_FULL_RX_DESC_WB; 1967 E1000_WRITE_REG(hw, RXDCTL, ctrl); 1968 } 1969 1970 switch (hw->mac_type) { 1971 default: 1972 break; 1973 case e1000_80003es2lan: 1974 /* Enable retransmit on late collisions */ 1975 reg_data = E1000_READ_REG(hw, TCTL); 1976 reg_data |= E1000_TCTL_RTLC; 1977 E1000_WRITE_REG(hw, TCTL, reg_data); 1978 1979 /* Configure Gigabit Carry Extend Padding */ 1980 reg_data = E1000_READ_REG(hw, TCTL_EXT); 1981 reg_data &= ~E1000_TCTL_EXT_GCEX_MASK; 1982 reg_data |= DEFAULT_80003ES2LAN_TCTL_EXT_GCEX; 1983 E1000_WRITE_REG(hw, TCTL_EXT, reg_data); 1984 1985 /* Configure Transmit Inter-Packet Gap */ 1986 reg_data = E1000_READ_REG(hw, TIPG); 1987 reg_data &= ~E1000_TIPG_IPGT_MASK; 1988 reg_data |= DEFAULT_80003ES2LAN_TIPG_IPGT_1000; 1989 E1000_WRITE_REG(hw, TIPG, reg_data); 1990 1991 reg_data = E1000_READ_REG_ARRAY(hw, FFLT, 0x0001); 1992 reg_data &= ~0x00100000; 1993 E1000_WRITE_REG_ARRAY(hw, FFLT, 0x0001, reg_data); 1994 /* Fall through */ 1995 case e1000_82571: 1996 case e1000_82572: 1997 case e1000_ich8lan: 1998 ctrl = E1000_READ_REG(hw, TXDCTL1); 1999 ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH) 2000 | E1000_TXDCTL_FULL_TX_DESC_WB; 2001 E1000_WRITE_REG(hw, TXDCTL1, ctrl); 2002 break; 2003 case e1000_82573: 2004 case e1000_82574: 2005 reg_data = E1000_READ_REG(hw, GCR); 2006 reg_data |= E1000_GCR_L1_ACT_WITHOUT_L0S_RX; 2007 E1000_WRITE_REG(hw, GCR, reg_data); 2008 case e1000_igb: 2009 break; 2010 } 2011 2012 if (hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER || 2013 hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3) { 2014 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); 2015 /* Relaxed ordering must be disabled to avoid a parity 2016 * error crash in a PCI slot. */ 2017 ctrl_ext |= E1000_CTRL_EXT_RO_DIS; 2018 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); 2019 } 2020 2021 return ret_val; 2022} 2023 2024/****************************************************************************** 2025 * Configures flow control and link settings. 2026 * 2027 * hw - Struct containing variables accessed by shared code 2028 * 2029 * Determines which flow control settings to use. Calls the apropriate media- 2030 * specific link configuration function. Configures the flow control settings. 2031 * Assuming the adapter has a valid link partner, a valid link should be 2032 * established. Assumes the hardware has previously been reset and the 2033 * transmitter and receiver are not enabled. 2034 *****************************************************************************/ 2035static int 2036e1000_setup_link(struct e1000_hw *hw) 2037{ 2038 int32_t ret_val; 2039#ifndef CONFIG_E1000_NO_NVM 2040 uint32_t ctrl_ext; 2041 uint16_t eeprom_data; 2042#endif 2043 2044 DEBUGFUNC(); 2045 2046 /* In the case of the phy reset being blocked, we already have a link. 2047 * We do not have to set it up again. */ 2048 if (e1000_check_phy_reset_block(hw)) 2049 return E1000_SUCCESS; 2050 2051#ifndef CONFIG_E1000_NO_NVM 2052 /* Read and store word 0x0F of the EEPROM. This word contains bits 2053 * that determine the hardware's default PAUSE (flow control) mode, 2054 * a bit that determines whether the HW defaults to enabling or 2055 * disabling auto-negotiation, and the direction of the 2056 * SW defined pins. If there is no SW over-ride of the flow 2057 * control setting, then the variable hw->fc will 2058 * be initialized based on a value in the EEPROM. 2059 */ 2060 if (e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG, 1, 2061 &eeprom_data) < 0) { 2062 DEBUGOUT("EEPROM Read Error\n"); 2063 return -E1000_ERR_EEPROM; 2064 } 2065#endif 2066 if (hw->fc == e1000_fc_default) { 2067 switch (hw->mac_type) { 2068 case e1000_ich8lan: 2069 case e1000_82573: 2070 case e1000_82574: 2071 case e1000_igb: 2072 hw->fc = e1000_fc_full; 2073 break; 2074 default: 2075#ifndef CONFIG_E1000_NO_NVM 2076 ret_val = e1000_read_eeprom(hw, 2077 EEPROM_INIT_CONTROL2_REG, 1, &eeprom_data); 2078 if (ret_val) { 2079 DEBUGOUT("EEPROM Read Error\n"); 2080 return -E1000_ERR_EEPROM; 2081 } 2082 if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == 0) 2083 hw->fc = e1000_fc_none; 2084 else if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == 2085 EEPROM_WORD0F_ASM_DIR) 2086 hw->fc = e1000_fc_tx_pause; 2087 else 2088#endif 2089 hw->fc = e1000_fc_full; 2090 break; 2091 } 2092 } 2093 2094 /* We want to save off the original Flow Control configuration just 2095 * in case we get disconnected and then reconnected into a different 2096 * hub or switch with different Flow Control capabilities. 2097 */ 2098 if (hw->mac_type == e1000_82542_rev2_0) 2099 hw->fc &= (~e1000_fc_tx_pause); 2100 2101 if ((hw->mac_type < e1000_82543) && (hw->report_tx_early == 1)) 2102 hw->fc &= (~e1000_fc_rx_pause); 2103 2104 hw->original_fc = hw->fc; 2105 2106 DEBUGOUT("After fix-ups FlowControl is now = %x\n", hw->fc); 2107 2108#ifndef CONFIG_E1000_NO_NVM 2109 /* Take the 4 bits from EEPROM word 0x0F that determine the initial 2110 * polarity value for the SW controlled pins, and setup the 2111 * Extended Device Control reg with that info. 2112 * This is needed because one of the SW controlled pins is used for 2113 * signal detection. So this should be done before e1000_setup_pcs_link() 2114 * or e1000_phy_setup() is called. 2115 */ 2116 if (hw->mac_type == e1000_82543) { 2117 ctrl_ext = ((eeprom_data & EEPROM_WORD0F_SWPDIO_EXT) << 2118 SWDPIO__EXT_SHIFT); 2119 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); 2120 } 2121#endif 2122 2123 /* Call the necessary subroutine to configure the link. */ 2124 ret_val = (hw->media_type == e1000_media_type_fiber) ? 2125 e1000_setup_fiber_link(hw) : e1000_setup_copper_link(hw); 2126 if (ret_val < 0) { 2127 return ret_val; 2128 } 2129 2130 /* Initialize the flow control address, type, and PAUSE timer 2131 * registers to their default values. This is done even if flow 2132 * control is disabled, because it does not hurt anything to 2133 * initialize these registers. 2134 */ 2135 DEBUGOUT("Initializing the Flow Control address, type" 2136 "and timer regs\n"); 2137 2138 /* FCAL/H and FCT are hardcoded to standard values in e1000_ich8lan. */ 2139 if (hw->mac_type != e1000_ich8lan) { 2140 E1000_WRITE_REG(hw, FCT, FLOW_CONTROL_TYPE); 2141 E1000_WRITE_REG(hw, FCAH, FLOW_CONTROL_ADDRESS_HIGH); 2142 E1000_WRITE_REG(hw, FCAL, FLOW_CONTROL_ADDRESS_LOW); 2143 } 2144 2145 E1000_WRITE_REG(hw, FCTTV, hw->fc_pause_time); 2146 2147 /* Set the flow control receive threshold registers. Normally, 2148 * these registers will be set to a default threshold that may be 2149 * adjusted later by the driver's runtime code. However, if the 2150 * ability to transmit pause frames in not enabled, then these 2151 * registers will be set to 0. 2152 */ 2153 if (!(hw->fc & e1000_fc_tx_pause)) { 2154 E1000_WRITE_REG(hw, FCRTL, 0); 2155 E1000_WRITE_REG(hw, FCRTH, 0); 2156 } else { 2157 /* We need to set up the Receive Threshold high and low water marks 2158 * as well as (optionally) enabling the transmission of XON frames. 2159 */ 2160 if (hw->fc_send_xon) { 2161 E1000_WRITE_REG(hw, FCRTL, 2162 (hw->fc_low_water | E1000_FCRTL_XONE)); 2163 E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water); 2164 } else { 2165 E1000_WRITE_REG(hw, FCRTL, hw->fc_low_water); 2166 E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water); 2167 } 2168 } 2169 return ret_val; 2170} 2171 2172/****************************************************************************** 2173 * Sets up link for a fiber based adapter 2174 * 2175 * hw - Struct containing variables accessed by shared code 2176 * 2177 * Manipulates Physical Coding Sublayer functions in order to configure 2178 * link. Assumes the hardware has been previously reset and the transmitter 2179 * and receiver are not enabled. 2180 *****************************************************************************/ 2181static int 2182e1000_setup_fiber_link(struct e1000_hw *hw) 2183{ 2184 uint32_t ctrl; 2185 uint32_t status; 2186 uint32_t txcw = 0; 2187 uint32_t i; 2188 uint32_t signal; 2189 int32_t ret_val; 2190 2191 DEBUGFUNC(); 2192 /* On adapters with a MAC newer that 82544, SW Defineable pin 1 will be 2193 * set when the optics detect a signal. On older adapters, it will be 2194 * cleared when there is a signal 2195 */ 2196 ctrl = E1000_READ_REG(hw, CTRL); 2197 if ((hw->mac_type > e1000_82544) && !(ctrl & E1000_CTRL_ILOS)) 2198 signal = E1000_CTRL_SWDPIN1; 2199 else 2200 signal = 0; 2201 2202 printf("signal for %s is %x (ctrl %08x)!!!!\n", hw->name, signal, 2203 ctrl); 2204 /* Take the link out of reset */ 2205 ctrl &= ~(E1000_CTRL_LRST); 2206 2207 e1000_config_collision_dist(hw); 2208 2209 /* Check for a software override of the flow control settings, and setup 2210 * the device accordingly. If auto-negotiation is enabled, then software 2211 * will have to set the "PAUSE" bits to the correct value in the Tranmsit 2212 * Config Word Register (TXCW) and re-start auto-negotiation. However, if 2213 * auto-negotiation is disabled, then software will have to manually 2214 * configure the two flow control enable bits in the CTRL register. 2215 * 2216 * The possible values of the "fc" parameter are: 2217 * 0: Flow control is completely disabled 2218 * 1: Rx flow control is enabled (we can receive pause frames, but 2219 * not send pause frames). 2220 * 2: Tx flow control is enabled (we can send pause frames but we do 2221 * not support receiving pause frames). 2222 * 3: Both Rx and TX flow control (symmetric) are enabled. 2223 */ 2224 switch (hw->fc) { 2225 case e1000_fc_none: 2226 /* Flow control is completely disabled by a software over-ride. */ 2227 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD); 2228 break; 2229 case e1000_fc_rx_pause: 2230 /* RX Flow control is enabled and TX Flow control is disabled by a 2231 * software over-ride. Since there really isn't a way to advertise 2232 * that we are capable of RX Pause ONLY, we will advertise that we 2233 * support both symmetric and asymmetric RX PAUSE. Later, we will 2234 * disable the adapter's ability to send PAUSE frames. 2235 */ 2236 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK); 2237 break; 2238 case e1000_fc_tx_pause: 2239 /* TX Flow control is enabled, and RX Flow control is disabled, by a 2240 * software over-ride. 2241 */ 2242 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR); 2243 break; 2244 case e1000_fc_full: 2245 /* Flow control (both RX and TX) is enabled by a software over-ride. */ 2246 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK); 2247 break; 2248 default: 2249 DEBUGOUT("Flow control param set incorrectly\n"); 2250 return -E1000_ERR_CONFIG; 2251 break; 2252 } 2253 2254 /* Since auto-negotiation is enabled, take the link out of reset (the link 2255 * will be in reset, because we previously reset the chip). This will 2256 * restart auto-negotiation. If auto-neogtiation is successful then the 2257 * link-up status bit will be set and the flow control enable bits (RFCE 2258 * and TFCE) will be set according to their negotiated value. 2259 */ 2260 DEBUGOUT("Auto-negotiation enabled (%#x)\n", txcw); 2261 2262 E1000_WRITE_REG(hw, TXCW, txcw); 2263 E1000_WRITE_REG(hw, CTRL, ctrl); 2264 E1000_WRITE_FLUSH(hw); 2265 2266 hw->txcw = txcw; 2267 mdelay(1); 2268 2269 /* If we have a signal (the cable is plugged in) then poll for a "Link-Up" 2270 * indication in the Device Status Register. Time-out if a link isn't 2271 * seen in 500 milliseconds seconds (Auto-negotiation should complete in 2272 * less than 500 milliseconds even if the other end is doing it in SW). 2273 */ 2274 if ((E1000_READ_REG(hw, CTRL) & E1000_CTRL_SWDPIN1) == signal) { 2275 DEBUGOUT("Looking for Link\n"); 2276 for (i = 0; i < (LINK_UP_TIMEOUT / 10); i++) { 2277 mdelay(10); 2278 status = E1000_READ_REG(hw, STATUS); 2279 if (status & E1000_STATUS_LU) 2280 break; 2281 } 2282 if (i == (LINK_UP_TIMEOUT / 10)) { 2283 /* AutoNeg failed to achieve a link, so we'll call 2284 * e1000_check_for_link. This routine will force the link up if we 2285 * detect a signal. This will allow us to communicate with 2286 * non-autonegotiating link partners. 2287 */ 2288 DEBUGOUT("Never got a valid link from auto-neg!!!\n"); 2289 hw->autoneg_failed = 1; 2290 ret_val = e1000_check_for_link(hw); 2291 if (ret_val < 0) { 2292 DEBUGOUT("Error while checking for link\n"); 2293 return ret_val; 2294 } 2295 hw->autoneg_failed = 0; 2296 } else { 2297 hw->autoneg_failed = 0; 2298 DEBUGOUT("Valid Link Found\n"); 2299 } 2300 } else { 2301 DEBUGOUT("No Signal Detected\n"); 2302 return -E1000_ERR_NOLINK; 2303 } 2304 return 0; 2305} 2306 2307/****************************************************************************** 2308* Make sure we have a valid PHY and change PHY mode before link setup. 2309* 2310* hw - Struct containing variables accessed by shared code 2311******************************************************************************/ 2312static int32_t 2313e1000_copper_link_preconfig(struct e1000_hw *hw) 2314{ 2315 uint32_t ctrl; 2316 int32_t ret_val; 2317 uint16_t phy_data; 2318 2319 DEBUGFUNC(); 2320 2321 ctrl = E1000_READ_REG(hw, CTRL); 2322 /* With 82543, we need to force speed and duplex on the MAC equal to what 2323 * the PHY speed and duplex configuration is. In addition, we need to 2324 * perform a hardware reset on the PHY to take it out of reset. 2325 */ 2326 if (hw->mac_type > e1000_82543) { 2327 ctrl |= E1000_CTRL_SLU; 2328 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 2329 E1000_WRITE_REG(hw, CTRL, ctrl); 2330 } else { 2331 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX 2332 | E1000_CTRL_SLU); 2333 E1000_WRITE_REG(hw, CTRL, ctrl); 2334 ret_val = e1000_phy_hw_reset(hw); 2335 if (ret_val) 2336 return ret_val; 2337 } 2338 2339 /* Make sure we have a valid PHY */ 2340 ret_val = e1000_detect_gig_phy(hw); 2341 if (ret_val) { 2342 DEBUGOUT("Error, did not detect valid phy.\n"); 2343 return ret_val; 2344 } 2345 DEBUGOUT("Phy ID = %x\n", hw->phy_id); 2346 2347 /* Set PHY to class A mode (if necessary) */ 2348 ret_val = e1000_set_phy_mode(hw); 2349 if (ret_val) 2350 return ret_val; 2351 if ((hw->mac_type == e1000_82545_rev_3) || 2352 (hw->mac_type == e1000_82546_rev_3)) { 2353 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, 2354 &phy_data); 2355 phy_data |= 0x00000008; 2356 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, 2357 phy_data); 2358 } 2359 2360 if (hw->mac_type <= e1000_82543 || 2361 hw->mac_type == e1000_82541 || hw->mac_type == e1000_82547 || 2362 hw->mac_type == e1000_82541_rev_2 2363 || hw->mac_type == e1000_82547_rev_2) 2364 hw->phy_reset_disable = false; 2365 2366 return E1000_SUCCESS; 2367} 2368 2369/***************************************************************************** 2370 * 2371 * This function sets the lplu state according to the active flag. When 2372 * activating lplu this function also disables smart speed and vise versa. 2373 * lplu will not be activated unless the device autonegotiation advertisment 2374 * meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes. 2375 * hw: Struct containing variables accessed by shared code 2376 * active - true to enable lplu false to disable lplu. 2377 * 2378 * returns: - E1000_ERR_PHY if fail to read/write the PHY 2379 * E1000_SUCCESS at any other case. 2380 * 2381 ****************************************************************************/ 2382 2383static int32_t 2384e1000_set_d3_lplu_state(struct e1000_hw *hw, bool active) 2385{ 2386 uint32_t phy_ctrl = 0; 2387 int32_t ret_val; 2388 uint16_t phy_data; 2389 DEBUGFUNC(); 2390 2391 if (hw->phy_type != e1000_phy_igp && hw->phy_type != e1000_phy_igp_2 2392 && hw->phy_type != e1000_phy_igp_3) 2393 return E1000_SUCCESS; 2394 2395 /* During driver activity LPLU should not be used or it will attain link 2396 * from the lowest speeds starting from 10Mbps. The capability is used 2397 * for Dx transitions and states */ 2398 if (hw->mac_type == e1000_82541_rev_2 2399 || hw->mac_type == e1000_82547_rev_2) { 2400 ret_val = e1000_read_phy_reg(hw, IGP01E1000_GMII_FIFO, 2401 &phy_data); 2402 if (ret_val) 2403 return ret_val; 2404 } else if (hw->mac_type == e1000_ich8lan) { 2405 /* MAC writes into PHY register based on the state transition 2406 * and start auto-negotiation. SW driver can overwrite the 2407 * settings in CSR PHY power control E1000_PHY_CTRL register. */ 2408 phy_ctrl = E1000_READ_REG(hw, PHY_CTRL); 2409 } else { 2410 ret_val = e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, 2411 &phy_data); 2412 if (ret_val) 2413 return ret_val; 2414 } 2415 2416 if (!active) { 2417 if (hw->mac_type == e1000_82541_rev_2 || 2418 hw->mac_type == e1000_82547_rev_2) { 2419 phy_data &= ~IGP01E1000_GMII_FLEX_SPD; 2420 ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO, 2421 phy_data); 2422 if (ret_val) 2423 return ret_val; 2424 } else { 2425 if (hw->mac_type == e1000_ich8lan) { 2426 phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU; 2427 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl); 2428 } else { 2429 phy_data &= ~IGP02E1000_PM_D3_LPLU; 2430 ret_val = e1000_write_phy_reg(hw, 2431 IGP02E1000_PHY_POWER_MGMT, phy_data); 2432 if (ret_val) 2433 return ret_val; 2434 } 2435 } 2436 2437 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used during 2438 * Dx states where the power conservation is most important. During 2439 * driver activity we should enable SmartSpeed, so performance is 2440 * maintained. */ 2441 if (hw->smart_speed == e1000_smart_speed_on) { 2442 ret_val = e1000_read_phy_reg(hw, 2443 IGP01E1000_PHY_PORT_CONFIG, &phy_data); 2444 if (ret_val) 2445 return ret_val; 2446 2447 phy_data |= IGP01E1000_PSCFR_SMART_SPEED; 2448 ret_val = e1000_write_phy_reg(hw, 2449 IGP01E1000_PHY_PORT_CONFIG, phy_data); 2450 if (ret_val) 2451 return ret_val; 2452 } else if (hw->smart_speed == e1000_smart_speed_off) { 2453 ret_val = e1000_read_phy_reg(hw, 2454 IGP01E1000_PHY_PORT_CONFIG, &phy_data); 2455 if (ret_val) 2456 return ret_val; 2457 2458 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; 2459 ret_val = e1000_write_phy_reg(hw, 2460 IGP01E1000_PHY_PORT_CONFIG, phy_data); 2461 if (ret_val) 2462 return ret_val; 2463 } 2464 2465 } else if ((hw->autoneg_advertised == AUTONEG_ADVERTISE_SPEED_DEFAULT) 2466 || (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_ALL) || 2467 (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_100_ALL)) { 2468 2469 if (hw->mac_type == e1000_82541_rev_2 || 2470 hw->mac_type == e1000_82547_rev_2) { 2471 phy_data |= IGP01E1000_GMII_FLEX_SPD; 2472 ret_val = e1000_write_phy_reg(hw, 2473 IGP01E1000_GMII_FIFO, phy_data); 2474 if (ret_val) 2475 return ret_val; 2476 } else { 2477 if (hw->mac_type == e1000_ich8lan) { 2478 phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU; 2479 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl); 2480 } else { 2481 phy_data |= IGP02E1000_PM_D3_LPLU; 2482 ret_val = e1000_write_phy_reg(hw, 2483 IGP02E1000_PHY_POWER_MGMT, phy_data); 2484 if (ret_val) 2485 return ret_val; 2486 } 2487 } 2488 2489 /* When LPLU is enabled we should disable SmartSpeed */ 2490 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 2491 &phy_data); 2492 if (ret_val) 2493 return ret_val; 2494 2495 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; 2496 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 2497 phy_data); 2498 if (ret_val) 2499 return ret_val; 2500 } 2501 return E1000_SUCCESS; 2502} 2503 2504/***************************************************************************** 2505 * 2506 * This function sets the lplu d0 state according to the active flag. When 2507 * activating lplu this function also disables smart speed and vise versa. 2508 * lplu will not be activated unless the device autonegotiation advertisment 2509 * meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes. 2510 * hw: Struct containing variables accessed by shared code 2511 * active - true to enable lplu false to disable lplu. 2512 * 2513 * returns: - E1000_ERR_PHY if fail to read/write the PHY 2514 * E1000_SUCCESS at any other case. 2515 * 2516 ****************************************************************************/ 2517 2518static int32_t 2519e1000_set_d0_lplu_state(struct e1000_hw *hw, bool active) 2520{ 2521 uint32_t phy_ctrl = 0; 2522 int32_t ret_val; 2523 uint16_t phy_data; 2524 DEBUGFUNC(); 2525 2526 if (hw->mac_type <= e1000_82547_rev_2) 2527 return E1000_SUCCESS; 2528 2529 if (hw->mac_type == e1000_ich8lan) { 2530 phy_ctrl = E1000_READ_REG(hw, PHY_CTRL); 2531 } else if (hw->mac_type == e1000_igb) { 2532 phy_ctrl = E1000_READ_REG(hw, I210_PHY_CTRL); 2533 } else { 2534 ret_val = e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, 2535 &phy_data); 2536 if (ret_val) 2537 return ret_val; 2538 } 2539 2540 if (!active) { 2541 if (hw->mac_type == e1000_ich8lan) { 2542 phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU; 2543 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl); 2544 } else if (hw->mac_type == e1000_igb) { 2545 phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU; 2546 E1000_WRITE_REG(hw, I210_PHY_CTRL, phy_ctrl); 2547 } else { 2548 phy_data &= ~IGP02E1000_PM_D0_LPLU; 2549 ret_val = e1000_write_phy_reg(hw, 2550 IGP02E1000_PHY_POWER_MGMT, phy_data); 2551 if (ret_val) 2552 return ret_val; 2553 } 2554 2555 if (hw->mac_type == e1000_igb) 2556 return E1000_SUCCESS; 2557 2558 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used during 2559 * Dx states where the power conservation is most important. During 2560 * driver activity we should enable SmartSpeed, so performance is 2561 * maintained. */ 2562 if (hw->smart_speed == e1000_smart_speed_on) { 2563 ret_val = e1000_read_phy_reg(hw, 2564 IGP01E1000_PHY_PORT_CONFIG, &phy_data); 2565 if (ret_val) 2566 return ret_val; 2567 2568 phy_data |= IGP01E1000_PSCFR_SMART_SPEED; 2569 ret_val = e1000_write_phy_reg(hw, 2570 IGP01E1000_PHY_PORT_CONFIG, phy_data); 2571 if (ret_val) 2572 return ret_val; 2573 } else if (hw->smart_speed == e1000_smart_speed_off) { 2574 ret_val = e1000_read_phy_reg(hw, 2575 IGP01E1000_PHY_PORT_CONFIG, &phy_data); 2576 if (ret_val) 2577 return ret_val; 2578 2579 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; 2580 ret_val = e1000_write_phy_reg(hw, 2581 IGP01E1000_PHY_PORT_CONFIG, phy_data); 2582 if (ret_val) 2583 return ret_val; 2584 } 2585 2586 2587 } else { 2588 2589 if (hw->mac_type == e1000_ich8lan) { 2590 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU; 2591 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl); 2592 } else if (hw->mac_type == e1000_igb) { 2593 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU; 2594 E1000_WRITE_REG(hw, I210_PHY_CTRL, phy_ctrl); 2595 } else { 2596 phy_data |= IGP02E1000_PM_D0_LPLU; 2597 ret_val = e1000_write_phy_reg(hw, 2598 IGP02E1000_PHY_POWER_MGMT, phy_data); 2599 if (ret_val) 2600 return ret_val; 2601 } 2602 2603 if (hw->mac_type == e1000_igb) 2604 return E1000_SUCCESS; 2605 2606 /* When LPLU is enabled we should disable SmartSpeed */ 2607 ret_val = e1000_read_phy_reg(hw, 2608 IGP01E1000_PHY_PORT_CONFIG, &phy_data); 2609 if (ret_val) 2610 return ret_val; 2611 2612 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; 2613 ret_val = e1000_write_phy_reg(hw, 2614 IGP01E1000_PHY_PORT_CONFIG, phy_data); 2615 if (ret_val) 2616 return ret_val; 2617 2618 } 2619 return E1000_SUCCESS; 2620} 2621 2622/******************************************************************** 2623* Copper link setup for e1000_phy_igp series. 2624* 2625* hw - Struct containing variables accessed by shared code 2626*********************************************************************/ 2627static int32_t 2628e1000_copper_link_igp_setup(struct e1000_hw *hw) 2629{ 2630 uint32_t led_ctrl; 2631 int32_t ret_val; 2632 uint16_t phy_data; 2633 2634 DEBUGFUNC(); 2635 2636 if (hw->phy_reset_disable) 2637 return E1000_SUCCESS; 2638 2639 ret_val = e1000_phy_reset(hw); 2640 if (ret_val) { 2641 DEBUGOUT("Error Resetting the PHY\n"); 2642 return ret_val; 2643 } 2644 2645 /* Wait 15ms for MAC to configure PHY from eeprom settings */ 2646 mdelay(15); 2647 if (hw->mac_type != e1000_ich8lan) { 2648 /* Configure activity LED after PHY reset */ 2649 led_ctrl = E1000_READ_REG(hw, LEDCTL); 2650 led_ctrl &= IGP_ACTIVITY_LED_MASK; 2651 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE); 2652 E1000_WRITE_REG(hw, LEDCTL, led_ctrl); 2653 } 2654 2655 /* The NVM settings will configure LPLU in D3 for IGP2 and IGP3 PHYs */ 2656 if (hw->phy_type == e1000_phy_igp) { 2657 /* disable lplu d3 during driver init */ 2658 ret_val = e1000_set_d3_lplu_state(hw, false); 2659 if (ret_val) { 2660 DEBUGOUT("Error Disabling LPLU D3\n"); 2661 return ret_val; 2662 } 2663 } 2664 2665 /* disable lplu d0 during driver init */ 2666 ret_val = e1000_set_d0_lplu_state(hw, false); 2667 if (ret_val) { 2668 DEBUGOUT("Error Disabling LPLU D0\n"); 2669 return ret_val; 2670 } 2671 /* Configure mdi-mdix settings */ 2672 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data); 2673 if (ret_val) 2674 return ret_val; 2675 2676 if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) { 2677 hw->dsp_config_state = e1000_dsp_config_disabled; 2678 /* Force MDI for earlier revs of the IGP PHY */ 2679 phy_data &= ~(IGP01E1000_PSCR_AUTO_MDIX 2680 | IGP01E1000_PSCR_FORCE_MDI_MDIX); 2681 hw->mdix = 1; 2682 2683 } else { 2684 hw->dsp_config_state = e1000_dsp_config_enabled; 2685 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX; 2686 2687 switch (hw->mdix) { 2688 case 1: 2689 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX; 2690 break; 2691 case 2: 2692 phy_data |= IGP01E1000_PSCR_FORCE_MDI_MDIX; 2693 break; 2694 case 0: 2695 default: 2696 phy_data |= IGP01E1000_PSCR_AUTO_MDIX; 2697 break; 2698 } 2699 } 2700 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data); 2701 if (ret_val) 2702 return ret_val; 2703 2704 /* set auto-master slave resolution settings */ 2705 if (hw->autoneg) { 2706 e1000_ms_type phy_ms_setting = hw->master_slave; 2707 2708 if (hw->ffe_config_state == e1000_ffe_config_active) 2709 hw->ffe_config_state = e1000_ffe_config_enabled; 2710 2711 if (hw->dsp_config_state == e1000_dsp_config_activated) 2712 hw->dsp_config_state = e1000_dsp_config_enabled; 2713 2714 /* when autonegotiation advertisment is only 1000Mbps then we 2715 * should disable SmartSpeed and enable Auto MasterSlave 2716 * resolution as hardware default. */ 2717 if (hw->autoneg_advertised == ADVERTISE_1000_FULL) { 2718 /* Disable SmartSpeed */ 2719 ret_val = e1000_read_phy_reg(hw, 2720 IGP01E1000_PHY_PORT_CONFIG, &phy_data); 2721 if (ret_val) 2722 return ret_val; 2723 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; 2724 ret_val = e1000_write_phy_reg(hw, 2725 IGP01E1000_PHY_PORT_CONFIG, phy_data); 2726 if (ret_val) 2727 return ret_val; 2728 /* Set auto Master/Slave resolution process */ 2729 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, 2730 &phy_data); 2731 if (ret_val) 2732 return ret_val; 2733 phy_data &= ~CR_1000T_MS_ENABLE; 2734 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, 2735 phy_data); 2736 if (ret_val) 2737 return ret_val; 2738 } 2739 2740 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data); 2741 if (ret_val) 2742 return ret_val; 2743 2744 /* load defaults for future use */ 2745 hw->original_master_slave = (phy_data & CR_1000T_MS_ENABLE) ? 2746 ((phy_data & CR_1000T_MS_VALUE) ? 2747 e1000_ms_force_master : 2748 e1000_ms_force_slave) : 2749 e1000_ms_auto; 2750 2751 switch (phy_ms_setting) { 2752 case e1000_ms_force_master: 2753 phy_data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE); 2754 break; 2755 case e1000_ms_force_slave: 2756 phy_data |= CR_1000T_MS_ENABLE; 2757 phy_data &= ~(CR_1000T_MS_VALUE); 2758 break; 2759 case e1000_ms_auto: 2760 phy_data &= ~CR_1000T_MS_ENABLE; 2761 default: 2762 break; 2763 } 2764 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_data); 2765 if (ret_val) 2766 return ret_val; 2767 } 2768 2769 return E1000_SUCCESS; 2770} 2771 2772/***************************************************************************** 2773 * This function checks the mode of the firmware. 2774 * 2775 * returns - true when the mode is IAMT or false. 2776 ****************************************************************************/ 2777bool 2778e1000_check_mng_mode(struct e1000_hw *hw) 2779{ 2780 uint32_t fwsm; 2781 DEBUGFUNC(); 2782 2783 fwsm = E1000_READ_REG(hw, FWSM); 2784 2785 if (hw->mac_type == e1000_ich8lan) { 2786 if ((fwsm & E1000_FWSM_MODE_MASK) == 2787 (E1000_MNG_ICH_IAMT_MODE << E1000_FWSM_MODE_SHIFT)) 2788 return true; 2789 } else if ((fwsm & E1000_FWSM_MODE_MASK) == 2790 (E1000_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT)) 2791 return true; 2792 2793 return false; 2794} 2795 2796static int32_t 2797e1000_write_kmrn_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t data) 2798{ 2799 uint16_t swfw = E1000_SWFW_PHY0_SM; 2800 uint32_t reg_val; 2801 DEBUGFUNC(); 2802 2803 if (e1000_is_second_port(hw)) 2804 swfw = E1000_SWFW_PHY1_SM; 2805 2806 if (e1000_swfw_sync_acquire(hw, swfw)) 2807 return -E1000_ERR_SWFW_SYNC; 2808 2809 reg_val = ((reg_addr << E1000_KUMCTRLSTA_OFFSET_SHIFT) 2810 & E1000_KUMCTRLSTA_OFFSET) | data; 2811 E1000_WRITE_REG(hw, KUMCTRLSTA, reg_val); 2812 udelay(2); 2813 2814 return E1000_SUCCESS; 2815} 2816 2817static int32_t 2818e1000_read_kmrn_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t *data) 2819{ 2820 uint16_t swfw = E1000_SWFW_PHY0_SM; 2821 uint32_t reg_val; 2822 DEBUGFUNC(); 2823 2824 if (e1000_is_second_port(hw)) 2825 swfw = E1000_SWFW_PHY1_SM; 2826 2827 if (e1000_swfw_sync_acquire(hw, swfw)) { 2828 debug("%s[%i]\n", __func__, __LINE__); 2829 return -E1000_ERR_SWFW_SYNC; 2830 } 2831 2832 /* Write register address */ 2833 reg_val = ((reg_addr << E1000_KUMCTRLSTA_OFFSET_SHIFT) & 2834 E1000_KUMCTRLSTA_OFFSET) | E1000_KUMCTRLSTA_REN; 2835 E1000_WRITE_REG(hw, KUMCTRLSTA, reg_val); 2836 udelay(2); 2837 2838 /* Read the data returned */ 2839 reg_val = E1000_READ_REG(hw, KUMCTRLSTA); 2840 *data = (uint16_t)reg_val; 2841 2842 return E1000_SUCCESS; 2843} 2844 2845/******************************************************************** 2846* Copper link setup for e1000_phy_gg82563 series. 2847* 2848* hw - Struct containing variables accessed by shared code 2849*********************************************************************/ 2850static int32_t 2851e1000_copper_link_ggp_setup(struct e1000_hw *hw) 2852{ 2853 int32_t ret_val; 2854 uint16_t phy_data; 2855 uint32_t reg_data; 2856 2857 DEBUGFUNC(); 2858 2859 if (!hw->phy_reset_disable) { 2860 /* Enable CRS on TX for half-duplex operation. */ 2861 ret_val = e1000_read_phy_reg(hw, 2862 GG82563_PHY_MAC_SPEC_CTRL, &phy_data); 2863 if (ret_val) 2864 return ret_val; 2865 2866 phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX; 2867 /* Use 25MHz for both link down and 1000BASE-T for Tx clock */ 2868 phy_data |= GG82563_MSCR_TX_CLK_1000MBPS_25MHZ; 2869 2870 ret_val = e1000_write_phy_reg(hw, 2871 GG82563_PHY_MAC_SPEC_CTRL, phy_data); 2872 if (ret_val) 2873 return ret_val; 2874 2875 /* Options: 2876 * MDI/MDI-X = 0 (default) 2877 * 0 - Auto for all speeds 2878 * 1 - MDI mode 2879 * 2 - MDI-X mode 2880 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes) 2881 */ 2882 ret_val = e1000_read_phy_reg(hw, 2883 GG82563_PHY_SPEC_CTRL, &phy_data); 2884 if (ret_val) 2885 return ret_val; 2886 2887 phy_data &= ~GG82563_PSCR_CROSSOVER_MODE_MASK; 2888 2889 switch (hw->mdix) { 2890 case 1: 2891 phy_data |= GG82563_PSCR_CROSSOVER_MODE_MDI; 2892 break; 2893 case 2: 2894 phy_data |= GG82563_PSCR_CROSSOVER_MODE_MDIX; 2895 break; 2896 case 0: 2897 default: 2898 phy_data |= GG82563_PSCR_CROSSOVER_MODE_AUTO; 2899 break; 2900 } 2901 2902 /* Options: 2903 * disable_polarity_correction = 0 (default) 2904 * Automatic Correction for Reversed Cable Polarity 2905 * 0 - Disabled 2906 * 1 - Enabled 2907 */ 2908 phy_data &= ~GG82563_PSCR_POLARITY_REVERSAL_DISABLE; 2909 ret_val = e1000_write_phy_reg(hw, 2910 GG82563_PHY_SPEC_CTRL, phy_data); 2911 2912 if (ret_val) 2913 return ret_val; 2914 2915 /* SW Reset the PHY so all changes take effect */ 2916 ret_val = e1000_phy_reset(hw); 2917 if (ret_val) { 2918 DEBUGOUT("Error Resetting the PHY\n"); 2919 return ret_val; 2920 } 2921 } /* phy_reset_disable */ 2922 2923 if (hw->mac_type == e1000_80003es2lan) { 2924 /* Bypass RX and TX FIFO's */ 2925 ret_val = e1000_write_kmrn_reg(hw, 2926 E1000_KUMCTRLSTA_OFFSET_FIFO_CTRL, 2927 E1000_KUMCTRLSTA_FIFO_CTRL_RX_BYPASS 2928 | E1000_KUMCTRLSTA_FIFO_CTRL_TX_BYPASS); 2929 if (ret_val) 2930 return ret_val; 2931 2932 ret_val = e1000_read_phy_reg(hw, 2933 GG82563_PHY_SPEC_CTRL_2, &phy_data); 2934 if (ret_val) 2935 return ret_val; 2936 2937 phy_data &= ~GG82563_PSCR2_REVERSE_AUTO_NEG; 2938 ret_val = e1000_write_phy_reg(hw, 2939 GG82563_PHY_SPEC_CTRL_2, phy_data); 2940 2941 if (ret_val) 2942 return ret_val; 2943 2944 reg_data = E1000_READ_REG(hw, CTRL_EXT); 2945 reg_data &= ~(E1000_CTRL_EXT_LINK_MODE_MASK); 2946 E1000_WRITE_REG(hw, CTRL_EXT, reg_data); 2947 2948 ret_val = e1000_read_phy_reg(hw, 2949 GG82563_PHY_PWR_MGMT_CTRL, &phy_data); 2950 if (ret_val) 2951 return ret_val; 2952 2953 /* Do not init these registers when the HW is in IAMT mode, since the 2954 * firmware will have already initialized them. We only initialize 2955 * them if the HW is not in IAMT mode. 2956 */ 2957 if (e1000_check_mng_mode(hw) == false) { 2958 /* Enable Electrical Idle on the PHY */ 2959 phy_data |= GG82563_PMCR_ENABLE_ELECTRICAL_IDLE; 2960 ret_val = e1000_write_phy_reg(hw, 2961 GG82563_PHY_PWR_MGMT_CTRL, phy_data); 2962 if (ret_val) 2963 return ret_val; 2964 2965 ret_val = e1000_read_phy_reg(hw, 2966 GG82563_PHY_KMRN_MODE_CTRL, &phy_data); 2967 if (ret_val) 2968 return ret_val; 2969 2970 phy_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER; 2971 ret_val = e1000_write_phy_reg(hw, 2972 GG82563_PHY_KMRN_MODE_CTRL, phy_data); 2973 2974 if (ret_val) 2975 return ret_val; 2976 } 2977 2978 /* Workaround: Disable padding in Kumeran interface in the MAC 2979 * and in the PHY to avoid CRC errors. 2980 */ 2981 ret_val = e1000_read_phy_reg(hw, 2982 GG82563_PHY_INBAND_CTRL, &phy_data); 2983 if (ret_val) 2984 return ret_val; 2985 phy_data |= GG82563_ICR_DIS_PADDING; 2986 ret_val = e1000_write_phy_reg(hw, 2987 GG82563_PHY_INBAND_CTRL, phy_data); 2988 if (ret_val) 2989 return ret_val; 2990 } 2991 return E1000_SUCCESS; 2992} 2993 2994/******************************************************************** 2995* Copper link setup for e1000_phy_m88 series. 2996* 2997* hw - Struct containing variables accessed by shared code 2998*********************************************************************/ 2999static int32_t 3000e1000_copper_link_mgp_setup(struct e1000_hw *hw) 3001{ 3002 int32_t ret_val; 3003 uint16_t phy_data; 3004 3005 DEBUGFUNC(); 3006 3007 if (hw->phy_reset_disable) 3008 return E1000_SUCCESS; 3009 3010 /* Enable CRS on TX. This must be set for half-duplex operation. */ 3011 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); 3012 if (ret_val) 3013 return ret_val; 3014 3015 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX; 3016 3017 /* Options: 3018 * MDI/MDI-X = 0 (default) 3019 * 0 - Auto for all speeds 3020 * 1 - MDI mode 3021 * 2 - MDI-X mode 3022 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes) 3023 */ 3024 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE; 3025 3026 switch (hw->mdix) { 3027 case 1: 3028 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE; 3029 break; 3030 case 2: 3031 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE; 3032 break; 3033 case 3: 3034 phy_data |= M88E1000_PSCR_AUTO_X_1000T; 3035 break; 3036 case 0: 3037 default: 3038 phy_data |= M88E1000_PSCR_AUTO_X_MODE; 3039 break; 3040 } 3041 3042 /* Options: 3043 * disable_polarity_correction = 0 (default) 3044 * Automatic Correction for Reversed Cable Polarity 3045 * 0 - Disabled 3046 * 1 - Enabled 3047 */ 3048 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL; 3049 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); 3050 if (ret_val) 3051 return ret_val; 3052 3053 if (hw->phy_revision < M88E1011_I_REV_4) { 3054 /* Force TX_CLK in the Extended PHY Specific Control Register 3055 * to 25MHz clock. 3056 */ 3057 ret_val = e1000_read_phy_reg(hw, 3058 M88E1000_EXT_PHY_SPEC_CTRL, &phy_data); 3059 if (ret_val) 3060 return ret_val; 3061 3062 phy_data |= M88E1000_EPSCR_TX_CLK_25; 3063 3064 if ((hw->phy_revision == E1000_REVISION_2) && 3065 (hw->phy_id == M88E1111_I_PHY_ID)) { 3066 /* Vidalia Phy, set the downshift counter to 5x */ 3067 phy_data &= ~(M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK); 3068 phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X; 3069 ret_val = e1000_write_phy_reg(hw, 3070 M88E1000_EXT_PHY_SPEC_CTRL, phy_data); 3071 if (ret_val) 3072 return ret_val; 3073 } else { 3074 /* Configure Master and Slave downshift values */ 3075 phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK 3076 | M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK); 3077 phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X 3078 | M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X); 3079 ret_val = e1000_write_phy_reg(hw, 3080 M88E1000_EXT_PHY_SPEC_CTRL, phy_data); 3081 if (ret_val) 3082 return ret_val; 3083 } 3084 } 3085 3086 /* SW Reset the PHY so all changes take effect */ 3087 ret_val = e1000_phy_reset(hw); 3088 if (ret_val) { 3089 DEBUGOUT("Error Resetting the PHY\n"); 3090 return ret_val; 3091 } 3092 3093 return E1000_SUCCESS; 3094} 3095 3096/******************************************************************** 3097* Setup auto-negotiation and flow control advertisements, 3098* and then perform auto-negotiation. 3099* 3100* hw - Struct containing variables accessed by shared code 3101*********************************************************************/ 3102static int32_t 3103e1000_copper_link_autoneg(struct e1000_hw *hw) 3104{ 3105 int32_t ret_val; 3106 uint16_t phy_data; 3107 3108 DEBUGFUNC(); 3109 3110 /* Perform some bounds checking on the hw->autoneg_advertised 3111 * parameter. If this variable is zero, then set it to the default. 3112 */ 3113 hw->autoneg_advertised &= AUTONEG_ADVERTISE_SPEED_DEFAULT; 3114 3115 /* If autoneg_advertised is zero, we assume it was not defaulted 3116 * by the calling code so we set to advertise full capability. 3117 */ 3118 if (hw->autoneg_advertised == 0) 3119 hw->autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT; 3120 3121 /* IFE phy only supports 10/100 */ 3122 if (hw->phy_type == e1000_phy_ife) 3123 hw->autoneg_advertised &= AUTONEG_ADVERTISE_10_100_ALL; 3124 3125 DEBUGOUT("Reconfiguring auto-neg advertisement params\n"); 3126 ret_val = e1000_phy_setup_autoneg(hw); 3127 if (ret_val) { 3128 DEBUGOUT("Error Setting up Auto-Negotiation\n"); 3129 return ret_val; 3130 } 3131 DEBUGOUT("Restarting Auto-Neg\n"); 3132 3133 /* Restart auto-negotiation by setting the Auto Neg Enable bit and 3134 * the Auto Neg Restart bit in the PHY control register. 3135 */ 3136 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data); 3137 if (ret_val) 3138 return ret_val; 3139 3140 phy_data |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG); 3141 ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data); 3142 if (ret_val) 3143 return ret_val; 3144 3145 /* Does the user want to wait for Auto-Neg to complete here, or 3146 * check at a later time (for example, callback routine). 3147 */ 3148 /* If we do not wait for autonegtation to complete I 3149 * do not see a valid link status. 3150 * wait_autoneg_complete = 1 . 3151 */ 3152 if (hw->wait_autoneg_complete) { 3153 ret_val = e1000_wait_autoneg(hw); 3154 if (ret_val) { 3155 DEBUGOUT("Error while waiting for autoneg" 3156 "to complete\n"); 3157 return ret_val; 3158 } 3159 } 3160 3161 hw->get_link_status = true; 3162 3163 return E1000_SUCCESS; 3164} 3165 3166/****************************************************************************** 3167* Config the MAC and the PHY after link is up. 3168* 1) Set up the MAC to the current PHY speed/duplex 3169* if we are on 82543. If we 3170* are on newer silicon, we only need to configure 3171* collision distance in the Transmit Control Register. 3172* 2) Set up flow control on the MAC to that established with 3173* the link partner. 3174* 3) Config DSP to improve Gigabit link quality for some PHY revisions. 3175* 3176* hw - Struct containing variables accessed by shared code 3177******************************************************************************/ 3178static int32_t 3179e1000_copper_link_postconfig(struct e1000_hw *hw) 3180{ 3181 int32_t ret_val; 3182 DEBUGFUNC(); 3183 3184 if (hw->mac_type >= e1000_82544) { 3185 e1000_config_collision_dist(hw); 3186 } else { 3187 ret_val = e1000_config_mac_to_phy(hw); 3188 if (ret_val) { 3189 DEBUGOUT("Error configuring MAC to PHY settings\n"); 3190 return ret_val; 3191 } 3192 } 3193 ret_val = e1000_config_fc_after_link_up(hw); 3194 if (ret_val) { 3195 DEBUGOUT("Error Configuring Flow Control\n"); 3196 return ret_val; 3197 } 3198 return E1000_SUCCESS; 3199} 3200 3201/****************************************************************************** 3202* Detects which PHY is present and setup the speed and duplex 3203* 3204* hw - Struct containing variables accessed by shared code 3205******************************************************************************/ 3206static int 3207e1000_setup_copper_link(struct e1000_hw *hw) 3208{ 3209 int32_t ret_val; 3210 uint16_t i; 3211 uint16_t phy_data; 3212 uint16_t reg_data; 3213 3214 DEBUGFUNC(); 3215 3216 switch (hw->mac_type) { 3217 case e1000_80003es2lan: 3218 case e1000_ich8lan: 3219 /* Set the mac to wait the maximum time between each 3220 * iteration and increase the max iterations when 3221 * polling the phy; this fixes erroneous timeouts at 10Mbps. */ 3222 ret_val = e1000_write_kmrn_reg(hw, 3223 GG82563_REG(0x34, 4), 0xFFFF); 3224 if (ret_val) 3225 return ret_val; 3226 ret_val = e1000_read_kmrn_reg(hw, 3227 GG82563_REG(0x34, 9), ®_data); 3228 if (ret_val) 3229 return ret_val; 3230 reg_data |= 0x3F; 3231 ret_val = e1000_write_kmrn_reg(hw, 3232 GG82563_REG(0x34, 9), reg_data); 3233 if (ret_val) 3234 return ret_val; 3235 default: 3236 break; 3237 } 3238 3239 /* Check if it is a valid PHY and set PHY mode if necessary. */ 3240 ret_val = e1000_copper_link_preconfig(hw); 3241 if (ret_val) 3242 return ret_val; 3243 switch (hw->mac_type) { 3244 case e1000_80003es2lan: 3245 /* Kumeran registers are written-only */ 3246 reg_data = 3247 E1000_KUMCTRLSTA_INB_CTRL_LINK_STATUS_TX_TIMEOUT_DEFAULT; 3248 reg_data |= E1000_KUMCTRLSTA_INB_CTRL_DIS_PADDING; 3249 ret_val = e1000_write_kmrn_reg(hw, 3250 E1000_KUMCTRLSTA_OFFSET_INB_CTRL, reg_data); 3251 if (ret_val) 3252 return ret_val; 3253 break; 3254 default: 3255 break; 3256 } 3257 3258 if (hw->phy_type == e1000_phy_igp || 3259 hw->phy_type == e1000_phy_igp_3 || 3260 hw->phy_type == e1000_phy_igp_2) { 3261 ret_val = e1000_copper_link_igp_setup(hw); 3262 if (ret_val) 3263 return ret_val; 3264 } else if (hw->phy_type == e1000_phy_m88 || 3265 hw->phy_type == e1000_phy_igb || 3266 hw->phy_type == e1000_phy_igc) { 3267 ret_val = e1000_copper_link_mgp_setup(hw); 3268 if (ret_val) 3269 return ret_val; 3270 } else if (hw->phy_type == e1000_phy_gg82563) { 3271 ret_val = e1000_copper_link_ggp_setup(hw); 3272 if (ret_val) 3273 return ret_val; 3274 } 3275 3276 /* always auto */ 3277 /* Setup autoneg and flow control advertisement 3278 * and perform autonegotiation */ 3279 ret_val = e1000_copper_link_autoneg(hw); 3280 if (ret_val) 3281 return ret_val; 3282 3283 /* Check link status. Wait up to 100 microseconds for link to become 3284 * valid. 3285 */ 3286 for (i = 0; i < 10; i++) { 3287 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); 3288 if (ret_val) 3289 return ret_val; 3290 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); 3291 if (ret_val) 3292 return ret_val; 3293 3294 if (phy_data & MII_SR_LINK_STATUS) { 3295 /* Config the MAC and PHY after link is up */ 3296 ret_val = e1000_copper_link_postconfig(hw); 3297 if (ret_val) 3298 return ret_val; 3299 3300 DEBUGOUT("Valid link established!!!\n"); 3301 return E1000_SUCCESS; 3302 } 3303 udelay(10); 3304 } 3305 3306 DEBUGOUT("Unable to establish link!!!\n"); 3307 return E1000_SUCCESS; 3308} 3309 3310/****************************************************************************** 3311* Configures PHY autoneg and flow control advertisement settings 3312* 3313* hw - Struct containing variables accessed by shared code 3314******************************************************************************/ 3315int32_t 3316e1000_phy_setup_autoneg(struct e1000_hw *hw) 3317{ 3318 int32_t ret_val; 3319 uint16_t mii_autoneg_adv_reg; 3320 uint16_t mii_1000t_ctrl_reg; 3321 3322 DEBUGFUNC(); 3323 3324 /* Read the MII Auto-Neg Advertisement Register (Address 4). */ 3325 ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg); 3326 if (ret_val) 3327 return ret_val; 3328 3329 if (hw->phy_type != e1000_phy_ife) { 3330 /* Read the MII 1000Base-T Control Register (Address 9). */ 3331 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, 3332 &mii_1000t_ctrl_reg); 3333 if (ret_val) 3334 return ret_val; 3335 } else 3336 mii_1000t_ctrl_reg = 0; 3337 3338 /* Need to parse both autoneg_advertised and fc and set up 3339 * the appropriate PHY registers. First we will parse for 3340 * autoneg_advertised software override. Since we can advertise 3341 * a plethora of combinations, we need to check each bit 3342 * individually. 3343 */ 3344 3345 /* First we clear all the 10/100 mb speed bits in the Auto-Neg 3346 * Advertisement Register (Address 4) and the 1000 mb speed bits in 3347 * the 1000Base-T Control Register (Address 9). 3348 */ 3349 mii_autoneg_adv_reg &= ~REG4_SPEED_MASK; 3350 mii_1000t_ctrl_reg &= ~REG9_SPEED_MASK; 3351 3352 DEBUGOUT("autoneg_advertised %x\n", hw->autoneg_advertised); 3353 3354 /* Do we want to advertise 10 Mb Half Duplex? */ 3355 if (hw->autoneg_advertised & ADVERTISE_10_HALF) { 3356 DEBUGOUT("Advertise 10mb Half duplex\n"); 3357 mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS; 3358 } 3359 3360 /* Do we want to advertise 10 Mb Full Duplex? */ 3361 if (hw->autoneg_advertised & ADVERTISE_10_FULL) { 3362 DEBUGOUT("Advertise 10mb Full duplex\n"); 3363 mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS; 3364 } 3365 3366 /* Do we want to advertise 100 Mb Half Duplex? */ 3367 if (hw->autoneg_advertised & ADVERTISE_100_HALF) { 3368 DEBUGOUT("Advertise 100mb Half duplex\n"); 3369 mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS; 3370 } 3371 3372 /* Do we want to advertise 100 Mb Full Duplex? */ 3373 if (hw->autoneg_advertised & ADVERTISE_100_FULL) { 3374 DEBUGOUT("Advertise 100mb Full duplex\n"); 3375 mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS; 3376 } 3377 3378 /* We do not allow the Phy to advertise 1000 Mb Half Duplex */ 3379 if (hw->autoneg_advertised & ADVERTISE_1000_HALF) { 3380 DEBUGOUT 3381 ("Advertise 1000mb Half duplex requested, request denied!\n"); 3382 } 3383 3384 /* Do we want to advertise 1000 Mb Full Duplex? */ 3385 if (hw->autoneg_advertised & ADVERTISE_1000_FULL) { 3386 DEBUGOUT("Advertise 1000mb Full duplex\n"); 3387 mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS; 3388 } 3389 3390 /* Check for a software override of the flow control settings, and 3391 * setup the PHY advertisement registers accordingly. If 3392 * auto-negotiation is enabled, then software will have to set the 3393 * "PAUSE" bits to the correct value in the Auto-Negotiation 3394 * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto-negotiation. 3395 * 3396 * The possible values of the "fc" parameter are: 3397 * 0: Flow control is completely disabled 3398 * 1: Rx flow control is enabled (we can receive pause frames 3399 * but not send pause frames). 3400 * 2: Tx flow control is enabled (we can send pause frames 3401 * but we do not support receiving pause frames). 3402 * 3: Both Rx and TX flow control (symmetric) are enabled. 3403 * other: No software override. The flow control configuration 3404 * in the EEPROM is used. 3405 */ 3406 switch (hw->fc) { 3407 case e1000_fc_none: /* 0 */ 3408 /* Flow control (RX & TX) is completely disabled by a 3409 * software over-ride. 3410 */ 3411 mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); 3412 break; 3413 case e1000_fc_rx_pause: /* 1 */ 3414 /* RX Flow control is enabled, and TX Flow control is 3415 * disabled, by a software over-ride. 3416 */ 3417 /* Since there really isn't a way to advertise that we are 3418 * capable of RX Pause ONLY, we will advertise that we 3419 * support both symmetric and asymmetric RX PAUSE. Later 3420 * (in e1000_config_fc_after_link_up) we will disable the 3421 *hw's ability to send PAUSE frames. 3422 */ 3423 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); 3424 break; 3425 case e1000_fc_tx_pause: /* 2 */ 3426 /* TX Flow control is enabled, and RX Flow control is 3427 * disabled, by a software over-ride. 3428 */ 3429 mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR; 3430 mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE; 3431 break; 3432 case e1000_fc_full: /* 3 */ 3433 /* Flow control (both RX and TX) is enabled by a software 3434 * over-ride. 3435 */ 3436 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); 3437 break; 3438 default: 3439 DEBUGOUT("Flow control param set incorrectly\n"); 3440 return -E1000_ERR_CONFIG; 3441 } 3442 3443 ret_val = e1000_write_phy_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg); 3444 if (ret_val) 3445 return ret_val; 3446 3447 DEBUGOUT("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg); 3448 3449 if (hw->phy_type != e1000_phy_ife) { 3450 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, 3451 mii_1000t_ctrl_reg); 3452 if (ret_val) 3453 return ret_val; 3454 } 3455 3456 return E1000_SUCCESS; 3457} 3458 3459/****************************************************************************** 3460* Sets the collision distance in the Transmit Control register 3461* 3462* hw - Struct containing variables accessed by shared code 3463* 3464* Link should have been established previously. Reads the speed and duplex 3465* information from the Device Status register. 3466******************************************************************************/ 3467static void 3468e1000_config_collision_dist(struct e1000_hw *hw) 3469{ 3470 uint32_t tctl, coll_dist; 3471 3472 DEBUGFUNC(); 3473 3474 if (hw->mac_type < e1000_82543) 3475 coll_dist = E1000_COLLISION_DISTANCE_82542; 3476 else 3477 coll_dist = E1000_COLLISION_DISTANCE; 3478 3479 tctl = E1000_READ_REG(hw, TCTL); 3480 3481 tctl &= ~E1000_TCTL_COLD; 3482 tctl |= coll_dist << E1000_COLD_SHIFT; 3483 3484 E1000_WRITE_REG(hw, TCTL, tctl); 3485 E1000_WRITE_FLUSH(hw); 3486} 3487 3488/****************************************************************************** 3489* Sets MAC speed and duplex settings to reflect the those in the PHY 3490* 3491* hw - Struct containing variables accessed by shared code 3492* mii_reg - data to write to the MII control register 3493* 3494* The contents of the PHY register containing the needed information need to 3495* be passed in. 3496******************************************************************************/ 3497static int 3498e1000_config_mac_to_phy(struct e1000_hw *hw) 3499{ 3500 uint32_t ctrl; 3501 uint16_t phy_data; 3502 3503 DEBUGFUNC(); 3504 3505 /* Read the Device Control Register and set the bits to Force Speed 3506 * and Duplex. 3507 */ 3508 ctrl = E1000_READ_REG(hw, CTRL); 3509 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 3510 ctrl &= ~(E1000_CTRL_ILOS); 3511 ctrl |= (E1000_CTRL_SPD_SEL); 3512 3513 /* Set up duplex in the Device Control and Transmit Control 3514 * registers depending on negotiated values. 3515 */ 3516 if (e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data) < 0) { 3517 DEBUGOUT("PHY Read Error\n"); 3518 return -E1000_ERR_PHY; 3519 } 3520 if (phy_data & M88E1000_PSSR_DPLX) 3521 ctrl |= E1000_CTRL_FD; 3522 else 3523 ctrl &= ~E1000_CTRL_FD; 3524 3525 e1000_config_collision_dist(hw); 3526 3527 /* Set up speed in the Device Control register depending on 3528 * negotiated values. 3529 */ 3530 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) 3531 ctrl |= E1000_CTRL_SPD_1000; 3532 else if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_100MBS) 3533 ctrl |= E1000_CTRL_SPD_100; 3534 /* Write the configured values back to the Device Control Reg. */ 3535 E1000_WRITE_REG(hw, CTRL, ctrl); 3536 return 0; 3537} 3538 3539/****************************************************************************** 3540 * Forces the MAC's flow control settings. 3541 * 3542 * hw - Struct containing variables accessed by shared code 3543 * 3544 * Sets the TFCE and RFCE bits in the device control register to reflect 3545 * the adapter settings. TFCE and RFCE need to be explicitly set by 3546 * software when a Copper PHY is used because autonegotiation is managed 3547 * by the PHY rather than the MAC. Software must also configure these 3548 * bits when link is forced on a fiber connection. 3549 *****************************************************************************/ 3550static int 3551e1000_force_mac_fc(struct e1000_hw *hw) 3552{ 3553 uint32_t ctrl; 3554 3555 DEBUGFUNC(); 3556 3557 /* Get the current configuration of the Device Control Register */ 3558 ctrl = E1000_READ_REG(hw, CTRL); 3559 3560 /* Because we didn't get link via the internal auto-negotiation 3561 * mechanism (we either forced link or we got link via PHY 3562 * auto-neg), we have to manually enable/disable transmit an 3563 * receive flow control. 3564 * 3565 * The "Case" statement below enables/disable flow control 3566 * according to the "hw->fc" parameter. 3567 * 3568 * The possible values of the "fc" parameter are: 3569 * 0: Flow control is completely disabled 3570 * 1: Rx flow control is enabled (we can receive pause 3571 * frames but not send pause frames). 3572 * 2: Tx flow control is enabled (we can send pause frames 3573 * frames but we do not receive pause frames). 3574 * 3: Both Rx and TX flow control (symmetric) is enabled. 3575 * other: No other values should be possible at this point. 3576 */ 3577 3578 switch (hw->fc) { 3579 case e1000_fc_none: 3580 ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE)); 3581 break; 3582 case e1000_fc_rx_pause: 3583 ctrl &= (~E1000_CTRL_TFCE); 3584 ctrl |= E1000_CTRL_RFCE; 3585 break; 3586 case e1000_fc_tx_pause: 3587 ctrl &= (~E1000_CTRL_RFCE); 3588 ctrl |= E1000_CTRL_TFCE; 3589 break; 3590 case e1000_fc_full: 3591 ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE); 3592 break; 3593 default: 3594 DEBUGOUT("Flow control param set incorrectly\n"); 3595 return -E1000_ERR_CONFIG; 3596 } 3597 3598 /* Disable TX Flow Control for 82542 (rev 2.0) */ 3599 if (hw->mac_type == e1000_82542_rev2_0) 3600 ctrl &= (~E1000_CTRL_TFCE); 3601 3602 E1000_WRITE_REG(hw, CTRL, ctrl); 3603 return 0; 3604} 3605 3606/****************************************************************************** 3607 * Configures flow control settings after link is established 3608 * 3609 * hw - Struct containing variables accessed by shared code 3610 * 3611 * Should be called immediately after a valid link has been established. 3612 * Forces MAC flow control settings if link was forced. When in MII/GMII mode 3613 * and autonegotiation is enabled, the MAC flow control settings will be set 3614 * based on the flow control negotiated by the PHY. In TBI mode, the TFCE 3615 * and RFCE bits will be automaticaly set to the negotiated flow control mode. 3616 *****************************************************************************/ 3617static int32_t 3618e1000_config_fc_after_link_up(struct e1000_hw *hw) 3619{ 3620 int32_t ret_val; 3621 uint16_t mii_status_reg; 3622 uint16_t mii_nway_adv_reg; 3623 uint16_t mii_nway_lp_ability_reg; 3624 uint16_t speed; 3625 uint16_t duplex; 3626 3627 DEBUGFUNC(); 3628 3629 /* Check for the case where we have fiber media and auto-neg failed 3630 * so we had to force link. In this case, we need to force the 3631 * configuration of the MAC to match the "fc" parameter. 3632 */ 3633 if (((hw->media_type == e1000_media_type_fiber) && (hw->autoneg_failed)) 3634 || ((hw->media_type == e1000_media_type_internal_serdes) 3635 && (hw->autoneg_failed)) 3636 || ((hw->media_type == e1000_media_type_copper) 3637 && (!hw->autoneg))) { 3638 ret_val = e1000_force_mac_fc(hw); 3639 if (ret_val < 0) { 3640 DEBUGOUT("Error forcing flow control settings\n"); 3641 return ret_val; 3642 } 3643 } 3644 3645 /* Check for the case where we have copper media and auto-neg is 3646 * enabled. In this case, we need to check and see if Auto-Neg 3647 * has completed, and if so, how the PHY and link partner has 3648 * flow control configured. 3649 */ 3650 if (hw->media_type == e1000_media_type_copper) { 3651 /* Read the MII Status Register and check to see if AutoNeg 3652 * has completed. We read this twice because this reg has 3653 * some "sticky" (latched) bits. 3654 */ 3655 if (e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg) < 0) { 3656 DEBUGOUT("PHY Read Error\n"); 3657 return -E1000_ERR_PHY; 3658 } 3659 if (e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg) < 0) { 3660 DEBUGOUT("PHY Read Error\n"); 3661 return -E1000_ERR_PHY; 3662 } 3663 3664 if (mii_status_reg & MII_SR_AUTONEG_COMPLETE) { 3665 /* The AutoNeg process has completed, so we now need to 3666 * read both the Auto Negotiation Advertisement Register 3667 * (Address 4) and the Auto_Negotiation Base Page Ability 3668 * Register (Address 5) to determine how flow control was 3669 * negotiated. 3670 */ 3671 if (e1000_read_phy_reg 3672 (hw, PHY_AUTONEG_ADV, &mii_nway_adv_reg) < 0) { 3673 DEBUGOUT("PHY Read Error\n"); 3674 return -E1000_ERR_PHY; 3675 } 3676 if (e1000_read_phy_reg 3677 (hw, PHY_LP_ABILITY, 3678 &mii_nway_lp_ability_reg) < 0) { 3679 DEBUGOUT("PHY Read Error\n"); 3680 return -E1000_ERR_PHY; 3681 } 3682 3683 /* Two bits in the Auto Negotiation Advertisement Register 3684 * (Address 4) and two bits in the Auto Negotiation Base 3685 * Page Ability Register (Address 5) determine flow control 3686 * for both the PHY and the link partner. The following 3687 * table, taken out of the IEEE 802.3ab/D6.0 dated March 25, 3688 * 1999, describes these PAUSE resolution bits and how flow 3689 * control is determined based upon these settings. 3690 * NOTE: DC = Don't Care 3691 * 3692 * LOCAL DEVICE | LINK PARTNER 3693 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution 3694 *-------|---------|-------|---------|-------------------- 3695 * 0 | 0 | DC | DC | e1000_fc_none 3696 * 0 | 1 | 0 | DC | e1000_fc_none 3697 * 0 | 1 | 1 | 0 | e1000_fc_none 3698 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause 3699 * 1 | 0 | 0 | DC | e1000_fc_none 3700 * 1 | DC | 1 | DC | e1000_fc_full 3701 * 1 | 1 | 0 | 0 | e1000_fc_none 3702 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause 3703 * 3704 */ 3705 /* Are both PAUSE bits set to 1? If so, this implies 3706 * Symmetric Flow Control is enabled at both ends. The 3707 * ASM_DIR bits are irrelevant per the spec. 3708 * 3709 * For Symmetric Flow Control: 3710 * 3711 * LOCAL DEVICE | LINK PARTNER 3712 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 3713 *-------|---------|-------|---------|-------------------- 3714 * 1 | DC | 1 | DC | e1000_fc_full 3715 * 3716 */ 3717 if ((mii_nway_adv_reg & NWAY_AR_PAUSE) && 3718 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) { 3719 /* Now we need to check if the user selected RX ONLY 3720 * of pause frames. In this case, we had to advertise 3721 * FULL flow control because we could not advertise RX 3722 * ONLY. Hence, we must now check to see if we need to 3723 * turn OFF the TRANSMISSION of PAUSE frames. 3724 */ 3725 if (hw->original_fc == e1000_fc_full) { 3726 hw->fc = e1000_fc_full; 3727 DEBUGOUT("Flow Control = FULL.\r\n"); 3728 } else { 3729 hw->fc = e1000_fc_rx_pause; 3730 DEBUGOUT 3731 ("Flow Control = RX PAUSE frames only.\r\n"); 3732 } 3733 } 3734 /* For receiving PAUSE frames ONLY. 3735 * 3736 * LOCAL DEVICE | LINK PARTNER 3737 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 3738 *-------|---------|-------|---------|-------------------- 3739 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause 3740 * 3741 */ 3742 else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) && 3743 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && 3744 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && 3745 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) 3746 { 3747 hw->fc = e1000_fc_tx_pause; 3748 DEBUGOUT 3749 ("Flow Control = TX PAUSE frames only.\r\n"); 3750 } 3751 /* For transmitting PAUSE frames ONLY. 3752 * 3753 * LOCAL DEVICE | LINK PARTNER 3754 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 3755 *-------|---------|-------|---------|-------------------- 3756 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause 3757 * 3758 */ 3759 else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) && 3760 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && 3761 !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && 3762 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) 3763 { 3764 hw->fc = e1000_fc_rx_pause; 3765 DEBUGOUT 3766 ("Flow Control = RX PAUSE frames only.\r\n"); 3767 } 3768 /* Per the IEEE spec, at this point flow control should be 3769 * disabled. However, we want to consider that we could 3770 * be connected to a legacy switch that doesn't advertise 3771 * desired flow control, but can be forced on the link 3772 * partner. So if we advertised no flow control, that is 3773 * what we will resolve to. If we advertised some kind of 3774 * receive capability (Rx Pause Only or Full Flow Control) 3775 * and the link partner advertised none, we will configure 3776 * ourselves to enable Rx Flow Control only. We can do 3777 * this safely for two reasons: If the link partner really 3778 * didn't want flow control enabled, and we enable Rx, no 3779 * harm done since we won't be receiving any PAUSE frames 3780 * anyway. If the intent on the link partner was to have 3781 * flow control enabled, then by us enabling RX only, we 3782 * can at least receive pause frames and process them. 3783 * This is a good idea because in most cases, since we are 3784 * predominantly a server NIC, more times than not we will 3785 * be asked to delay transmission of packets than asking 3786 * our link partner to pause transmission of frames. 3787 */ 3788 else if (hw->original_fc == e1000_fc_none || 3789 hw->original_fc == e1000_fc_tx_pause) { 3790 hw->fc = e1000_fc_none; 3791 DEBUGOUT("Flow Control = NONE.\r\n"); 3792 } else { 3793 hw->fc = e1000_fc_rx_pause; 3794 DEBUGOUT 3795 ("Flow Control = RX PAUSE frames only.\r\n"); 3796 } 3797 3798 /* Now we need to do one last check... If we auto- 3799 * negotiated to HALF DUPLEX, flow control should not be 3800 * enabled per IEEE 802.3 spec. 3801 */ 3802 e1000_get_speed_and_duplex(hw, &speed, &duplex); 3803 3804 if (duplex == HALF_DUPLEX) 3805 hw->fc = e1000_fc_none; 3806 3807 /* Now we call a subroutine to actually force the MAC 3808 * controller to use the correct flow control settings. 3809 */ 3810 ret_val = e1000_force_mac_fc(hw); 3811 if (ret_val < 0) { 3812 DEBUGOUT 3813 ("Error forcing flow control settings\n"); 3814 return ret_val; 3815 } 3816 } else { 3817 DEBUGOUT 3818 ("Copper PHY and Auto Neg has not completed.\r\n"); 3819 } 3820 } 3821 return E1000_SUCCESS; 3822} 3823 3824/****************************************************************************** 3825 * Checks to see if the link status of the hardware has changed. 3826 * 3827 * hw - Struct containing variables accessed by shared code 3828 * 3829 * Called by any function that needs to check the link status of the adapter. 3830 *****************************************************************************/ 3831static int 3832e1000_check_for_link(struct e1000_hw *hw) 3833{ 3834 uint32_t rxcw; 3835 uint32_t ctrl; 3836 uint32_t status; 3837 uint32_t rctl; 3838 uint32_t signal; 3839 int32_t ret_val; 3840 uint16_t phy_data; 3841 uint16_t lp_capability; 3842 3843 DEBUGFUNC(); 3844 3845 /* On adapters with a MAC newer that 82544, SW Defineable pin 1 will be 3846 * set when the optics detect a signal. On older adapters, it will be 3847 * cleared when there is a signal 3848 */ 3849 ctrl = E1000_READ_REG(hw, CTRL); 3850 if ((hw->mac_type > e1000_82544) && !(ctrl & E1000_CTRL_ILOS)) 3851 signal = E1000_CTRL_SWDPIN1; 3852 else 3853 signal = 0; 3854 3855 status = E1000_READ_REG(hw, STATUS); 3856 rxcw = E1000_READ_REG(hw, RXCW); 3857 DEBUGOUT("ctrl: %#08x status %#08x rxcw %#08x\n", ctrl, status, rxcw); 3858 3859 /* If we have a copper PHY then we only want to go out to the PHY 3860 * registers to see if Auto-Neg has completed and/or if our link 3861 * status has changed. The get_link_status flag will be set if we 3862 * receive a Link Status Change interrupt or we have Rx Sequence 3863 * Errors. 3864 */ 3865 if ((hw->media_type == e1000_media_type_copper) && hw->get_link_status) { 3866 /* First we want to see if the MII Status Register reports 3867 * link. If so, then we want to get the current speed/duplex 3868 * of the PHY. 3869 * Read the register twice since the link bit is sticky. 3870 */ 3871 if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) { 3872 DEBUGOUT("PHY Read Error\n"); 3873 return -E1000_ERR_PHY; 3874 } 3875 if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) { 3876 DEBUGOUT("PHY Read Error\n"); 3877 return -E1000_ERR_PHY; 3878 } 3879 3880 if (phy_data & MII_SR_LINK_STATUS) { 3881 hw->get_link_status = false; 3882 } else { 3883 /* No link detected */ 3884 return -E1000_ERR_NOLINK; 3885 } 3886 3887 /* We have a M88E1000 PHY and Auto-Neg is enabled. If we 3888 * have Si on board that is 82544 or newer, Auto 3889 * Speed Detection takes care of MAC speed/duplex 3890 * configuration. So we only need to configure Collision 3891 * Distance in the MAC. Otherwise, we need to force 3892 * speed/duplex on the MAC to the current PHY speed/duplex 3893 * settings. 3894 */ 3895 if (hw->mac_type >= e1000_82544) 3896 e1000_config_collision_dist(hw); 3897 else { 3898 ret_val = e1000_config_mac_to_phy(hw); 3899 if (ret_val < 0) { 3900 DEBUGOUT 3901 ("Error configuring MAC to PHY settings\n"); 3902 return ret_val; 3903 } 3904 } 3905 3906 /* Configure Flow Control now that Auto-Neg has completed. First, we 3907 * need to restore the desired flow control settings because we may 3908 * have had to re-autoneg with a different link partner. 3909 */ 3910 ret_val = e1000_config_fc_after_link_up(hw); 3911 if (ret_val < 0) { 3912 DEBUGOUT("Error configuring flow control\n"); 3913 return ret_val; 3914 } 3915 3916 /* At this point we know that we are on copper and we have 3917 * auto-negotiated link. These are conditions for checking the link 3918 * parter capability register. We use the link partner capability to 3919 * determine if TBI Compatibility needs to be turned on or off. If 3920 * the link partner advertises any speed in addition to Gigabit, then 3921 * we assume that they are GMII-based, and TBI compatibility is not 3922 * needed. If no other speeds are advertised, we assume the link 3923 * partner is TBI-based, and we turn on TBI Compatibility. 3924 */ 3925 if (hw->tbi_compatibility_en) { 3926 if (e1000_read_phy_reg 3927 (hw, PHY_LP_ABILITY, &lp_capability) < 0) { 3928 DEBUGOUT("PHY Read Error\n"); 3929 return -E1000_ERR_PHY; 3930 } 3931 if (lp_capability & (NWAY_LPAR_10T_HD_CAPS | 3932 NWAY_LPAR_10T_FD_CAPS | 3933 NWAY_LPAR_100TX_HD_CAPS | 3934 NWAY_LPAR_100TX_FD_CAPS | 3935 NWAY_LPAR_100T4_CAPS)) { 3936 /* If our link partner advertises anything in addition to 3937 * gigabit, we do not need to enable TBI compatibility. 3938 */ 3939 if (hw->tbi_compatibility_on) { 3940 /* If we previously were in the mode, turn it off. */ 3941 rctl = E1000_READ_REG(hw, RCTL); 3942 rctl &= ~E1000_RCTL_SBP; 3943 E1000_WRITE_REG(hw, RCTL, rctl); 3944 hw->tbi_compatibility_on = false; 3945 } 3946 } else { 3947 /* If TBI compatibility is was previously off, turn it on. For 3948 * compatibility with a TBI link partner, we will store bad 3949 * packets. Some frames have an additional byte on the end and 3950 * will look like CRC errors to to the hardware. 3951 */ 3952 if (!hw->tbi_compatibility_on) { 3953 hw->tbi_compatibility_on = true; 3954 rctl = E1000_READ_REG(hw, RCTL); 3955 rctl |= E1000_RCTL_SBP; 3956 E1000_WRITE_REG(hw, RCTL, rctl); 3957 } 3958 } 3959 } 3960 } 3961 /* If we don't have link (auto-negotiation failed or link partner cannot 3962 * auto-negotiate), the cable is plugged in (we have signal), and our 3963 * link partner is not trying to auto-negotiate with us (we are receiving 3964 * idles or data), we need to force link up. We also need to give 3965 * auto-negotiation time to complete, in case the cable was just plugged 3966 * in. The autoneg_failed flag does this. 3967 */ 3968 else if ((hw->media_type == e1000_media_type_fiber) && 3969 (!(status & E1000_STATUS_LU)) && 3970 ((ctrl & E1000_CTRL_SWDPIN1) == signal) && 3971 (!(rxcw & E1000_RXCW_C))) { 3972 if (hw->autoneg_failed == 0) { 3973 hw->autoneg_failed = 1; 3974 return 0; 3975 } 3976 DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\r\n"); 3977 3978 /* Disable auto-negotiation in the TXCW register */ 3979 E1000_WRITE_REG(hw, TXCW, (hw->txcw & ~E1000_TXCW_ANE)); 3980 3981 /* Force link-up and also force full-duplex. */ 3982 ctrl = E1000_READ_REG(hw, CTRL); 3983 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD); 3984 E1000_WRITE_REG(hw, CTRL, ctrl); 3985 3986 /* Configure Flow Control after forcing link up. */ 3987 ret_val = e1000_config_fc_after_link_up(hw); 3988 if (ret_val < 0) { 3989 DEBUGOUT("Error configuring flow control\n"); 3990 return ret_val; 3991 } 3992 } 3993 /* If we are forcing link and we are receiving /C/ ordered sets, re-enable 3994 * auto-negotiation in the TXCW register and disable forced link in the 3995 * Device Control register in an attempt to auto-negotiate with our link 3996 * partner. 3997 */ 3998 else if ((hw->media_type == e1000_media_type_fiber) && 3999 (ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) { 4000 DEBUGOUT 4001 ("RXing /C/, enable AutoNeg and stop forcing link.\r\n"); 4002 E1000_WRITE_REG(hw, TXCW, hw->txcw); 4003 E1000_WRITE_REG(hw, CTRL, (ctrl & ~E1000_CTRL_SLU)); 4004 } 4005 return 0; 4006} 4007 4008/****************************************************************************** 4009* Configure the MAC-to-PHY interface for 10/100Mbps 4010* 4011* hw - Struct containing variables accessed by shared code 4012******************************************************************************/ 4013static int32_t 4014e1000_configure_kmrn_for_10_100(struct e1000_hw *hw, uint16_t duplex) 4015{ 4016 int32_t ret_val = E1000_SUCCESS; 4017 uint32_t tipg; 4018 uint16_t reg_data; 4019 4020 DEBUGFUNC(); 4021 4022 reg_data = E1000_KUMCTRLSTA_HD_CTRL_10_100_DEFAULT; 4023 ret_val = e1000_write_kmrn_reg(hw, 4024 E1000_KUMCTRLSTA_OFFSET_HD_CTRL, reg_data); 4025 if (ret_val) 4026 return ret_val; 4027 4028 /* Configure Transmit Inter-Packet Gap */ 4029 tipg = E1000_READ_REG(hw, TIPG); 4030 tipg &= ~E1000_TIPG_IPGT_MASK; 4031 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGT_10_100; 4032 E1000_WRITE_REG(hw, TIPG, tipg); 4033 4034 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, ®_data); 4035 4036 if (ret_val) 4037 return ret_val; 4038 4039 if (duplex == HALF_DUPLEX) 4040 reg_data |= GG82563_KMCR_PASS_FALSE_CARRIER; 4041 else 4042 reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER; 4043 4044 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data); 4045 4046 return ret_val; 4047} 4048 4049static int32_t 4050e1000_configure_kmrn_for_1000(struct e1000_hw *hw) 4051{ 4052 int32_t ret_val = E1000_SUCCESS; 4053 uint16_t reg_data; 4054 uint32_t tipg; 4055 4056 DEBUGFUNC(); 4057 4058 reg_data = E1000_KUMCTRLSTA_HD_CTRL_1000_DEFAULT; 4059 ret_val = e1000_write_kmrn_reg(hw, 4060 E1000_KUMCTRLSTA_OFFSET_HD_CTRL, reg_data); 4061 if (ret_val) 4062 return ret_val; 4063 4064 /* Configure Transmit Inter-Packet Gap */ 4065 tipg = E1000_READ_REG(hw, TIPG); 4066 tipg &= ~E1000_TIPG_IPGT_MASK; 4067 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGT_1000; 4068 E1000_WRITE_REG(hw, TIPG, tipg); 4069 4070 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, ®_data); 4071 4072 if (ret_val) 4073 return ret_val; 4074 4075 reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER; 4076 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data); 4077 4078 return ret_val; 4079} 4080 4081/****************************************************************************** 4082 * Detects the current speed and duplex settings of the hardware. 4083 * 4084 * hw - Struct containing variables accessed by shared code 4085 * speed - Speed of the connection 4086 * duplex - Duplex setting of the connection 4087 *****************************************************************************/ 4088static int 4089e1000_get_speed_and_duplex(struct e1000_hw *hw, uint16_t *speed, 4090 uint16_t *duplex) 4091{ 4092 uint32_t status; 4093 int32_t ret_val; 4094 uint16_t phy_data; 4095 4096 DEBUGFUNC(); 4097 4098 if (hw->mac_type >= e1000_82543) { 4099 status = E1000_READ_REG(hw, STATUS); 4100 if (status & E1000_STATUS_SPEED_1000) { 4101 *speed = SPEED_1000; 4102 DEBUGOUT("1000 Mbs, "); 4103 } else if (status & E1000_STATUS_SPEED_100) { 4104 *speed = SPEED_100; 4105 DEBUGOUT("100 Mbs, "); 4106 } else { 4107 *speed = SPEED_10; 4108 DEBUGOUT("10 Mbs, "); 4109 } 4110 4111 if (status & E1000_STATUS_FD) { 4112 *duplex = FULL_DUPLEX; 4113 DEBUGOUT("Full Duplex\r\n"); 4114 } else { 4115 *duplex = HALF_DUPLEX; 4116 DEBUGOUT(" Half Duplex\r\n"); 4117 } 4118 } else { 4119 DEBUGOUT("1000 Mbs, Full Duplex\r\n"); 4120 *speed = SPEED_1000; 4121 *duplex = FULL_DUPLEX; 4122 } 4123 4124 /* IGP01 PHY may advertise full duplex operation after speed downgrade 4125 * even if it is operating at half duplex. Here we set the duplex 4126 * settings to match the duplex in the link partner's capabilities. 4127 */ 4128 if (hw->phy_type == e1000_phy_igp && hw->speed_downgraded) { 4129 ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_EXP, &phy_data); 4130 if (ret_val) 4131 return ret_val; 4132 4133 if (!(phy_data & NWAY_ER_LP_NWAY_CAPS)) 4134 *duplex = HALF_DUPLEX; 4135 else { 4136 ret_val = e1000_read_phy_reg(hw, 4137 PHY_LP_ABILITY, &phy_data); 4138 if (ret_val) 4139 return ret_val; 4140 if ((*speed == SPEED_100 && 4141 !(phy_data & NWAY_LPAR_100TX_FD_CAPS)) 4142 || (*speed == SPEED_10 4143 && !(phy_data & NWAY_LPAR_10T_FD_CAPS))) 4144 *duplex = HALF_DUPLEX; 4145 } 4146 } 4147 4148 if ((hw->mac_type == e1000_80003es2lan) && 4149 (hw->media_type == e1000_media_type_copper)) { 4150 if (*speed == SPEED_1000) 4151 ret_val = e1000_configure_kmrn_for_1000(hw); 4152 else 4153 ret_val = e1000_configure_kmrn_for_10_100(hw, *duplex); 4154 if (ret_val) 4155 return ret_val; 4156 } 4157 return E1000_SUCCESS; 4158} 4159 4160/****************************************************************************** 4161* Blocks until autoneg completes or times out (~4.5 seconds) 4162* 4163* hw - Struct containing variables accessed by shared code 4164******************************************************************************/ 4165static int 4166e1000_wait_autoneg(struct e1000_hw *hw) 4167{ 4168 uint16_t i; 4169 uint16_t phy_data; 4170 4171 DEBUGFUNC(); 4172 DEBUGOUT("Waiting for Auto-Neg to complete.\n"); 4173 4174 /* We will wait for autoneg to complete or timeout to expire. */ 4175 for (i = PHY_AUTO_NEG_TIME; i > 0; i--) { 4176 /* Read the MII Status Register and wait for Auto-Neg 4177 * Complete bit to be set. 4178 */ 4179 if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) { 4180 DEBUGOUT("PHY Read Error\n"); 4181 return -E1000_ERR_PHY; 4182 } 4183 if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) { 4184 DEBUGOUT("PHY Read Error\n"); 4185 return -E1000_ERR_PHY; 4186 } 4187 if (phy_data & MII_SR_AUTONEG_COMPLETE) { 4188 DEBUGOUT("Auto-Neg complete.\n"); 4189 return 0; 4190 } 4191 mdelay(100); 4192 } 4193 DEBUGOUT("Auto-Neg timedout.\n"); 4194 return -E1000_ERR_TIMEOUT; 4195} 4196 4197/****************************************************************************** 4198* Raises the Management Data Clock 4199* 4200* hw - Struct containing variables accessed by shared code 4201* ctrl - Device control register's current value 4202******************************************************************************/ 4203static void 4204e1000_raise_mdi_clk(struct e1000_hw *hw, uint32_t * ctrl) 4205{ 4206 /* Raise the clock input to the Management Data Clock (by setting the MDC 4207 * bit), and then delay 2 microseconds. 4208 */ 4209 E1000_WRITE_REG(hw, CTRL, (*ctrl | E1000_CTRL_MDC)); 4210 E1000_WRITE_FLUSH(hw); 4211 udelay(2); 4212} 4213 4214/****************************************************************************** 4215* Lowers the Management Data Clock 4216* 4217* hw - Struct containing variables accessed by shared code 4218* ctrl - Device control register's current value 4219******************************************************************************/ 4220static void 4221e1000_lower_mdi_clk(struct e1000_hw *hw, uint32_t * ctrl) 4222{ 4223 /* Lower the clock input to the Management Data Clock (by clearing the MDC 4224 * bit), and then delay 2 microseconds. 4225 */ 4226 E1000_WRITE_REG(hw, CTRL, (*ctrl & ~E1000_CTRL_MDC)); 4227 E1000_WRITE_FLUSH(hw); 4228 udelay(2); 4229} 4230 4231/****************************************************************************** 4232* Shifts data bits out to the PHY 4233* 4234* hw - Struct containing variables accessed by shared code 4235* data - Data to send out to the PHY 4236* count - Number of bits to shift out 4237* 4238* Bits are shifted out in MSB to LSB order. 4239******************************************************************************/ 4240static void 4241e1000_shift_out_mdi_bits(struct e1000_hw *hw, uint32_t data, uint16_t count) 4242{ 4243 uint32_t ctrl; 4244 uint32_t mask; 4245 4246 /* We need to shift "count" number of bits out to the PHY. So, the value 4247 * in the "data" parameter will be shifted out to the PHY one bit at a 4248 * time. In order to do this, "data" must be broken down into bits. 4249 */ 4250 mask = 0x01; 4251 mask <<= (count - 1); 4252 4253 ctrl = E1000_READ_REG(hw, CTRL); 4254 4255 /* Set MDIO_DIR and MDC_DIR direction bits to be used as output pins. */ 4256 ctrl |= (E1000_CTRL_MDIO_DIR | E1000_CTRL_MDC_DIR); 4257 4258 while (mask) { 4259 /* A "1" is shifted out to the PHY by setting the MDIO bit to "1" and 4260 * then raising and lowering the Management Data Clock. A "0" is 4261 * shifted out to the PHY by setting the MDIO bit to "0" and then 4262 * raising and lowering the clock. 4263 */ 4264 if (data & mask) 4265 ctrl |= E1000_CTRL_MDIO; 4266 else 4267 ctrl &= ~E1000_CTRL_MDIO; 4268 4269 E1000_WRITE_REG(hw, CTRL, ctrl); 4270 E1000_WRITE_FLUSH(hw); 4271 4272 udelay(2); 4273 4274 e1000_raise_mdi_clk(hw, &ctrl); 4275 e1000_lower_mdi_clk(hw, &ctrl); 4276 4277 mask = mask >> 1; 4278 } 4279} 4280 4281/****************************************************************************** 4282* Shifts data bits in from the PHY 4283* 4284* hw - Struct containing variables accessed by shared code 4285* 4286* Bits are shifted in in MSB to LSB order. 4287******************************************************************************/ 4288static uint16_t 4289e1000_shift_in_mdi_bits(struct e1000_hw *hw) 4290{ 4291 uint32_t ctrl; 4292 uint16_t data = 0; 4293 uint8_t i; 4294 4295 /* In order to read a register from the PHY, we need to shift in a total 4296 * of 18 bits from the PHY. The first two bit (turnaround) times are used 4297 * to avoid contention on the MDIO pin when a read operation is performed. 4298 * These two bits are ignored by us and thrown away. Bits are "shifted in" 4299 * by raising the input to the Management Data Clock (setting the MDC bit), 4300 * and then reading the value of the MDIO bit. 4301 */ 4302 ctrl = E1000_READ_REG(hw, CTRL); 4303 4304 /* Clear MDIO_DIR (SWDPIO1) to indicate this bit is to be used as input. */ 4305 ctrl &= ~E1000_CTRL_MDIO_DIR; 4306 ctrl &= ~E1000_CTRL_MDIO; 4307 4308 E1000_WRITE_REG(hw, CTRL, ctrl); 4309 E1000_WRITE_FLUSH(hw); 4310 4311 /* Raise and Lower the clock before reading in the data. This accounts for 4312 * the turnaround bits. The first clock occurred when we clocked out the 4313 * last bit of the Register Address. 4314 */ 4315 e1000_raise_mdi_clk(hw, &ctrl); 4316 e1000_lower_mdi_clk(hw, &ctrl); 4317 4318 for (data = 0, i = 0; i < 16; i++) { 4319 data = data << 1; 4320 e1000_raise_mdi_clk(hw, &ctrl); 4321 ctrl = E1000_READ_REG(hw, CTRL); 4322 /* Check to see if we shifted in a "1". */ 4323 if (ctrl & E1000_CTRL_MDIO) 4324 data |= 1; 4325 e1000_lower_mdi_clk(hw, &ctrl); 4326 } 4327 4328 e1000_raise_mdi_clk(hw, &ctrl); 4329 e1000_lower_mdi_clk(hw, &ctrl); 4330 4331 return data; 4332} 4333 4334/***************************************************************************** 4335* Reads the value from a PHY register 4336* 4337* hw - Struct containing variables accessed by shared code 4338* reg_addr - address of the PHY register to read 4339******************************************************************************/ 4340static int 4341e1000_read_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t * phy_data) 4342{ 4343 uint32_t i; 4344 uint32_t mdic = 0; 4345 const uint32_t phy_addr = 1; 4346 4347 if (reg_addr > MAX_PHY_REG_ADDRESS) { 4348 DEBUGOUT("PHY Address %d is out of range\n", reg_addr); 4349 return -E1000_ERR_PARAM; 4350 } 4351 4352 if (hw->mac_type > e1000_82543) { 4353 /* Set up Op-code, Phy Address, and register address in the MDI 4354 * Control register. The MAC will take care of interfacing with the 4355 * PHY to retrieve the desired data. 4356 */ 4357 mdic = ((reg_addr << E1000_MDIC_REG_SHIFT) | 4358 (phy_addr << E1000_MDIC_PHY_SHIFT) | 4359 (E1000_MDIC_OP_READ)); 4360 4361 E1000_WRITE_REG(hw, MDIC, mdic); 4362 4363 /* Poll the ready bit to see if the MDI read completed */ 4364 for (i = 0; i < 64; i++) { 4365 udelay(10); 4366 mdic = E1000_READ_REG(hw, MDIC); 4367 if (mdic & E1000_MDIC_READY) 4368 break; 4369 } 4370 if (!(mdic & E1000_MDIC_READY)) { 4371 DEBUGOUT("MDI Read did not complete\n"); 4372 return -E1000_ERR_PHY; 4373 } 4374 if (mdic & E1000_MDIC_ERROR) { 4375 DEBUGOUT("MDI Error\n"); 4376 return -E1000_ERR_PHY; 4377 } 4378 *phy_data = (uint16_t) mdic; 4379 } else { 4380 /* We must first send a preamble through the MDIO pin to signal the 4381 * beginning of an MII instruction. This is done by sending 32 4382 * consecutive "1" bits. 4383 */ 4384 e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE); 4385 4386 /* Now combine the next few fields that are required for a read 4387 * operation. We use this method instead of calling the 4388 * e1000_shift_out_mdi_bits routine five different times. The format of 4389 * a MII read instruction consists of a shift out of 14 bits and is 4390 * defined as follows: 4391 * <Preamble><SOF><Op Code><Phy Addr><Reg Addr> 4392 * followed by a shift in of 18 bits. This first two bits shifted in 4393 * are TurnAround bits used to avoid contention on the MDIO pin when a 4394 * READ operation is performed. These two bits are thrown away 4395 * followed by a shift in of 16 bits which contains the desired data. 4396 */ 4397 mdic = ((reg_addr) | (phy_addr << 5) | 4398 (PHY_OP_READ << 10) | (PHY_SOF << 12)); 4399 4400 e1000_shift_out_mdi_bits(hw, mdic, 14); 4401 4402 /* Now that we've shifted out the read command to the MII, we need to 4403 * "shift in" the 16-bit value (18 total bits) of the requested PHY 4404 * register address. 4405 */ 4406 *phy_data = e1000_shift_in_mdi_bits(hw); 4407 } 4408 return 0; 4409} 4410 4411/****************************************************************************** 4412* Writes a value to a PHY register 4413* 4414* hw - Struct containing variables accessed by shared code 4415* reg_addr - address of the PHY register to write 4416* data - data to write to the PHY 4417******************************************************************************/ 4418static int 4419e1000_write_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t phy_data) 4420{ 4421 uint32_t i; 4422 uint32_t mdic = 0; 4423 const uint32_t phy_addr = 1; 4424 4425 if (reg_addr > MAX_PHY_REG_ADDRESS) { 4426 DEBUGOUT("PHY Address %d is out of range\n", reg_addr); 4427 return -E1000_ERR_PARAM; 4428 } 4429 4430 if (hw->mac_type > e1000_82543) { 4431 /* Set up Op-code, Phy Address, register address, and data intended 4432 * for the PHY register in the MDI Control register. The MAC will take 4433 * care of interfacing with the PHY to send the desired data. 4434 */ 4435 mdic = (((uint32_t) phy_data) | 4436 (reg_addr << E1000_MDIC_REG_SHIFT) | 4437 (phy_addr << E1000_MDIC_PHY_SHIFT) | 4438 (E1000_MDIC_OP_WRITE)); 4439 4440 E1000_WRITE_REG(hw, MDIC, mdic); 4441 4442 /* Poll the ready bit to see if the MDI read completed */ 4443 for (i = 0; i < 64; i++) { 4444 udelay(10); 4445 mdic = E1000_READ_REG(hw, MDIC); 4446 if (mdic & E1000_MDIC_READY) 4447 break; 4448 } 4449 if (!(mdic & E1000_MDIC_READY)) { 4450 DEBUGOUT("MDI Write did not complete\n"); 4451 return -E1000_ERR_PHY; 4452 } 4453 } else { 4454 /* We'll need to use the SW defined pins to shift the write command 4455 * out to the PHY. We first send a preamble to the PHY to signal the 4456 * beginning of the MII instruction. This is done by sending 32 4457 * consecutive "1" bits. 4458 */ 4459 e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE); 4460 4461 /* Now combine the remaining required fields that will indicate a 4462 * write operation. We use this method instead of calling the 4463 * e1000_shift_out_mdi_bits routine for each field in the command. The 4464 * format of a MII write instruction is as follows: 4465 * <Preamble><SOF><Op Code><Phy Addr><Reg Addr><Turnaround><Data>. 4466 */ 4467 mdic = ((PHY_TURNAROUND) | (reg_addr << 2) | (phy_addr << 7) | 4468 (PHY_OP_WRITE << 12) | (PHY_SOF << 14)); 4469 mdic <<= 16; 4470 mdic |= (uint32_t) phy_data; 4471 4472 e1000_shift_out_mdi_bits(hw, mdic, 32); 4473 } 4474 return 0; 4475} 4476 4477/****************************************************************************** 4478 * Checks if PHY reset is blocked due to SOL/IDER session, for example. 4479 * Returning E1000_BLK_PHY_RESET isn't necessarily an error. But it's up to 4480 * the caller to figure out how to deal with it. 4481 * 4482 * hw - Struct containing variables accessed by shared code 4483 * 4484 * returns: - E1000_BLK_PHY_RESET 4485 * E1000_SUCCESS 4486 * 4487 *****************************************************************************/ 4488int32_t 4489e1000_check_phy_reset_block(struct e1000_hw *hw) 4490{ 4491 uint32_t manc = 0; 4492 uint32_t fwsm = 0; 4493 4494 if (hw->mac_type == e1000_ich8lan) { 4495 fwsm = E1000_READ_REG(hw, FWSM); 4496 return (fwsm & E1000_FWSM_RSPCIPHY) ? E1000_SUCCESS 4497 : E1000_BLK_PHY_RESET; 4498 } 4499 4500 if (hw->mac_type > e1000_82547_rev_2) 4501 manc = E1000_READ_REG(hw, MANC); 4502 return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ? 4503 E1000_BLK_PHY_RESET : E1000_SUCCESS; 4504} 4505 4506/*************************************************************************** 4507 * Checks if the PHY configuration is done 4508 * 4509 * hw: Struct containing variables accessed by shared code 4510 * 4511 * returns: - E1000_ERR_RESET if fail to reset MAC 4512 * E1000_SUCCESS at any other case. 4513 * 4514 ***************************************************************************/ 4515static int32_t 4516e1000_get_phy_cfg_done(struct e1000_hw *hw) 4517{ 4518 int32_t timeout = PHY_CFG_TIMEOUT; 4519 uint32_t cfg_mask = E1000_EEPROM_CFG_DONE; 4520 4521 DEBUGFUNC(); 4522 4523 switch (hw->mac_type) { 4524 default: 4525 mdelay(10); 4526 break; 4527 4528 case e1000_80003es2lan: 4529 /* Separate *_CFG_DONE_* bit for each port */ 4530 if (e1000_is_second_port(hw)) 4531 cfg_mask = E1000_EEPROM_CFG_DONE_PORT_1; 4532 /* Fall Through */ 4533 4534 case e1000_82571: 4535 case e1000_82572: 4536 case e1000_igb: 4537 while (timeout) { 4538 if (hw->mac_type == e1000_igb) { 4539 if (hw->phy_type == e1000_phy_igc) 4540 break; 4541 if (E1000_READ_REG(hw, I210_EEMNGCTL) & cfg_mask) 4542 break; 4543 } else { 4544 if (E1000_READ_REG(hw, EEMNGCTL) & cfg_mask) 4545 break; 4546 } 4547 mdelay(1); 4548 timeout--; 4549 } 4550 if (!timeout) { 4551 DEBUGOUT("MNG configuration cycle has not " 4552 "completed.\n"); 4553 return -E1000_ERR_RESET; 4554 } 4555 break; 4556 } 4557 4558 return E1000_SUCCESS; 4559} 4560 4561/****************************************************************************** 4562* Returns the PHY to the power-on reset state 4563* 4564* hw - Struct containing variables accessed by shared code 4565******************************************************************************/ 4566int32_t 4567e1000_phy_hw_reset(struct e1000_hw *hw) 4568{ 4569 uint16_t swfw = E1000_SWFW_PHY0_SM; 4570 uint32_t ctrl, ctrl_ext; 4571 uint32_t led_ctrl; 4572 int32_t ret_val; 4573 4574 DEBUGFUNC(); 4575 4576 /* In the case of the phy reset being blocked, it's not an error, we 4577 * simply return success without performing the reset. */ 4578 ret_val = e1000_check_phy_reset_block(hw); 4579 if (ret_val) 4580 return E1000_SUCCESS; 4581 4582 DEBUGOUT("Resetting Phy...\n"); 4583 4584 if (hw->mac_type > e1000_82543) { 4585 if (e1000_is_second_port(hw)) 4586 swfw = E1000_SWFW_PHY1_SM; 4587 4588 if (e1000_swfw_sync_acquire(hw, swfw)) { 4589 DEBUGOUT("Unable to acquire swfw sync\n"); 4590 return -E1000_ERR_SWFW_SYNC; 4591 } 4592 4593 /* Read the device control register and assert the E1000_CTRL_PHY_RST 4594 * bit. Then, take it out of reset. 4595 */ 4596 ctrl = E1000_READ_REG(hw, CTRL); 4597 E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PHY_RST); 4598 E1000_WRITE_FLUSH(hw); 4599 4600 if (hw->mac_type < e1000_82571) 4601 udelay(10); 4602 else 4603 udelay(100); 4604 4605 E1000_WRITE_REG(hw, CTRL, ctrl); 4606 E1000_WRITE_FLUSH(hw); 4607 4608 if (hw->mac_type >= e1000_82571) 4609 mdelay(10); 4610 4611 } else { 4612 /* Read the Extended Device Control Register, assert the PHY_RESET_DIR 4613 * bit to put the PHY into reset. Then, take it out of reset. 4614 */ 4615 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); 4616 ctrl_ext |= E1000_CTRL_EXT_SDP4_DIR; 4617 ctrl_ext &= ~E1000_CTRL_EXT_SDP4_DATA; 4618 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); 4619 E1000_WRITE_FLUSH(hw); 4620 mdelay(10); 4621 ctrl_ext |= E1000_CTRL_EXT_SDP4_DATA; 4622 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); 4623 E1000_WRITE_FLUSH(hw); 4624 } 4625 udelay(150); 4626 4627 if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) { 4628 /* Configure activity LED after PHY reset */ 4629 led_ctrl = E1000_READ_REG(hw, LEDCTL); 4630 led_ctrl &= IGP_ACTIVITY_LED_MASK; 4631 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE); 4632 E1000_WRITE_REG(hw, LEDCTL, led_ctrl); 4633 } 4634 4635 e1000_swfw_sync_release(hw, swfw); 4636 4637 /* Wait for FW to finish PHY configuration. */ 4638 ret_val = e1000_get_phy_cfg_done(hw); 4639 if (ret_val != E1000_SUCCESS) 4640 return ret_val; 4641 4642 return ret_val; 4643} 4644 4645/****************************************************************************** 4646 * IGP phy init script - initializes the GbE PHY 4647 * 4648 * hw - Struct containing variables accessed by shared code 4649 *****************************************************************************/ 4650static void 4651e1000_phy_init_script(struct e1000_hw *hw) 4652{ 4653 uint32_t ret_val; 4654 uint16_t phy_saved_data; 4655 DEBUGFUNC(); 4656 4657 if (hw->phy_init_script) { 4658 mdelay(20); 4659 4660 /* Save off the current value of register 0x2F5B to be 4661 * restored at the end of this routine. */ 4662 ret_val = e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data); 4663 4664 /* Disabled the PHY transmitter */ 4665 e1000_write_phy_reg(hw, 0x2F5B, 0x0003); 4666 4667 mdelay(20); 4668 4669 e1000_write_phy_reg(hw, 0x0000, 0x0140); 4670 4671 mdelay(5); 4672 4673 switch (hw->mac_type) { 4674 case e1000_82541: 4675 case e1000_82547: 4676 e1000_write_phy_reg(hw, 0x1F95, 0x0001); 4677 4678 e1000_write_phy_reg(hw, 0x1F71, 0xBD21); 4679 4680 e1000_write_phy_reg(hw, 0x1F79, 0x0018); 4681 4682 e1000_write_phy_reg(hw, 0x1F30, 0x1600); 4683 4684 e1000_write_phy_reg(hw, 0x1F31, 0x0014); 4685 4686 e1000_write_phy_reg(hw, 0x1F32, 0x161C); 4687 4688 e1000_write_phy_reg(hw, 0x1F94, 0x0003); 4689 4690 e1000_write_phy_reg(hw, 0x1F96, 0x003F); 4691 4692 e1000_write_phy_reg(hw, 0x2010, 0x0008); 4693 break; 4694 4695 case e1000_82541_rev_2: 4696 case e1000_82547_rev_2: 4697 e1000_write_phy_reg(hw, 0x1F73, 0x0099); 4698 break; 4699 default: 4700 break; 4701 } 4702 4703 e1000_write_phy_reg(hw, 0x0000, 0x3300); 4704 4705 mdelay(20); 4706 4707 /* Now enable the transmitter */ 4708 if (!ret_val) 4709 e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data); 4710 4711 if (hw->mac_type == e1000_82547) { 4712 uint16_t fused, fine, coarse; 4713 4714 /* Move to analog registers page */ 4715 e1000_read_phy_reg(hw, 4716 IGP01E1000_ANALOG_SPARE_FUSE_STATUS, &fused); 4717 4718 if (!(fused & IGP01E1000_ANALOG_SPARE_FUSE_ENABLED)) { 4719 e1000_read_phy_reg(hw, 4720 IGP01E1000_ANALOG_FUSE_STATUS, &fused); 4721 4722 fine = fused & IGP01E1000_ANALOG_FUSE_FINE_MASK; 4723 coarse = fused 4724 & IGP01E1000_ANALOG_FUSE_COARSE_MASK; 4725 4726 if (coarse > 4727 IGP01E1000_ANALOG_FUSE_COARSE_THRESH) { 4728 coarse -= 4729 IGP01E1000_ANALOG_FUSE_COARSE_10; 4730 fine -= IGP01E1000_ANALOG_FUSE_FINE_1; 4731 } else if (coarse 4732 == IGP01E1000_ANALOG_FUSE_COARSE_THRESH) 4733 fine -= IGP01E1000_ANALOG_FUSE_FINE_10; 4734 4735 fused = (fused 4736 & IGP01E1000_ANALOG_FUSE_POLY_MASK) | 4737 (fine 4738 & IGP01E1000_ANALOG_FUSE_FINE_MASK) | 4739 (coarse 4740 & IGP01E1000_ANALOG_FUSE_COARSE_MASK); 4741 4742 e1000_write_phy_reg(hw, 4743 IGP01E1000_ANALOG_FUSE_CONTROL, fused); 4744 e1000_write_phy_reg(hw, 4745 IGP01E1000_ANALOG_FUSE_BYPASS, 4746 IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL); 4747 } 4748 } 4749 } 4750} 4751 4752/****************************************************************************** 4753* Resets the PHY 4754* 4755* hw - Struct containing variables accessed by shared code 4756* 4757* Sets bit 15 of the MII Control register 4758******************************************************************************/ 4759int32_t 4760e1000_phy_reset(struct e1000_hw *hw) 4761{ 4762 int32_t ret_val; 4763 uint16_t phy_data; 4764 4765 DEBUGFUNC(); 4766 4767 /* In the case of the phy reset being blocked, it's not an error, we 4768 * simply return success without performing the reset. */ 4769 ret_val = e1000_check_phy_reset_block(hw); 4770 if (ret_val) 4771 return E1000_SUCCESS; 4772 4773 switch (hw->phy_type) { 4774 case e1000_phy_igp: 4775 case e1000_phy_igp_2: 4776 case e1000_phy_igp_3: 4777 case e1000_phy_ife: 4778 case e1000_phy_igb: 4779 case e1000_phy_igc: 4780 ret_val = e1000_phy_hw_reset(hw); 4781 if (ret_val) 4782 return ret_val; 4783 break; 4784 default: 4785 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data); 4786 if (ret_val) 4787 return ret_val; 4788 4789 phy_data |= MII_CR_RESET; 4790 ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data); 4791 if (ret_val) 4792 return ret_val; 4793 4794 udelay(1); 4795 break; 4796 } 4797 4798 if (hw->phy_type == e1000_phy_igp || hw->phy_type == e1000_phy_igp_2) 4799 e1000_phy_init_script(hw); 4800 4801 return E1000_SUCCESS; 4802} 4803 4804static int e1000_set_phy_type (struct e1000_hw *hw) 4805{ 4806 DEBUGFUNC (); 4807 4808 if (hw->mac_type == e1000_undefined) 4809 return -E1000_ERR_PHY_TYPE; 4810 4811 switch (hw->phy_id) { 4812 case M88E1000_E_PHY_ID: 4813 case M88E1000_I_PHY_ID: 4814 case M88E1011_I_PHY_ID: 4815 case M88E1111_I_PHY_ID: 4816 hw->phy_type = e1000_phy_m88; 4817 break; 4818 case IGP01E1000_I_PHY_ID: 4819 if (hw->mac_type == e1000_82541 || 4820 hw->mac_type == e1000_82541_rev_2 || 4821 hw->mac_type == e1000_82547 || 4822 hw->mac_type == e1000_82547_rev_2) { 4823 hw->phy_type = e1000_phy_igp; 4824 break; 4825 } 4826 case IGP03E1000_E_PHY_ID: 4827 hw->phy_type = e1000_phy_igp_3; 4828 break; 4829 case IFE_E_PHY_ID: 4830 case IFE_PLUS_E_PHY_ID: 4831 case IFE_C_E_PHY_ID: 4832 hw->phy_type = e1000_phy_ife; 4833 break; 4834 case GG82563_E_PHY_ID: 4835 if (hw->mac_type == e1000_80003es2lan) { 4836 hw->phy_type = e1000_phy_gg82563; 4837 break; 4838 } 4839 case BME1000_E_PHY_ID: 4840 hw->phy_type = e1000_phy_bm; 4841 break; 4842 case I210_I_PHY_ID: 4843 hw->phy_type = e1000_phy_igb; 4844 break; 4845 case I225_I_PHY_ID: 4846 hw->phy_type = e1000_phy_igc; 4847 break; 4848 /* Fall Through */ 4849 default: 4850 /* Should never have loaded on this device */ 4851 hw->phy_type = e1000_phy_undefined; 4852 return -E1000_ERR_PHY_TYPE; 4853 } 4854 4855 return E1000_SUCCESS; 4856} 4857 4858/****************************************************************************** 4859* Probes the expected PHY address for known PHY IDs 4860* 4861* hw - Struct containing variables accessed by shared code 4862******************************************************************************/ 4863static int32_t 4864e1000_detect_gig_phy(struct e1000_hw *hw) 4865{ 4866 int32_t phy_init_status, ret_val; 4867 uint16_t phy_id_high, phy_id_low; 4868 bool match = false; 4869 4870 DEBUGFUNC(); 4871 4872 /* The 82571 firmware may still be configuring the PHY. In this 4873 * case, we cannot access the PHY until the configuration is done. So 4874 * we explicitly set the PHY values. */ 4875 if (hw->mac_type == e1000_82571 || 4876 hw->mac_type == e1000_82572) { 4877 hw->phy_id = IGP01E1000_I_PHY_ID; 4878 hw->phy_type = e1000_phy_igp_2; 4879 return E1000_SUCCESS; 4880 } 4881 4882 /* ESB-2 PHY reads require e1000_phy_gg82563 to be set because of a 4883 * work- around that forces PHY page 0 to be set or the reads fail. 4884 * The rest of the code in this routine uses e1000_read_phy_reg to 4885 * read the PHY ID. So for ESB-2 we need to have this set so our 4886 * reads won't fail. If the attached PHY is not a e1000_phy_gg82563, 4887 * the routines below will figure this out as well. */ 4888 if (hw->mac_type == e1000_80003es2lan) 4889 hw->phy_type = e1000_phy_gg82563; 4890 4891 /* Read the PHY ID Registers to identify which PHY is onboard. */ 4892 ret_val = e1000_read_phy_reg(hw, PHY_ID1, &phy_id_high); 4893 if (ret_val) 4894 return ret_val; 4895 4896 hw->phy_id = (uint32_t) (phy_id_high << 16); 4897 udelay(20); 4898 ret_val = e1000_read_phy_reg(hw, PHY_ID2, &phy_id_low); 4899 if (ret_val) 4900 return ret_val; 4901 4902 hw->phy_id |= (uint32_t) (phy_id_low & PHY_REVISION_MASK); 4903 hw->phy_revision = (uint32_t) phy_id_low & ~PHY_REVISION_MASK; 4904 4905 switch (hw->mac_type) { 4906 case e1000_82543: 4907 if (hw->phy_id == M88E1000_E_PHY_ID) 4908 match = true; 4909 break; 4910 case e1000_82544: 4911 if (hw->phy_id == M88E1000_I_PHY_ID) 4912 match = true; 4913 break; 4914 case e1000_82540: 4915 case e1000_82545: 4916 case e1000_82545_rev_3: 4917 case e1000_82546: 4918 case e1000_82546_rev_3: 4919 if (hw->phy_id == M88E1011_I_PHY_ID) 4920 match = true; 4921 break; 4922 case e1000_82541: 4923 case e1000_82541_rev_2: 4924 case e1000_82547: 4925 case e1000_82547_rev_2: 4926 if(hw->phy_id == IGP01E1000_I_PHY_ID) 4927 match = true; 4928 4929 break; 4930 case e1000_82573: 4931 if (hw->phy_id == M88E1111_I_PHY_ID) 4932 match = true; 4933 break; 4934 case e1000_82574: 4935 if (hw->phy_id == BME1000_E_PHY_ID) 4936 match = true; 4937 break; 4938 case e1000_80003es2lan: 4939 if (hw->phy_id == GG82563_E_PHY_ID) 4940 match = true; 4941 break; 4942 case e1000_ich8lan: 4943 if (hw->phy_id == IGP03E1000_E_PHY_ID) 4944 match = true; 4945 if (hw->phy_id == IFE_E_PHY_ID) 4946 match = true; 4947 if (hw->phy_id == IFE_PLUS_E_PHY_ID) 4948 match = true; 4949 if (hw->phy_id == IFE_C_E_PHY_ID) 4950 match = true; 4951 break; 4952 case e1000_igb: 4953 if (hw->phy_id == I210_I_PHY_ID) 4954 match = true; 4955 if (hw->phy_id == I225_I_PHY_ID) 4956 match = true; 4957 break; 4958 default: 4959 DEBUGOUT("Invalid MAC type %d\n", hw->mac_type); 4960 return -E1000_ERR_CONFIG; 4961 } 4962 4963 phy_init_status = e1000_set_phy_type(hw); 4964 4965 if ((match) && (phy_init_status == E1000_SUCCESS)) { 4966 DEBUGOUT("PHY ID 0x%X detected\n", hw->phy_id); 4967 return 0; 4968 } 4969 DEBUGOUT("Invalid PHY ID 0x%X\n", hw->phy_id); 4970 return -E1000_ERR_PHY; 4971} 4972 4973/***************************************************************************** 4974 * Set media type and TBI compatibility. 4975 * 4976 * hw - Struct containing variables accessed by shared code 4977 * **************************************************************************/ 4978void 4979e1000_set_media_type(struct e1000_hw *hw) 4980{ 4981 uint32_t status; 4982 4983 DEBUGFUNC(); 4984 4985 if (hw->mac_type != e1000_82543) { 4986 /* tbi_compatibility is only valid on 82543 */ 4987 hw->tbi_compatibility_en = false; 4988 } 4989 4990 switch (hw->device_id) { 4991 case E1000_DEV_ID_82545GM_SERDES: 4992 case E1000_DEV_ID_82546GB_SERDES: 4993 case E1000_DEV_ID_82571EB_SERDES: 4994 case E1000_DEV_ID_82571EB_SERDES_DUAL: 4995 case E1000_DEV_ID_82571EB_SERDES_QUAD: 4996 case E1000_DEV_ID_82572EI_SERDES: 4997 case E1000_DEV_ID_80003ES2LAN_SERDES_DPT: 4998 hw->media_type = e1000_media_type_internal_serdes; 4999 break; 5000 default: 5001 switch (hw->mac_type) { 5002 case e1000_82542_rev2_0: 5003 case e1000_82542_rev2_1: 5004 hw->media_type = e1000_media_type_fiber; 5005 break; 5006 case e1000_ich8lan: 5007 case e1000_82573: 5008 case e1000_82574: 5009 case e1000_igb: 5010 /* The STATUS_TBIMODE bit is reserved or reused 5011 * for the this device. 5012 */ 5013 hw->media_type = e1000_media_type_copper; 5014 break; 5015 default: 5016 status = E1000_READ_REG(hw, STATUS); 5017 if (status & E1000_STATUS_TBIMODE) { 5018 hw->media_type = e1000_media_type_fiber; 5019 /* tbi_compatibility not valid on fiber */ 5020 hw->tbi_compatibility_en = false; 5021 } else { 5022 hw->media_type = e1000_media_type_copper; 5023 } 5024 break; 5025 } 5026 } 5027} 5028 5029/** 5030 * e1000_sw_init - Initialize general software structures (struct e1000_adapter) 5031 * 5032 * e1000_sw_init initializes the Adapter private data structure. 5033 * Fields are initialized based on PCI device information and 5034 * OS network device settings (MTU size). 5035 **/ 5036 5037static int 5038e1000_sw_init(struct e1000_hw *hw) 5039{ 5040 int result; 5041 5042 /* PCI config space info */ 5043 dm_pci_read_config16(hw->pdev, PCI_VENDOR_ID, &hw->vendor_id); 5044 dm_pci_read_config16(hw->pdev, PCI_DEVICE_ID, &hw->device_id); 5045 dm_pci_read_config16(hw->pdev, PCI_SUBSYSTEM_VENDOR_ID, 5046 &hw->subsystem_vendor_id); 5047 dm_pci_read_config16(hw->pdev, PCI_SUBSYSTEM_ID, &hw->subsystem_id); 5048 5049 dm_pci_read_config8(hw->pdev, PCI_REVISION_ID, &hw->revision_id); 5050 dm_pci_read_config16(hw->pdev, PCI_COMMAND, &hw->pci_cmd_word); 5051 5052 /* identify the MAC */ 5053 result = e1000_set_mac_type(hw); 5054 if (result) { 5055 E1000_ERR(hw, "Unknown MAC Type\n"); 5056 return result; 5057 } 5058 5059 switch (hw->mac_type) { 5060 default: 5061 break; 5062 case e1000_82541: 5063 case e1000_82547: 5064 case e1000_82541_rev_2: 5065 case e1000_82547_rev_2: 5066 hw->phy_init_script = 1; 5067 break; 5068 } 5069 5070 /* flow control settings */ 5071 hw->fc_high_water = E1000_FC_HIGH_THRESH; 5072 hw->fc_low_water = E1000_FC_LOW_THRESH; 5073 hw->fc_pause_time = E1000_FC_PAUSE_TIME; 5074 hw->fc_send_xon = 1; 5075 5076 /* Media type - copper or fiber */ 5077 hw->tbi_compatibility_en = true; 5078 e1000_set_media_type(hw); 5079 5080 if (hw->mac_type >= e1000_82543) { 5081 uint32_t status = E1000_READ_REG(hw, STATUS); 5082 5083 if (status & E1000_STATUS_TBIMODE) { 5084 DEBUGOUT("fiber interface\n"); 5085 hw->media_type = e1000_media_type_fiber; 5086 } else { 5087 DEBUGOUT("copper interface\n"); 5088 hw->media_type = e1000_media_type_copper; 5089 } 5090 } else { 5091 hw->media_type = e1000_media_type_fiber; 5092 } 5093 5094 hw->wait_autoneg_complete = true; 5095 if (hw->mac_type < e1000_82543) 5096 hw->report_tx_early = 0; 5097 else 5098 hw->report_tx_early = 1; 5099 5100 return E1000_SUCCESS; 5101} 5102 5103void 5104fill_rx(struct e1000_hw *hw) 5105{ 5106 struct e1000_rx_desc *rd; 5107 unsigned long flush_start, flush_end; 5108 5109 rx_last = rx_tail; 5110 rd = rx_base + rx_tail; 5111 rx_tail = (rx_tail + 1) % 8; 5112 memset(rd, 0, 16); 5113 rd->buffer_addr = cpu_to_le64(virt_to_phys(packet)); 5114 5115 /* 5116 * Make sure there are no stale data in WB over this area, which 5117 * might get written into the memory while the e1000 also writes 5118 * into the same memory area. 5119 */ 5120 invalidate_dcache_range((unsigned long)packet, 5121 (unsigned long)packet + 4096); 5122 /* Dump the DMA descriptor into RAM. */ 5123 flush_start = ((unsigned long)rd) & ~(ARCH_DMA_MINALIGN - 1); 5124 flush_end = flush_start + roundup(sizeof(*rd), ARCH_DMA_MINALIGN); 5125 flush_dcache_range(flush_start, flush_end); 5126 5127 E1000_WRITE_REG(hw, RDT, rx_tail); 5128} 5129 5130/** 5131 * e1000_configure_tx - Configure 8254x Transmit Unit after Reset 5132 * @adapter: board private structure 5133 * 5134 * Configure the Tx unit of the MAC after a reset. 5135 **/ 5136 5137static void 5138e1000_configure_tx(struct e1000_hw *hw) 5139{ 5140 unsigned long tctl; 5141 unsigned long tipg, tarc; 5142 uint32_t ipgr1, ipgr2; 5143 5144 E1000_WRITE_REG(hw, TDBAL, lower_32_bits(virt_to_phys(tx_base))); 5145 E1000_WRITE_REG(hw, TDBAH, upper_32_bits(virt_to_phys(tx_base))); 5146 5147 E1000_WRITE_REG(hw, TDLEN, 128); 5148 5149 /* Setup the HW Tx Head and Tail descriptor pointers */ 5150 E1000_WRITE_REG(hw, TDH, 0); 5151 E1000_WRITE_REG(hw, TDT, 0); 5152 tx_tail = 0; 5153 5154 /* Set the default values for the Tx Inter Packet Gap timer */ 5155 if (hw->mac_type <= e1000_82547_rev_2 && 5156 (hw->media_type == e1000_media_type_fiber || 5157 hw->media_type == e1000_media_type_internal_serdes)) 5158 tipg = DEFAULT_82543_TIPG_IPGT_FIBER; 5159 else 5160 tipg = DEFAULT_82543_TIPG_IPGT_COPPER; 5161 5162 /* Set the default values for the Tx Inter Packet Gap timer */ 5163 switch (hw->mac_type) { 5164 case e1000_82542_rev2_0: 5165 case e1000_82542_rev2_1: 5166 tipg = DEFAULT_82542_TIPG_IPGT; 5167 ipgr1 = DEFAULT_82542_TIPG_IPGR1; 5168 ipgr2 = DEFAULT_82542_TIPG_IPGR2; 5169 break; 5170 case e1000_80003es2lan: 5171 ipgr1 = DEFAULT_82543_TIPG_IPGR1; 5172 ipgr2 = DEFAULT_80003ES2LAN_TIPG_IPGR2; 5173 break; 5174 default: 5175 ipgr1 = DEFAULT_82543_TIPG_IPGR1; 5176 ipgr2 = DEFAULT_82543_TIPG_IPGR2; 5177 break; 5178 } 5179 tipg |= ipgr1 << E1000_TIPG_IPGR1_SHIFT; 5180 tipg |= ipgr2 << E1000_TIPG_IPGR2_SHIFT; 5181 E1000_WRITE_REG(hw, TIPG, tipg); 5182 /* Program the Transmit Control Register */ 5183 tctl = E1000_READ_REG(hw, TCTL); 5184 tctl &= ~E1000_TCTL_CT; 5185 tctl |= E1000_TCTL_EN | E1000_TCTL_PSP | 5186 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT); 5187 5188 if (hw->mac_type == e1000_82571 || hw->mac_type == e1000_82572) { 5189 tarc = E1000_READ_REG(hw, TARC0); 5190 /* set the speed mode bit, we'll clear it if we're not at 5191 * gigabit link later */ 5192 /* git bit can be set to 1*/ 5193 } else if (hw->mac_type == e1000_80003es2lan) { 5194 tarc = E1000_READ_REG(hw, TARC0); 5195 tarc |= 1; 5196 E1000_WRITE_REG(hw, TARC0, tarc); 5197 tarc = E1000_READ_REG(hw, TARC1); 5198 tarc |= 1; 5199 E1000_WRITE_REG(hw, TARC1, tarc); 5200 } 5201 5202 5203 e1000_config_collision_dist(hw); 5204 /* Setup Transmit Descriptor Settings for eop descriptor */ 5205 hw->txd_cmd = E1000_TXD_CMD_EOP | E1000_TXD_CMD_IFCS; 5206 5207 /* Need to set up RS bit */ 5208 if (hw->mac_type < e1000_82543) 5209 hw->txd_cmd |= E1000_TXD_CMD_RPS; 5210 else 5211 hw->txd_cmd |= E1000_TXD_CMD_RS; 5212 5213 5214 if (hw->mac_type == e1000_igb) { 5215 E1000_WRITE_REG(hw, TCTL_EXT, 0x42 << 10); 5216 5217 uint32_t reg_txdctl = E1000_READ_REG(hw, TXDCTL); 5218 reg_txdctl |= 1 << 25; 5219 E1000_WRITE_REG(hw, TXDCTL, reg_txdctl); 5220 mdelay(20); 5221 } 5222 5223 E1000_WRITE_REG(hw, TCTL, tctl); 5224} 5225 5226/** 5227 * e1000_setup_rctl - configure the receive control register 5228 * @adapter: Board private structure 5229 **/ 5230static void 5231e1000_setup_rctl(struct e1000_hw *hw) 5232{ 5233 uint32_t rctl; 5234 5235 rctl = E1000_READ_REG(hw, RCTL); 5236 5237 rctl &= ~(3 << E1000_RCTL_MO_SHIFT); 5238 5239 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_LBM_NO 5240 | E1000_RCTL_RDMTS_HALF; /* | 5241 (hw.mc_filter_type << E1000_RCTL_MO_SHIFT); */ 5242 5243 if (hw->tbi_compatibility_on == 1) 5244 rctl |= E1000_RCTL_SBP; 5245 else 5246 rctl &= ~E1000_RCTL_SBP; 5247 5248 rctl &= ~(E1000_RCTL_SZ_4096); 5249 rctl |= E1000_RCTL_SZ_2048; 5250 rctl &= ~(E1000_RCTL_BSEX | E1000_RCTL_LPE); 5251 E1000_WRITE_REG(hw, RCTL, rctl); 5252} 5253 5254/** 5255 * e1000_configure_rx - Configure 8254x Receive Unit after Reset 5256 * @adapter: board private structure 5257 * 5258 * Configure the Rx unit of the MAC after a reset. 5259 **/ 5260static void 5261e1000_configure_rx(struct e1000_hw *hw) 5262{ 5263 unsigned long rctl, ctrl_ext; 5264 rx_tail = 0; 5265 5266 /* make sure receives are disabled while setting up the descriptors */ 5267 rctl = E1000_READ_REG(hw, RCTL); 5268 E1000_WRITE_REG(hw, RCTL, rctl & ~E1000_RCTL_EN); 5269 if (hw->mac_type >= e1000_82540) { 5270 /* Set the interrupt throttling rate. Value is calculated 5271 * as DEFAULT_ITR = 1/(MAX_INTS_PER_SEC * 256ns) */ 5272#define MAX_INTS_PER_SEC 8000 5273#define DEFAULT_ITR 1000000000/(MAX_INTS_PER_SEC * 256) 5274 E1000_WRITE_REG(hw, ITR, DEFAULT_ITR); 5275 } 5276 5277 if (hw->mac_type >= e1000_82571) { 5278 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); 5279 /* Reset delay timers after every interrupt */ 5280 ctrl_ext |= E1000_CTRL_EXT_INT_TIMER_CLR; 5281 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); 5282 E1000_WRITE_FLUSH(hw); 5283 } 5284 /* Setup the Base and Length of the Rx Descriptor Ring */ 5285 E1000_WRITE_REG(hw, RDBAL, lower_32_bits(virt_to_phys(rx_base))); 5286 E1000_WRITE_REG(hw, RDBAH, upper_32_bits(virt_to_phys(rx_base))); 5287 5288 E1000_WRITE_REG(hw, RDLEN, 128); 5289 5290 /* Setup the HW Rx Head and Tail Descriptor Pointers */ 5291 E1000_WRITE_REG(hw, RDH, 0); 5292 E1000_WRITE_REG(hw, RDT, 0); 5293 /* Enable Receives */ 5294 5295 if (hw->mac_type == e1000_igb) { 5296 5297 uint32_t reg_rxdctl = E1000_READ_REG(hw, RXDCTL); 5298 reg_rxdctl |= 1 << 25; 5299 E1000_WRITE_REG(hw, RXDCTL, reg_rxdctl); 5300 mdelay(20); 5301 } 5302 5303 E1000_WRITE_REG(hw, RCTL, rctl); 5304 5305 fill_rx(hw); 5306} 5307 5308/************************************************************************** 5309POLL - Wait for a frame 5310***************************************************************************/ 5311static int 5312_e1000_poll(struct e1000_hw *hw) 5313{ 5314 struct e1000_rx_desc *rd; 5315 unsigned long inval_start, inval_end; 5316 uint32_t len; 5317 5318 /* return true if there's an ethernet packet ready to read */ 5319 rd = rx_base + rx_last; 5320 5321 /* Re-load the descriptor from RAM. */ 5322 inval_start = ((unsigned long)rd) & ~(ARCH_DMA_MINALIGN - 1); 5323 inval_end = inval_start + roundup(sizeof(*rd), ARCH_DMA_MINALIGN); 5324 invalidate_dcache_range(inval_start, inval_end); 5325 5326 if (!(rd->status & E1000_RXD_STAT_DD)) 5327 return 0; 5328 /* DEBUGOUT("recv: packet len=%d\n", rd->length); */ 5329 /* Packet received, make sure the data are re-loaded from RAM. */ 5330 len = le16_to_cpu(rd->length); 5331 invalidate_dcache_range((unsigned long)packet, 5332 (unsigned long)packet + 5333 roundup(len, ARCH_DMA_MINALIGN)); 5334 return len; 5335} 5336 5337static int _e1000_transmit(struct e1000_hw *hw, void *txpacket, int length) 5338{ 5339 void *nv_packet = (void *)txpacket; 5340 struct e1000_tx_desc *txp; 5341 int i = 0; 5342 unsigned long flush_start, flush_end; 5343 5344 txp = tx_base + tx_tail; 5345 tx_tail = (tx_tail + 1) % 8; 5346 5347 txp->buffer_addr = cpu_to_le64(virt_to_phys(nv_packet)); 5348 txp->lower.data = cpu_to_le32(hw->txd_cmd | length); 5349 txp->upper.data = 0; 5350 5351 /* Dump the packet into RAM so e1000 can pick them. */ 5352 flush_dcache_range((unsigned long)nv_packet, 5353 (unsigned long)nv_packet + 5354 roundup(length, ARCH_DMA_MINALIGN)); 5355 /* Dump the descriptor into RAM as well. */ 5356 flush_start = ((unsigned long)txp) & ~(ARCH_DMA_MINALIGN - 1); 5357 flush_end = flush_start + roundup(sizeof(*txp), ARCH_DMA_MINALIGN); 5358 flush_dcache_range(flush_start, flush_end); 5359 5360 E1000_WRITE_REG(hw, TDT, tx_tail); 5361 5362 E1000_WRITE_FLUSH(hw); 5363 while (1) { 5364 invalidate_dcache_range(flush_start, flush_end); 5365 if (le32_to_cpu(txp->upper.data) & E1000_TXD_STAT_DD) 5366 break; 5367 if (i++ > TOUT_LOOP) { 5368 DEBUGOUT("e1000: tx timeout\n"); 5369 return 0; 5370 } 5371 udelay(10); /* give the nic a chance to write to the register */ 5372 } 5373 return 1; 5374} 5375 5376static void 5377_e1000_disable(struct e1000_hw *hw) 5378{ 5379 /* Turn off the ethernet interface */ 5380 E1000_WRITE_REG(hw, RCTL, 0); 5381 E1000_WRITE_REG(hw, TCTL, 0); 5382 5383 /* Clear the transmit ring */ 5384 E1000_WRITE_REG(hw, TDH, 0); 5385 E1000_WRITE_REG(hw, TDT, 0); 5386 5387 /* Clear the receive ring */ 5388 E1000_WRITE_REG(hw, RDH, 0); 5389 E1000_WRITE_REG(hw, RDT, 0); 5390 5391 mdelay(10); 5392} 5393 5394/*reset function*/ 5395static inline int 5396e1000_reset(struct e1000_hw *hw, unsigned char enetaddr[6]) 5397{ 5398 e1000_reset_hw(hw); 5399 if (hw->mac_type >= e1000_82544) 5400 E1000_WRITE_REG(hw, WUC, 0); 5401 5402 return e1000_init_hw(hw, enetaddr); 5403} 5404 5405static int 5406_e1000_init(struct e1000_hw *hw, unsigned char enetaddr[6]) 5407{ 5408 int ret_val = 0; 5409 5410 ret_val = e1000_reset(hw, enetaddr); 5411 if (ret_val < 0) { 5412 if ((ret_val == -E1000_ERR_NOLINK) || 5413 (ret_val == -E1000_ERR_TIMEOUT)) { 5414 E1000_ERR(hw, "Valid Link not detected: %d\n", ret_val); 5415 } else { 5416 E1000_ERR(hw, "Hardware Initialization Failed\n"); 5417 } 5418 return ret_val; 5419 } 5420 e1000_configure_tx(hw); 5421 e1000_setup_rctl(hw); 5422 e1000_configure_rx(hw); 5423 return 0; 5424} 5425 5426/****************************************************************************** 5427 * Gets the current PCI bus type of hardware 5428 * 5429 * hw - Struct containing variables accessed by shared code 5430 *****************************************************************************/ 5431void e1000_get_bus_type(struct e1000_hw *hw) 5432{ 5433 uint32_t status; 5434 5435 switch (hw->mac_type) { 5436 case e1000_82542_rev2_0: 5437 case e1000_82542_rev2_1: 5438 hw->bus_type = e1000_bus_type_pci; 5439 break; 5440 case e1000_82571: 5441 case e1000_82572: 5442 case e1000_82573: 5443 case e1000_82574: 5444 case e1000_80003es2lan: 5445 case e1000_ich8lan: 5446 case e1000_igb: 5447 hw->bus_type = e1000_bus_type_pci_express; 5448 break; 5449 default: 5450 status = E1000_READ_REG(hw, STATUS); 5451 hw->bus_type = (status & E1000_STATUS_PCIX_MODE) ? 5452 e1000_bus_type_pcix : e1000_bus_type_pci; 5453 break; 5454 } 5455} 5456 5457static int e1000_init_one(struct e1000_hw *hw, int cardnum, 5458 struct udevice *devno, unsigned char enetaddr[6]) 5459{ 5460 u32 val; 5461 5462 /* Assign the passed-in values */ 5463 hw->pdev = devno; 5464 hw->cardnum = cardnum; 5465 5466 /* Print a debug message with the IO base address */ 5467 dm_pci_read_config32(devno, PCI_BASE_ADDRESS_0, &val); 5468 E1000_DBG(hw, "iobase 0x%08x\n", val & 0xfffffff0); 5469 5470 /* Try to enable I/O accesses and bus-mastering */ 5471 val = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER; 5472 dm_pci_write_config32(devno, PCI_COMMAND, val); 5473 5474 /* Make sure it worked */ 5475 dm_pci_read_config32(devno, PCI_COMMAND, &val); 5476 if (!(val & PCI_COMMAND_MEMORY)) { 5477 E1000_ERR(hw, "Can't enable I/O memory\n"); 5478 return -ENOSPC; 5479 } 5480 if (!(val & PCI_COMMAND_MASTER)) { 5481 E1000_ERR(hw, "Can't enable bus-mastering\n"); 5482 return -EPERM; 5483 } 5484 5485 /* Are these variables needed? */ 5486 hw->fc = e1000_fc_default; 5487 hw->original_fc = e1000_fc_default; 5488 hw->autoneg_failed = 0; 5489 hw->autoneg = 1; 5490 hw->get_link_status = true; 5491#ifndef CONFIG_E1000_NO_NVM 5492 hw->eeprom_semaphore_present = true; 5493#endif 5494 hw->hw_addr = dm_pci_map_bar(devno, PCI_BASE_ADDRESS_0, 0, 0, 5495 PCI_REGION_TYPE, PCI_REGION_MEM); 5496 hw->mac_type = e1000_undefined; 5497 5498 /* MAC and Phy settings */ 5499 if (e1000_sw_init(hw) < 0) { 5500 E1000_ERR(hw, "Software init failed\n"); 5501 return -EIO; 5502 } 5503 if (e1000_check_phy_reset_block(hw)) 5504 E1000_ERR(hw, "PHY Reset is blocked!\n"); 5505 5506 /* Basic init was OK, reset the hardware and allow SPI access */ 5507 e1000_reset_hw(hw); 5508 5509#ifndef CONFIG_E1000_NO_NVM 5510 /* Validate the EEPROM and get chipset information */ 5511 if (e1000_init_eeprom_params(hw)) { 5512 E1000_ERR(hw, "EEPROM is invalid!\n"); 5513 return -EINVAL; 5514 } 5515 if ((E1000_READ_REG(hw, I210_EECD) & E1000_EECD_FLUPD) && 5516 e1000_validate_eeprom_checksum(hw)) 5517 return -ENXIO; 5518 e1000_read_mac_addr(hw, enetaddr); 5519#endif 5520 e1000_get_bus_type(hw); 5521 5522#ifndef CONFIG_E1000_NO_NVM 5523 printf("e1000: %02x:%02x:%02x:%02x:%02x:%02x\n ", 5524 enetaddr[0], enetaddr[1], enetaddr[2], 5525 enetaddr[3], enetaddr[4], enetaddr[5]); 5526#else 5527 memset(enetaddr, 0, 6); 5528 printf("e1000: no NVM\n"); 5529#endif 5530 5531 return 0; 5532} 5533 5534/* Put the name of a device in a string */ 5535static void e1000_name(char *str, int cardnum) 5536{ 5537 sprintf(str, "e1000#%u", cardnum); 5538} 5539 5540static int e1000_write_hwaddr(struct udevice *dev) 5541{ 5542#ifndef CONFIG_E1000_NO_NVM 5543 unsigned char current_mac[6]; 5544 struct eth_pdata *plat = dev_get_plat(dev); 5545 struct e1000_hw *hw = dev_get_priv(dev); 5546 u8 *mac = plat->enetaddr; 5547 uint16_t data[3]; 5548 int ret_val, i; 5549 5550 DEBUGOUT("%s: mac=%pM\n", __func__, mac); 5551 5552 if ((hw->eeprom.type == e1000_eeprom_invm) && 5553 !(E1000_READ_REG(hw, EECD) & E1000_EECD_FLASH_DETECTED_I210)) 5554 return -ENOSYS; 5555 5556 memset(current_mac, 0, 6); 5557 5558 /* Read from EEPROM, not from registers, to make sure 5559 * the address is persistently configured 5560 */ 5561 ret_val = e1000_read_mac_addr_from_eeprom(hw, current_mac); 5562 DEBUGOUT("%s: current mac=%pM\n", __func__, current_mac); 5563 5564 /* Only write to EEPROM if the given address is different or 5565 * reading the current address failed 5566 */ 5567 if (!ret_val && memcmp(current_mac, mac, 6) == 0) 5568 return 0; 5569 5570 for (i = 0; i < 3; ++i) 5571 data[i] = mac[i * 2 + 1] << 8 | mac[i * 2]; 5572 5573 ret_val = e1000_write_eeprom_srwr(hw, 0x0, 3, data); 5574 5575 if (!ret_val) 5576 ret_val = e1000_update_eeprom_checksum_i210(hw); 5577 5578 return ret_val; 5579#else 5580 return 0; 5581#endif 5582} 5583 5584#ifdef CONFIG_CMD_E1000 5585static int do_e1000(struct cmd_tbl *cmdtp, int flag, int argc, 5586 char *const argv[]) 5587{ 5588 unsigned char *mac = NULL; 5589 struct eth_pdata *plat; 5590 struct udevice *dev; 5591 char name[30]; 5592 int ret; 5593#if defined(CONFIG_E1000_SPI) 5594 struct e1000_hw *hw; 5595#endif 5596 int cardnum; 5597 5598 if (argc < 3) { 5599 cmd_usage(cmdtp); 5600 return 1; 5601 } 5602 5603 /* Make sure we can find the requested e1000 card */ 5604 cardnum = dectoul(argv[1], NULL); 5605 e1000_name(name, cardnum); 5606 ret = uclass_get_device_by_name(UCLASS_ETH, name, &dev); 5607 if (!ret) { 5608 plat = dev_get_plat(dev); 5609 mac = plat->enetaddr; 5610 } 5611 if (!mac) { 5612 printf("e1000: ERROR: No such device: e1000#%s\n", argv[1]); 5613 return 1; 5614 } 5615 5616 if (!strcmp(argv[2], "print-mac-address")) { 5617 printf("%02x:%02x:%02x:%02x:%02x:%02x\n", 5618 mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]); 5619 return 0; 5620 } 5621 5622#ifdef CONFIG_E1000_SPI 5623 hw = dev_get_priv(dev); 5624 /* Handle the "SPI" subcommand */ 5625 if (!strcmp(argv[2], "spi")) 5626 return do_e1000_spi(cmdtp, hw, argc - 3, argv + 3); 5627#endif 5628 5629 cmd_usage(cmdtp); 5630 return 1; 5631} 5632 5633U_BOOT_CMD( 5634 e1000, 7, 0, do_e1000, 5635 "Intel e1000 controller management", 5636 /* */"<card#> print-mac-address\n" 5637#ifdef CONFIG_E1000_SPI 5638 "e1000 <card#> spi show [<offset> [<length>]]\n" 5639 "e1000 <card#> spi dump <addr> <offset> <length>\n" 5640 "e1000 <card#> spi program <addr> <offset> <length>\n" 5641 "e1000 <card#> spi checksum [update]\n" 5642#endif 5643 " - Manage the Intel E1000 PCI device" 5644); 5645#endif /* not CONFIG_CMD_E1000 */ 5646 5647static int e1000_eth_start(struct udevice *dev) 5648{ 5649 struct eth_pdata *plat = dev_get_plat(dev); 5650 struct e1000_hw *hw = dev_get_priv(dev); 5651 5652 return _e1000_init(hw, plat->enetaddr); 5653} 5654 5655static void e1000_eth_stop(struct udevice *dev) 5656{ 5657 struct e1000_hw *hw = dev_get_priv(dev); 5658 5659 _e1000_disable(hw); 5660} 5661 5662static int e1000_eth_send(struct udevice *dev, void *packet, int length) 5663{ 5664 struct e1000_hw *hw = dev_get_priv(dev); 5665 int ret; 5666 5667 ret = _e1000_transmit(hw, packet, length); 5668 5669 return ret ? 0 : -ETIMEDOUT; 5670} 5671 5672static int e1000_eth_recv(struct udevice *dev, int flags, uchar **packetp) 5673{ 5674 struct e1000_hw *hw = dev_get_priv(dev); 5675 int len; 5676 5677 len = _e1000_poll(hw); 5678 if (len) 5679 *packetp = packet; 5680 5681 return len ? len : -EAGAIN; 5682} 5683 5684static int e1000_free_pkt(struct udevice *dev, uchar *packet, int length) 5685{ 5686 struct e1000_hw *hw = dev_get_priv(dev); 5687 5688 fill_rx(hw); 5689 5690 return 0; 5691} 5692 5693static int e1000_eth_probe(struct udevice *dev) 5694{ 5695 struct eth_pdata *plat = dev_get_plat(dev); 5696 struct e1000_hw *hw = dev_get_priv(dev); 5697 int ret; 5698 5699 hw->name = dev->name; 5700 ret = e1000_init_one(hw, trailing_strtol(dev->name), 5701 dev, plat->enetaddr); 5702 if (ret < 0) { 5703 printf(pr_fmt("failed to initialize card: %d\n"), ret); 5704 return ret; 5705 } 5706 5707 return 0; 5708} 5709 5710static int e1000_eth_bind(struct udevice *dev) 5711{ 5712 char name[20]; 5713 5714 /* 5715 * A simple way to number the devices. When device tree is used this 5716 * is unnecessary, but when the device is just discovered on the PCI 5717 * bus we need a name. We could instead have the uclass figure out 5718 * which devices are different and number them. 5719 */ 5720 e1000_name(name, num_cards++); 5721 5722 return device_set_name(dev, name); 5723} 5724 5725static const struct eth_ops e1000_eth_ops = { 5726 .start = e1000_eth_start, 5727 .send = e1000_eth_send, 5728 .recv = e1000_eth_recv, 5729 .stop = e1000_eth_stop, 5730 .free_pkt = e1000_free_pkt, 5731 .write_hwaddr = e1000_write_hwaddr, 5732}; 5733 5734U_BOOT_DRIVER(eth_e1000) = { 5735 .name = "eth_e1000", 5736 .id = UCLASS_ETH, 5737 .bind = e1000_eth_bind, 5738 .probe = e1000_eth_probe, 5739 .ops = &e1000_eth_ops, 5740 .priv_auto = sizeof(struct e1000_hw), 5741 .plat_auto = sizeof(struct eth_pdata), 5742}; 5743 5744U_BOOT_PCI_DEVICE(eth_e1000, e1000_supported); 5745