Searched refs:parent (Results 1 - 25 of 531) sorted by relevance

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/u-boot/lib/
H A Drbtree.c49 * - old's parent and color get assigned to new
50 * - old gets assigned new as a parent and 'color' as a color.
56 struct rb_node *parent = rb_parent(old); local
59 __rb_change_child(old, new, parent, root);
66 struct rb_node *parent = rb_red_parent(node), *gparent, *tmp; local
72 * If there is a black parent, we are done.
76 if (!parent) {
79 } else if (rb_is_black(parent))
82 gparent = rb_red_parent(parent);
85 if (parent !
192 ____rb_erase_color(struct rb_node *parent, struct rb_root *root, void (*augment_rotate)(struct rb_node *old, struct rb_node *new)) argument
354 __rb_erase_color(struct rb_node *parent, struct rb_root *root, void (*augment_rotate)(struct rb_node *old, struct rb_node *new)) argument
436 struct rb_node *parent; local
468 struct rb_node *parent; local
498 struct rb_node *parent = rb_parent(victim); local
526 const struct rb_node *parent; local
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/u-boot/drivers/clk/renesas/
H A Drcar-cpg-lib.h16 s64 rcar_clk_get_rate64_div_table(unsigned int parent, u64 parent_rate,
20 int rcar_clk_set_rate64_div_table(unsigned int parent, u64 parent_rate, ulong rate,
24 s64 rcar_clk_get_rate64_sdh(unsigned int parent, u64 parent_rate, void __iomem *reg);
25 s64 rcar_clk_get_rate64_sd(unsigned int parent, u64 parent_rate, void __iomem *reg);
26 s64 rcar_clk_get_rate64_rpc(unsigned int parent, u64 parent_rate, void __iomem *reg);
27 u64 rcar_clk_get_rate64_rpcd2(unsigned int parent, u64 parent_rate);
28 int rcar_clk_set_rate64_sdh(unsigned int parent, u64 parent_rate, ulong rate,
30 int rcar_clk_set_rate64_sd(unsigned int parent, u64 parent_rate, ulong rate,
H A Dclk-rcar-gen3.c60 struct cpg_mssr_info *info, struct clk *parent)
73 parent->dev = clk->dev;
74 parent->id = core->parent >> shift;
75 parent->id &= 0xffff;
80 return renesas_clk_get_parent(clk, info, parent);
104 struct clk parent, grandparent; local
110 * Note that parent clock here always represents core clock. Also note
111 * that grandparent clock are the parent clock of the core clock here.
114 ret = gen3_clk_get_parent(priv, clk, info, &parent);
59 gen3_clk_get_parent(struct gen3_clk_priv *priv, struct clk *clk, struct cpg_mssr_info *info, struct clk *parent) argument
162 gen3_clk_get_rate64_pll_mul_reg(struct gen3_clk_priv *priv, struct clk *parent, u32 mul_reg, u32 mult, u32 div, char *name) argument
187 struct clk parent; local
577 gen3_cpg_bind(struct udevice *parent) argument
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H A Drcar-cpg-lib.c72 s64 rcar_clk_get_rate64_div_table(unsigned int parent, u64 parent_rate, argument
85 debug("%s[%i] %s clk: parent=%i div=%u => rate=%llu\n",
86 __func__, __LINE__, name, parent, div, rate);
91 int rcar_clk_set_rate64_div_table(unsigned int parent, u64 parent_rate, ulong rate, argument
104 debug("%s[%i] %s clk: parent=%i div=%u rate=%lu => val=%u\n",
105 __func__, __LINE__, name, parent, div, rate, value);
110 s64 rcar_clk_get_rate64_rpc(unsigned int parent, u64 parent_rate, void __iomem *reg) argument
112 return rcar_clk_get_rate64_div_table(parent, parent_rate, reg,
117 u64 rcar_clk_get_rate64_rpcd2(unsigned int parent, u64 parent_rate) argument
122 debug("%s[%i] RPCD2 clk: parent
128 rcar_clk_get_rate64_sdh(unsigned int parent, u64 parent_rate, void __iomem *reg) argument
141 rcar_clk_get_rate64_sd(unsigned int parent, u64 parent_rate, void __iomem *reg) argument
148 rcar_clk_set_rate64_sdh(unsigned int parent, u64 parent_rate, ulong rate, void __iomem *reg) argument
162 rcar_clk_set_rate64_sd(unsigned int parent, u64 parent_rate, ulong rate, void __iomem *reg) argument
[all...]
H A Dclk-rcar-gen2.c73 struct clk parent; local
82 ret = renesas_clk_get_parent(clk, info, &parent);
84 printf("%s[%i] parent fail, ret=%i\n", __func__, __LINE__, ret);
89 rate = gen2_clk_get_rate(&parent);
90 debug("%s[%i] MOD clk: parent=%lu => rate=%u\n",
91 __func__, __LINE__, parent.id, rate);
118 rate = (gen2_clk_get_rate(&parent) * core->mult) / core->div;
119 debug("%s[%i] FIXED clk: parent=%i mul=%i div=%i => rate=%u\n",
121 core->parent, core->mult, core->div, rate);
124 case CLK_TYPE_DIV6P1: /* DIV6 Clock with 1 parent cloc
209 struct clk parent, pparent; local
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/u-boot/fs/btrfs/common/
H A Drbtree-utils.c26 struct rb_node *parent = NULL; local
30 parent = *p;
32 ret = comp(parent, node);
41 rb_link_node(node, parent, p);
50 struct rb_node *parent = NULL; local
54 parent = n;
68 if (parent && ret > 0)
69 parent = rb_next(parent);
71 *next_ret = parent;
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/u-boot/include/dm/
H A Dlists.h37 * lists_bind_drivers() - search for and bind all drivers to parent
40 * each one. The devices will have @parent as their parent.
42 * @parent: parent device (root)
46 int lists_bind_drivers(struct udevice *parent, bool pre_reloc_only);
52 * @parent as its parent.
54 * @parent: parent devic
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H A Ddevice.h136 * @parent_plat_: The parent bus's configuration data for this device (do not
142 * @parent: Parent of this device, or NULL for the top level device
147 * @parent_priv_: The parent's private data for this device (do not access
177 struct udevice *parent; member in struct:udevice
362 * its parent. If required this will be automatically allocated if this
501 * dev_get_parent_plat() - Get the parent platform data for a device
506 * Return: parent's platform data, or NULL if none
531 * dev_get_parent_priv() - Get the parent private data for a device
533 * The parent private data is data stored in the device but owned by the
534 * parent
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/u-boot/test/dm/
H A Dphy.c23 struct udevice *parent; local
27 "gen_phy_user", &parent));
31 ut_assertok(generic_phy_get_by_name(parent, "phy1", &phy1_method1));
33 ut_assertok(generic_phy_get_by_index(parent, 0, &phy1_method2));
41 ut_assertok(generic_phy_get_by_name(parent, "phy2", &phy2));
48 ut_assertok(generic_phy_get_by_name(parent, "phy3", &phy3));
53 ut_asserteq(-ENODATA, generic_phy_get_by_name(parent,
56 ut_asserteq(-ENOENT, generic_phy_get_by_index(parent, 3,
62 "gen_phy_user2", &parent));
63 ut_asserteq(-EINVAL, generic_phy_get_by_name(parent, "phy
80 struct udevice *parent; local
149 struct udevice *parent; local
184 struct udevice *parent; local
241 struct udevice *parent; local
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/u-boot/drivers/clk/microchip/
H A Dmpfs_clk.h14 * @parent: a pointer to parent clock.
17 int mpfs_clk_register_cfgs(void __iomem *base, struct clk *parent);
22 * @parent: a pointer to parent clock.
25 int mpfs_clk_register_msspll(void __iomem *base, struct clk *parent);
38 * @parent_rate: parent clock rate.
/u-boot/drivers/sysreset/
H A Dsysreset_tps65910.c18 val = pmic_reg_read(dev->parent, TPS65910_REG_DEVICE_CTRL);
24 pmic_reg_write(dev->parent, TPS65910_REG_DEVICE_CTRL, val);
31 pmic_reg_write(dev->parent, TPS65910_REG_DEVICE_CTRL,
36 pmic_reg_write(dev->parent, TPS65910_REG_DEVICE_CTRL,
H A Dsysreset_max77663.c18 val = pmic_reg_read(dev->parent, MAX77663_REG_ONOFF_CFG1);
29 pmic_reg_write(dev->parent, MAX77663_REG_ONOFF_CFG1,
34 pmic_reg_write(dev->parent, MAX77663_REG_ONOFF_CFG1,
H A Dsysreset_palmas.c16 struct palmas_priv *priv = dev_get_priv(dev->parent);
31 pmic_reg_write(dev->parent, PALMAS_DEV_CTRL, SW_RST);
35 pmic_reg_write(dev->parent, PALMAS_DEV_CTRL, DEV_OFF);
H A Dsysreset_tps80031.c19 pmic_reg_write(dev->parent, TPS80031_PHOENIX_DEV_ON, SW_RESET);
23 pmic_reg_write(dev->parent, TPS80031_PHOENIX_DEV_ON, DEVOFF);
/u-boot/drivers/clk/ti/
H A Dclk-mux.c41 struct clk *parent)
45 if (!parents || !parent)
49 if (parents->clks[i].dev == parent->dev)
77 static int clk_ti_mux_set_parent(struct clk *clk, struct clk *parent) argument
83 index = clk_ti_mux_get_parent_index(&priv->parents, parent);
85 dev_err(clk->dev, "failed to get parent clock\n");
107 struct clk *parent; local
114 parent = clk_ti_mux_get_parent_by_index(&priv->parents, index);
115 if (IS_ERR(parent))
116 return PTR_ERR(parent);
40 clk_ti_mux_get_parent_index(struct clk_bulk *parents, struct clk *parent) argument
127 struct clk *parent; local
143 struct clk *parent; local
162 struct clk *parent; local
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/u-boot/include/
H A Dsandbox-clk.h36 const char *parent,
40 return clk_register_fixed_factor(NULL, name, parent,
45 const char *parent,
49 return clk_register_divider(NULL, name, parent, CLK_SET_RATE_PARENT,
53 static inline struct clk *sandbox_clk_gate(const char *name, const char *parent, argument
57 return clk_register_gate(NULL, name, parent, CLK_SET_RATE_PARENT,
68 const char *parent,
71 return sandbox_clk_register_gate2(NULL, name, parent,
35 sandbox_clk_fixed_factor(const char *name, const char *parent, unsigned int mult, unsigned int div) argument
44 sandbox_clk_divider(const char *name, const char *parent, void __iomem *reg, u8 shift, u8 width) argument
67 sandbox_clk_gate2(const char *name, const char *parent, void __iomem *reg, u8 shift) argument
/u-boot/drivers/usb/dwc3/
H A Ddwc3-generic.h24 int (*glue_get_ctrl_dev)(struct udevice *parent, ofnode *node);
29 int dwc3_glue_bind(struct udevice *parent);
/u-boot/drivers/core/
H A Ddevice.c40 static int device_bind_common(struct udevice *parent, const struct driver *drv, argument
79 dev->parent = parent;
146 if (parent) {
147 size = parent->driver->per_child_plat_auto;
149 size = parent->uclass->uc_drv->per_child_plat_auto;
159 /* put dev into parent's successor list */
160 list_add_tail(&dev->sibling_node, &parent->child_head);
173 if (parent && parent
240 device_bind_with_driver_data(struct udevice *parent, const struct driver *drv, const char *name, ulong driver_data, ofnode node, struct udevice **devp) argument
249 device_bind(struct udevice *parent, const struct driver *drv, const char *name, void *plat, ofnode node, struct udevice **devp) argument
257 device_bind_by_name(struct udevice *parent, bool pre_reloc_only, const struct driver_info *info, struct udevice **devp) argument
456 struct udevice *parent = dev->parent; local
702 const struct udevice *parent = dev_get_parent(dev); local
789 device_get_child(const struct udevice *parent, int index, struct udevice **devp) argument
802 device_get_child_count(const struct udevice *parent) argument
813 device_get_decendent_count(const struct udevice *parent) argument
824 device_find_child_by_seq(const struct udevice *parent, int seq, struct udevice **devp) argument
841 device_get_child_by_seq(const struct udevice *parent, int seq, struct udevice **devp) argument
853 device_find_child_by_of_offset(const struct udevice *parent, int of_offset, struct udevice **devp) argument
870 device_get_child_by_of_offset(const struct udevice *parent, int node, struct udevice **devp) argument
881 _device_find_global_by_ofnode(struct udevice *parent, ofnode ofnode) argument
933 device_find_first_child(const struct udevice *parent, struct udevice **devp) argument
948 struct udevice *parent = dev->parent; local
960 device_find_first_inactive_child(const struct udevice *parent, enum uclass_id uclass_id, struct udevice **devp) argument
978 device_find_first_child_by_uclass(const struct udevice *parent, enum uclass_id uclass_id, struct udevice **devp) argument
995 device_find_child_by_namelen(const struct udevice *parent, const char *name, int len, struct udevice **devp) argument
1013 device_find_child_by_name(const struct udevice *parent, const char *name, struct udevice **devp) argument
1019 device_first_child_err(struct udevice *parent, struct udevice **devp) argument
1041 device_first_child_ofdata_err(struct udevice *parent, struct udevice **devp) argument
1129 struct udevice *parent = dev->parent; local
1227 struct udevice *parent; local
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H A Dof_addr.c43 int (*match)(struct device_node *parent);
127 struct device_node *parent; local
131 /* Get parent & match bus type */
132 parent = of_get_parent(dev);
133 if (parent == NULL)
135 bus = of_match_bus(parent);
137 of_node_put(parent);
165 static int of_translate_one(const struct device_node *parent, argument
192 * child nodes without 'dma-ranges' in the parent nodes. --RobH
194 ranges = of_get_property(parent, rpro
244 struct device_node *parent = NULL; local
331 struct device_node *parent; local
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/u-boot/include/linux/
H A Drbtree_augmented.h99 struct rb_node *parent, struct rb_root *root)
101 if (parent) {
102 if (parent->rb_left == old)
103 parent->rb_left = new;
105 parent->rb_right = new;
110 extern void __rb_erase_color(struct rb_node *parent, struct rb_root *root,
118 struct rb_node *parent, *rebalance; local
130 parent = __rb_parent(pc);
131 __rb_change_child(node, child, parent, root);
136 rebalance = __rb_is_black(pc) ? parent
98 __rb_change_child(struct rb_node *old, struct rb_node *new, struct rb_node *parent, struct rb_root *root) argument
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/u-boot/drivers/virtio/
H A Dvirtio-uclass.c41 ops = virtio_get_ops(vdev->parent);
43 return ops->get_config(vdev->parent, offset, buf, len);
51 ops = virtio_get_ops(vdev->parent);
53 return ops->set_config(vdev->parent, offset, buf, len);
60 ops = virtio_get_ops(vdev->parent);
64 return ops->generation(vdev->parent, counter);
71 ops = virtio_get_ops(vdev->parent);
73 return ops->get_status(vdev->parent, status);
80 ops = virtio_get_ops(vdev->parent);
82 return ops->set_status(vdev->parent, statu
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/u-boot/drivers/clk/imx/
H A Dclk.h90 static inline struct clk *imx_clk_gate2(const char *name, const char *parent, argument
93 return clk_register_gate2(NULL, name, parent, CLK_SET_RATE_PARENT, reg,
98 const char *parent,
102 return clk_register_gate2(NULL, name, parent, CLK_SET_RATE_PARENT, reg,
107 const char *parent,
111 return clk_register_gate2(NULL, name, parent, CLK_SET_RATE_PARENT |
116 static inline struct clk *imx_clk_gate4(const char *name, const char *parent, argument
119 return clk_register_gate2(NULL, name, parent,
125 const char *parent, void __iomem *reg, u8 shift,
128 return clk_register_gate2(NULL, name, parent,
97 imx_clk_gate2_shared(const char *name, const char *parent, void __iomem *reg, u8 shift, unsigned int *share_count) argument
106 imx_clk_gate2_shared2(const char *name, const char *parent, void __iomem *reg, u8 shift, unsigned int *share_count) argument
124 imx_clk_gate4_flags(const char *name, const char *parent, void __iomem *reg, u8 shift, unsigned long flags) argument
133 imx_clk_fixed_factor(const char *name, const char *parent, unsigned int mult, unsigned int div) argument
140 imx_clk_divider(const char *name, const char *parent, void __iomem *reg, u8 shift, u8 width) argument
148 imx_clk_busy_divider(const char *name, const char *parent, void __iomem *reg, u8 shift, u8 width, void __iomem *busy_reg, u8 busy_shift) argument
155 imx_clk_divider2(const char *name, const char *parent, void __iomem *reg, u8 shift, u8 width) argument
218 imx_clk_gate(const char *name, const char *parent, void __iomem *reg, u8 shift) argument
225 imx_clk_gate_flags(const char *name, const char *parent, void __iomem *reg, u8 shift, unsigned long flags) argument
232 imx_clk_gate3(const char *name, const char *parent, void __iomem *reg, u8 shift) argument
[all...]
/u-boot/drivers/clk/tegra/
H A Dtegra-car-clk.c35 enum clock_id parent; local
40 parent = clock_get_periph_parent(clk->id);
41 return clock_get_periph_rate(clk->id, parent);
46 enum clock_id parent; local
51 parent = clock_get_periph_parent(clk->id);
52 return clock_adjust_periph_pll_div(clk->id, parent, rate, NULL);
/u-boot/drivers/clk/mediatek/
H A Dclk-mtk.h60 * @parent: index of parnet clocks
65 const int parent; member in struct:mtk_fixed_clk
71 .parent = _parent, \
79 * @parent: index of parnet clocks
86 const int parent; member in struct:mtk_fixed_factor
94 .parent = _parent, \
104 * @parent: index of parnet clocks
110 * @num_parents: number of parent clocks
115 const int *parent; member in struct:mtk_composite
137 .parent
191 const int parent; member in struct:mtk_gate
211 struct udevice *parent; member in struct:mtk_clk_priv
217 struct udevice *parent; member in struct:mtk_cg_priv
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/u-boot/drivers/iommu/
H A Diommu-uclass.c20 struct udevice *parent = dev->parent; local
26 while (parent) {
27 len = dev_read_size(parent, "iommu-map");
30 parent = parent->parent;
41 ret = dev_read_u32_array(parent, "iommu-map", iommu_map, count);
47 iommu_map_mask = dev_read_u32_default(parent, "iommu-map-mask", ~0);
103 if (dev->parent
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