1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (c) 2016, NVIDIA CORPORATION.
4 */
5
6#include <common.h>
7#include <clk-uclass.h>
8#include <dm.h>
9#include <log.h>
10#include <malloc.h>
11#include <asm/arch/clock.h>
12#include <asm/arch-tegra/clk_rst.h>
13
14static int tegra_car_clk_request(struct clk *clk)
15{
16	debug("%s(clk=%p) (dev=%p, id=%lu)\n", __func__, clk, clk->dev,
17	      clk->id);
18
19	/*
20	 * Note that the first PERIPH_ID_COUNT clock IDs (where the value
21	 * varies per SoC) are the peripheral clocks, which use a numbering
22	 * scheme that matches HW registers 1:1. There are other clock IDs
23	 * beyond this that are assigned arbitrarily by the Tegra CAR DT
24	 * binding. Due to the implementation of this driver, it currently
25	 * only supports the peripheral IDs.
26	 */
27	if (clk->id >= PERIPH_ID_COUNT)
28		return -EINVAL;
29
30	return 0;
31}
32
33static ulong tegra_car_clk_get_rate(struct clk *clk)
34{
35	enum clock_id parent;
36
37	debug("%s(clk=%p) (dev=%p, id=%lu)\n", __func__, clk, clk->dev,
38	      clk->id);
39
40	parent = clock_get_periph_parent(clk->id);
41	return clock_get_periph_rate(clk->id, parent);
42}
43
44static ulong tegra_car_clk_set_rate(struct clk *clk, ulong rate)
45{
46	enum clock_id parent;
47
48	debug("%s(clk=%p, rate=%lu) (dev=%p, id=%lu)\n", __func__, clk, rate,
49	      clk->dev, clk->id);
50
51	parent = clock_get_periph_parent(clk->id);
52	return clock_adjust_periph_pll_div(clk->id, parent, rate, NULL);
53}
54
55static int tegra_car_clk_enable(struct clk *clk)
56{
57	debug("%s(clk=%p) (dev=%p, id=%lu)\n", __func__, clk, clk->dev,
58	      clk->id);
59
60	clock_enable(clk->id);
61
62	return 0;
63}
64
65static int tegra_car_clk_disable(struct clk *clk)
66{
67	debug("%s(clk=%p) (dev=%p, id=%lu)\n", __func__, clk, clk->dev,
68	      clk->id);
69
70	clock_disable(clk->id);
71
72	return 0;
73}
74
75static struct clk_ops tegra_car_clk_ops = {
76	.request = tegra_car_clk_request,
77	.get_rate = tegra_car_clk_get_rate,
78	.set_rate = tegra_car_clk_set_rate,
79	.enable = tegra_car_clk_enable,
80	.disable = tegra_car_clk_disable,
81};
82
83static int tegra_car_clk_probe(struct udevice *dev)
84{
85	debug("%s(dev=%p)\n", __func__, dev);
86
87	return 0;
88}
89
90U_BOOT_DRIVER(tegra_car_clk) = {
91	.name = "tegra_car_clk",
92	.id = UCLASS_CLK,
93	.probe = tegra_car_clk_probe,
94	.ops = &tegra_car_clk_ops,
95};
96