Searched refs:mfspr (Results 1 - 18 of 18) sorted by relevance
| /u-boot/arch/powerpc/cpu/mpc8xx/ |
| H A D | cache.c | 15 return !!(mfspr(IC_CST) & IDC_ENABLED);
33 return !!(mfspr(IC_CST) & IDC_ENABLED);
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| H A D | start.S | 77 mfspr r3, ICR /* clear Interrupt Cause Register */
90 mfspr r3, IC_CST /* Clear error bits */
91 mfspr r3, DC_CST
201 mfspr r4,DAR
203 mfspr r5,DSISR
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| /u-boot/arch/powerpc/cpu/mpc85xx/ |
| H A D | spl_minimal.c | 38 u32 s = mfspr(SPRN_TBRL);
40 while ((mfspr(SPRN_TBRL) - s) < ticks);
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| H A D | release.S | 32 mfspr r3, SPRN_HDBCR0
48 mfspr r0,PVR
59 mfspr r3,SPRN_HDBCR1
65 mfspr r3,SPRN_SVR
83 mfspr r3,SPRN_HDBCR0
106 mfspr r3,SPRN_L1CSR1
115 mfspr r3,SPRN_L1CSR1
124 mfspr r3,SPRN_L1CSR0
133 mfspr r3,SPRN_L1CSR0
144 mfspr r
[all...] |
| H A D | tlb.c | 56 _mas1 = mfspr(MAS1);
60 *epn = mfspr(MAS2) & MAS2_EPN;
61 *rpn = mfspr(MAS3) & MAS3_RPN;
63 *rpn |= ((u64)mfspr(MAS7)) << 32;
70 unsigned int num_cam = mfspr(SPRN_TLB1CFG) & 0xfff;
106 unsigned int num_cam = mfspr(SPRN_TLB1CFG) & 0xfff;
115 if (mfspr(MAS1) & MAS1_VALID)
149 if ((mfspr(SPRN_MMUCFG) & MMUCFG_MAVN) == MMUCFG_MAVN_V1 &&
211 _mas0 = mfspr(MAS0);
212 _mas1 = mfspr(MAS
[all...] |
| H A D | traps.c | 51 asm volatile("mfspr %0, 0x03e" : "=r" (val) :);
143 mcsrr0 = mfspr(SPRN_MCSRR0);
144 mcsrr1 = mfspr(SPRN_MCSRR1);
145 mcsr = mfspr(SPRN_MCSR);
146 mcar = mfspr(SPRN_MCAR);
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| H A D | start.S | 183 mfspr r3,SPRN_SVR
203 mfspr r3,SPRN_HDBCR0
213 mfspr r3, SPRN_HDBCR0
227 mfspr r3, SPRN_L2CSR0
233 mfspr r3, SPRN_L2CSR0
243 mfspr r3, SPRN_L2CSR0
247 mfspr r3, SPRN_L2CSR0
266 mfspr r1,DBSR
408 mfspr r3,PVR
419 mfspr r
[all...] |
| H A D | interrupts.c | 48 mtspr(SPRN_TCR, mfspr(SPRN_TCR) | TCR_PIE);
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| H A D | cpu_init.c | 614 u32 l2cfg0 = mfspr(SPRN_L2CFG0);
618 while (mfspr(SPRN_L2CSR0) & (L2CSR0_L2FI|L2CSR0_L2LFC))
630 while (!(mfspr(SPRN_L2CSR0) & L2CSR0_L2E))
707 mtspr(L1CSR2, (mfspr(L1CSR2) | L1CSR2_DCWS));
714 mtspr(L1CSR2, (mfspr(L1CSR2) & ~L1CSR2_DCSTASHID));
723 if (mfspr(L1CSR2) & L1CSR2_DCWS)
724 mtspr(SPRN_HDBCR0, (mfspr(SPRN_HDBCR0) | 0x80000000));
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| H A D | fdt.c | 297 u32 l2cfg0 = mfspr(SPRN_L2CFG0);
390 u32 l1cfg0 = mfspr(SPRN_L1CFG0);
391 u32 l1cfg1 = mfspr(SPRN_L1CFG1);
495 svr = mfspr(SPRN_SVR);
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| H A D | cpu.c | 318 val = mfspr(DBCR0);
359 mtspr(SPRN_TCR, (mfspr(SPRN_TCR) & ~WATCHDOG_MASK) |
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| H A D | mp.c | 29 return mfspr(SPRN_PIR);
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| /u-boot/arch/powerpc/include/asm/ |
| H A D | ppc.h | 40 return mfspr(SPRN_IMMR);
45 return mfspr(PVR);
50 return mfspr(SVR);
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| H A D | cache.h | 105 return mfspr(IC_CST);
120 return mfspr(DC_CST);
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| H A D | processor.h | 1114 #define mfspr(rn) ({unsigned int rval; \ macro
1115 asm volatile("mfspr %0," stringify(rn) \
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| /u-boot/drivers/watchdog/ |
| H A D | booke_wdt.c | 67 val = mfspr(SPRN_TCR);
80 val = mfspr(SPRN_TCR);
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| /u-boot/arch/powerpc/cpu/mpc83xx/ |
| H A D | start.S | 314 mfspr r4,DAR
316 mfspr r5,DSISR
725 mfspr r3, HID0
738 mfspr r3, HID0
748 mfspr r3, HID0
755 mfspr r3, HID0
767 mfspr r3, HID0
780 mfspr r3, HID0
1065 mfspr r0, HID0
1089 mfspr r
[all...] |
| /u-boot/board/keymile/km83xx/ |
| H A D | km83xx.c | 150 svid = SVR_REV(mfspr(SVR));
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