1/*
2 * include/asm-ppc/cache.h
3 */
4#ifndef __ARCH_PPC_CACHE_H
5#define __ARCH_PPC_CACHE_H
6
7#include <asm/processor.h>
8
9/* bytes per L1 cache line */
10#if defined(CONFIG_MPC8xx)
11#define	L1_CACHE_SHIFT	4
12#elif defined(CONFIG_PPC64BRIDGE)
13#define L1_CACHE_SHIFT	7
14#elif defined(CONFIG_E500MC)
15#define L1_CACHE_SHIFT	6
16#else
17#define	L1_CACHE_SHIFT	5
18#endif
19
20#define L1_CACHE_BYTES          (1 << L1_CACHE_SHIFT)
21
22/*
23 * Use the L1 data cache line size value for the minimum DMA buffer alignment
24 * on PowerPC.
25 */
26#define ARCH_DMA_MINALIGN	L1_CACHE_BYTES
27
28#define	L1_CACHE_ALIGN(x)       (((x)+(L1_CACHE_BYTES-1))&~(L1_CACHE_BYTES-1))
29#define	L1_CACHE_PAGES		8
30
31#define	SMP_CACHE_BYTES L1_CACHE_BYTES
32
33#ifdef MODULE
34#define __cacheline_aligned __attribute__((__aligned__(L1_CACHE_BYTES)))
35#else
36#define __cacheline_aligned					\
37  __attribute__((__aligned__(L1_CACHE_BYTES)))			\
38  __section(".data.cacheline_aligned")
39#endif
40
41#if defined(__KERNEL__) && !defined(__ASSEMBLY__)
42extern void flush_dcache_range(unsigned long start, unsigned long stop);
43extern void clean_dcache_range(unsigned long start, unsigned long stop);
44extern void invalidate_dcache_range(unsigned long start, unsigned long stop);
45extern void flush_dcache(void);
46extern void invalidate_dcache(void);
47extern void invalidate_icache(void);
48extern void unlock_ram_in_cache(void);
49#endif /* __ASSEMBLY__ */
50
51#if defined(__KERNEL__) && !defined(__ASSEMBLY__)
52int l2cache_init(void);
53void enable_cpc(void);
54void disable_cpc_sram(void);
55#endif
56
57/* prep registers for L2 */
58#define CACHECRBA       0x80000823      /* Cache configuration register address */
59#define L2CACHE_MASK	0x03	/* Mask for 2 L2 Cache bits */
60#define L2CACHE_512KB	0x00	/* 512KB */
61#define L2CACHE_256KB	0x01	/* 256KB */
62#define L2CACHE_1MB	0x02	/* 1MB */
63#define L2CACHE_NONE	0x03	/* NONE */
64#define L2CACHE_PARITY  0x08    /* Mask for L2 Cache Parity Protected bit */
65
66#ifdef CONFIG_MPC8xx
67/* Cache control on the MPC8xx is provided through some additional
68 * special purpose registers.
69 */
70#define IC_CST		560	/* Instruction cache control/status */
71#define IC_ADR		561	/* Address needed for some commands */
72#define IC_DAT		562	/* Read-only data register */
73#define DC_CST		568	/* Data cache control/status */
74#define DC_ADR		569	/* Address needed for some commands */
75#define DC_DAT		570	/* Read-only data register */
76
77/* Commands.  Only the first few are available to the instruction cache.
78*/
79#define	IDC_ENABLE	0x02000000	/* Cache enable */
80#define IDC_DISABLE	0x04000000	/* Cache disable */
81#define IDC_LDLCK	0x06000000	/* Load and lock */
82#define IDC_UNLINE	0x08000000	/* Unlock line */
83#define IDC_UNALL	0x0a000000	/* Unlock all */
84#define IDC_INVALL	0x0c000000	/* Invalidate all */
85
86#define DC_FLINE	0x0e000000	/* Flush data cache line */
87#define DC_SFWT		0x01000000	/* Set forced writethrough mode */
88#define DC_CFWT		0x03000000	/* Clear forced writethrough mode */
89#define DC_SLES		0x05000000	/* Set little endian swap mode */
90#define DC_CLES		0x07000000	/* Clear little endian swap mode */
91
92/* Status.
93*/
94#define IDC_ENABLED	0x80000000	/* Cache is enabled */
95#define IDC_CERR1	0x00200000	/* Cache error 1 */
96#define IDC_CERR2	0x00100000	/* Cache error 2 */
97#define IDC_CERR3	0x00080000	/* Cache error 3 */
98
99#define DC_DFWT		0x40000000	/* Data cache is forced write through */
100#define DC_LES		0x20000000	/* Caches are little endian mode */
101
102#if !defined(__ASSEMBLY__)
103static inline uint rd_ic_cst(void)
104{
105	return mfspr(IC_CST);
106}
107
108static inline void wr_ic_cst(uint val)
109{
110	mtspr(IC_CST, val);
111}
112
113static inline void wr_ic_adr(uint val)
114{
115	mtspr(IC_ADR, val);
116}
117
118static inline uint rd_dc_cst(void)
119{
120	return mfspr(DC_CST);
121}
122
123static inline void wr_dc_cst(uint val)
124{
125	mtspr(DC_CST, val);
126}
127
128static inline void wr_dc_adr(uint val)
129{
130	mtspr(DC_ADR, val);
131}
132#endif
133#endif /* CONFIG_MPC8xx */
134
135#endif
136