/u-boot/arch/m68k/cpu/mcf530x/ |
H A D | interrupts.c | 21 intctrl_t *icr = (intctrl_t *)(MMAP_INTC); local 24 out_be32(&icr->imr, in_be32(&icr->imr) & ~0x00000400); 26 out_8(&icr->icr2, CFG_SYS_TMRINTR_PRI);
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H A D | cpu_init.c | 114 intctrl_t *icr = (intctrl_t *)(MMAP_INTC); local 117 out_be32(&icr->imr, 0xfffffbff); 119 out_8(&icr->icr0, 0x00); /* sw watchdog */ 120 out_8(&icr->icr1, 0x00); /* timer 1 */ 121 out_8(&icr->icr2, 0x88); /* timer 2 */ 122 out_8(&icr->icr3, 0x00); /* i2c */ 123 out_8(&icr->icr4, 0x00); /* uart 0 */ 124 out_8(&icr->icr5, 0x00); /* uart 1 */ 125 out_8(&icr->icr6, 0x00); /* dma 0 */ 126 out_8(&icr 155 intctrl_t *icr = (intctrl_t *)(MMAP_INTC); local [all...] |
/u-boot/drivers/i2c/ |
H A D | mv_i2c.c | 40 u32 icr; member in struct:mv_i2c 50 u32 icr; member in struct:mv_i2c 75 icr_mode = readl(&base->icr) & ICR_MODE_MASK; 76 writel(readl(&base->icr) & ~ICR_IUE, &base->icr); /* disable unit */ 77 writel(readl(&base->icr) | ICR_UR, &base->icr); /* reset the unit */ 79 writel(readl(&base->icr) & ~ICR_IUE, &base->icr); /* disable unit */ 85 writel(I2C_ICR_INIT | icr_mode, &base->icr); [all...] |
H A D | ast_i2c.h | 14 u32 icr; member in struct:ast_i2c_regs
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H A D | ast2600_i2c.h | 12 u32 icr; member in struct:ast2600_i2c_regs
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H A D | stm32f7_i2c.c | 34 u32 icr; /* I2C interrupt clear register */ member in struct:stm32_i2c_regs 380 setbits_le32(®s->icr, STM32_I2C_ICR_BERRCF); 389 setbits_le32(®s->icr, STM32_I2C_ICR_ARLOCF); 398 setbits_le32(®s->icr, STM32_I2C_ICR_NACKCF); 411 setbits_le32(®s->icr, STM32_I2C_ICR_STOPCF);
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H A D | ast_i2c.c | 88 | I2CD_INTR_ABNORMAL, &priv->regs->icr);
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/u-boot/arch/m68k/include/asm/coldfire/ |
H A D | ata.h | 56 u8 icr; /* 0x30 */ member in struct:atac
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H A D | lcd.h | 28 u32 icr; /* 0x38 Refresh Mode Control Register */ member in struct:lcd_ctrl
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/u-boot/drivers/spi/ |
H A D | rk_spi.h | 29 u32 icr; member in struct:rockchip_spi
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H A D | atmel-quadspi.c | 465 u32 iar, icr, ifr; local 470 icr = QSPI_ICR_INST(op->cmd.opcode); 499 icr |= QSPI_ICR_OPT(op->addr.val & 0xff); 556 atmel_qspi_write(icr, aq, QSPI_RICR); 558 atmel_qspi_write(icr, aq, QSPI_WICR); 566 atmel_qspi_write(icr, aq, QSPI_ICR); 624 u32 iar, icr, ifr; local 628 icr = FIELD_PREP(QSPI_ICR_INST_MASK_SAMA7G5, op->cmd.opcode); 692 atmel_qspi_write(icr, aq, QSPI_RICR); 694 atmel_qspi_write(icr, a [all...] |
/u-boot/arch/arm/mach-at91/include/mach/ |
H A D | at91_mc.h | 39 u32 icr; /* 0x20 SDRAMC Interrupt Status Register */ member in struct:at91_sdramc
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/u-boot/drivers/timer/ |
H A D | nomadik-mtu-timer.c | 36 u32 icr; /* Interrupt clear register */ member in struct:nomadik_mtu_regs
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/u-boot/drivers/mtd/nand/raw/ |
H A D | lpc32xx_nand_mlc.c | 51 u32 icr; member in struct:lpc32xx_nand_mlc_registers 132 &lpc32xx_nand_mlc_registers->icr);
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H A D | lpc32xx_nand_slc.c | 39 u32 icr; member in struct:lpc32xx_nand_slc_regs 127 &lpc32xx_nand_slc_regs->icr);
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/u-boot/arch/powerpc/include/asm/ |
H A D | immap_83xx.h | 225 u32 icr; /* external interrupt control register */ member in struct:gpio83xx
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