1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * (C) Copyright 2017 STMicroelectronics 4 */ 5 6#define LOG_CATEGORY UCLASS_I2C 7 8#include <common.h> 9#include <clk.h> 10#include <dm.h> 11#include <i2c.h> 12#include <log.h> 13#include <regmap.h> 14#include <reset.h> 15#include <syscon.h> 16#include <dm/device.h> 17#include <dm/device_compat.h> 18#include <linux/bitops.h> 19#include <linux/delay.h> 20#include <linux/err.h> 21#include <linux/io.h> 22#include <linux/printk.h> 23#include <linux/time.h> 24 25/* STM32 I2C registers */ 26struct stm32_i2c_regs { 27 u32 cr1; /* I2C control register 1 */ 28 u32 cr2; /* I2C control register 2 */ 29 u32 oar1; /* I2C own address 1 register */ 30 u32 oar2; /* I2C own address 2 register */ 31 u32 timingr; /* I2C timing register */ 32 u32 timeoutr; /* I2C timeout register */ 33 u32 isr; /* I2C interrupt and status register */ 34 u32 icr; /* I2C interrupt clear register */ 35 u32 pecr; /* I2C packet error checking register */ 36 u32 rxdr; /* I2C receive data register */ 37 u32 txdr; /* I2C transmit data register */ 38}; 39 40#define STM32_I2C_CR1 0x00 41#define STM32_I2C_CR2 0x04 42#define STM32_I2C_TIMINGR 0x10 43#define STM32_I2C_ISR 0x18 44#define STM32_I2C_ICR 0x1C 45#define STM32_I2C_RXDR 0x24 46#define STM32_I2C_TXDR 0x28 47 48/* STM32 I2C control 1 */ 49#define STM32_I2C_CR1_ANFOFF BIT(12) 50#define STM32_I2C_CR1_DNF_MASK GENMASK(11, 8) 51#define STM32_I2C_CR1_DNF(n) (((n) & 0xf) << 8) 52#define STM32_I2C_CR1_ERRIE BIT(7) 53#define STM32_I2C_CR1_TCIE BIT(6) 54#define STM32_I2C_CR1_STOPIE BIT(5) 55#define STM32_I2C_CR1_NACKIE BIT(4) 56#define STM32_I2C_CR1_ADDRIE BIT(3) 57#define STM32_I2C_CR1_RXIE BIT(2) 58#define STM32_I2C_CR1_TXIE BIT(1) 59#define STM32_I2C_CR1_PE BIT(0) 60 61/* STM32 I2C control 2 */ 62#define STM32_I2C_CR2_RELOAD BIT(24) 63#define STM32_I2C_CR2_NBYTES_MASK GENMASK(23, 16) 64#define STM32_I2C_CR2_NBYTES(n) ((n & 0xff) << 16) 65#define STM32_I2C_CR2_NACK BIT(15) 66#define STM32_I2C_CR2_STOP BIT(14) 67#define STM32_I2C_CR2_START BIT(13) 68#define STM32_I2C_CR2_HEAD10R BIT(12) 69#define STM32_I2C_CR2_ADD10 BIT(11) 70#define STM32_I2C_CR2_RD_WRN BIT(10) 71#define STM32_I2C_CR2_SADD10_MASK GENMASK(9, 0) 72#define STM32_I2C_CR2_SADD10(n) (n & STM32_I2C_CR2_SADD10_MASK) 73#define STM32_I2C_CR2_SADD7_MASK GENMASK(7, 1) 74#define STM32_I2C_CR2_SADD7(n) ((n & 0x7f) << 1) 75#define STM32_I2C_CR2_RESET_MASK (STM32_I2C_CR2_HEAD10R \ 76 | STM32_I2C_CR2_NBYTES_MASK \ 77 | STM32_I2C_CR2_SADD7_MASK \ 78 | STM32_I2C_CR2_RELOAD \ 79 | STM32_I2C_CR2_RD_WRN) 80 81/* STM32 I2C Interrupt Status */ 82#define STM32_I2C_ISR_BUSY BIT(15) 83#define STM32_I2C_ISR_ARLO BIT(9) 84#define STM32_I2C_ISR_BERR BIT(8) 85#define STM32_I2C_ISR_TCR BIT(7) 86#define STM32_I2C_ISR_TC BIT(6) 87#define STM32_I2C_ISR_STOPF BIT(5) 88#define STM32_I2C_ISR_NACKF BIT(4) 89#define STM32_I2C_ISR_ADDR BIT(3) 90#define STM32_I2C_ISR_RXNE BIT(2) 91#define STM32_I2C_ISR_TXIS BIT(1) 92#define STM32_I2C_ISR_TXE BIT(0) 93#define STM32_I2C_ISR_ERRORS (STM32_I2C_ISR_BERR \ 94 | STM32_I2C_ISR_ARLO) 95 96/* STM32 I2C Interrupt Clear */ 97#define STM32_I2C_ICR_ARLOCF BIT(9) 98#define STM32_I2C_ICR_BERRCF BIT(8) 99#define STM32_I2C_ICR_STOPCF BIT(5) 100#define STM32_I2C_ICR_NACKCF BIT(4) 101 102/* STM32 I2C Timing */ 103#define STM32_I2C_TIMINGR_PRESC(n) ((n & 0xf) << 28) 104#define STM32_I2C_TIMINGR_SCLDEL(n) ((n & 0xf) << 20) 105#define STM32_I2C_TIMINGR_SDADEL(n) ((n & 0xf) << 16) 106#define STM32_I2C_TIMINGR_SCLH(n) ((n & 0xff) << 8) 107#define STM32_I2C_TIMINGR_SCLL(n) (n & 0xff) 108 109#define STM32_I2C_MAX_LEN 0xff 110 111#define STM32_I2C_DNF_MAX 15 112 113#define STM32_I2C_ANALOG_FILTER_DELAY_MIN 50 /* ns */ 114#define STM32_I2C_ANALOG_FILTER_DELAY_MAX 260 /* ns */ 115 116#define STM32_I2C_RISE_TIME_DEFAULT 25 /* ns */ 117#define STM32_I2C_FALL_TIME_DEFAULT 10 /* ns */ 118 119#define STM32_PRESC_MAX BIT(4) 120#define STM32_SCLDEL_MAX BIT(4) 121#define STM32_SDADEL_MAX BIT(4) 122#define STM32_SCLH_MAX BIT(8) 123#define STM32_SCLL_MAX BIT(8) 124 125/** 126 * struct stm32_i2c_spec - private i2c specification timing 127 * @rate: I2C bus speed (Hz) 128 * @rate_min: 80% of I2C bus speed (Hz) 129 * @rate_max: 120% of I2C bus speed (Hz) 130 * @fall_max: Max fall time of both SDA and SCL signals (ns) 131 * @rise_max: Max rise time of both SDA and SCL signals (ns) 132 * @hddat_min: Min data hold time (ns) 133 * @vddat_max: Max data valid time (ns) 134 * @sudat_min: Min data setup time (ns) 135 * @l_min: Min low period of the SCL clock (ns) 136 * @h_min: Min high period of the SCL clock (ns) 137 */ 138 139struct stm32_i2c_spec { 140 u32 rate; 141 u32 rate_min; 142 u32 rate_max; 143 u32 fall_max; 144 u32 rise_max; 145 u32 hddat_min; 146 u32 vddat_max; 147 u32 sudat_min; 148 u32 l_min; 149 u32 h_min; 150}; 151 152/** 153 * struct stm32_i2c_setup - private I2C timing setup parameters 154 * @speed_freq: I2C speed frequency (Hz) 155 * @clock_src: I2C clock source frequency (Hz) 156 * @rise_time: Rise time (ns) 157 * @fall_time: Fall time (ns) 158 * @dnf: value of digital filter to apply 159 * @analog_filter: Analog filter delay (On/Off) 160 */ 161struct stm32_i2c_setup { 162 u32 speed_freq; 163 u32 clock_src; 164 u32 rise_time; 165 u32 fall_time; 166 u8 dnf; 167 bool analog_filter; 168}; 169 170/** 171 * struct stm32_i2c_data - driver data for I2C configuration by compatible 172 * @fmp_clr_offset: Fast Mode Plus clear register offset from set register 173 */ 174struct stm32_i2c_data { 175 u32 fmp_clr_offset; 176}; 177 178/** 179 * struct stm32_i2c_timings - private I2C output parameters 180 * @prec: Prescaler value 181 * @scldel: Data setup time 182 * @sdadel: Data hold time 183 * @sclh: SCL high period (master mode) 184 * @sclh: SCL low period (master mode) 185 */ 186struct stm32_i2c_timings { 187 struct list_head node; 188 u8 presc; 189 u8 scldel; 190 u8 sdadel; 191 u8 sclh; 192 u8 scll; 193}; 194 195/** 196 * struct stm32_i2c_priv - private data of the controller 197 * @regs: I2C registers address 198 * @clk: hw i2c clock 199 * @setup: I2C timing setup parameters 200 * @speed: I2C clock frequency of the controller. Standard, Fast or Fast+ 201 * @regmap: holds SYSCFG phandle for Fast Mode Plus bit 202 * @regmap_sreg: register address for setting Fast Mode Plus bits 203 * @regmap_creg: register address for clearing Fast Mode Plus bits 204 * @regmap_mask: mask for Fast Mode Plus bits 205 * @dnf_dt: value of digital filter requested via dt 206 */ 207struct stm32_i2c_priv { 208 struct stm32_i2c_regs *regs; 209 struct clk clk; 210 struct stm32_i2c_setup setup; 211 u32 speed; 212 struct regmap *regmap; 213 u32 regmap_sreg; 214 u32 regmap_creg; 215 u32 regmap_mask; 216 u32 dnf_dt; 217}; 218 219static const struct stm32_i2c_spec i2c_specs[] = { 220 /* Standard speed - 100 KHz */ 221 [IC_SPEED_MODE_STANDARD] = { 222 .rate = I2C_SPEED_STANDARD_RATE, 223 .rate_min = 8000, 224 .rate_max = 120000, 225 .fall_max = 300, 226 .rise_max = 1000, 227 .hddat_min = 0, 228 .vddat_max = 3450, 229 .sudat_min = 250, 230 .l_min = 4700, 231 .h_min = 4000, 232 }, 233 /* Fast speed - 400 KHz */ 234 [IC_SPEED_MODE_FAST] = { 235 .rate = I2C_SPEED_FAST_RATE, 236 .rate_min = 320000, 237 .rate_max = 480000, 238 .fall_max = 300, 239 .rise_max = 300, 240 .hddat_min = 0, 241 .vddat_max = 900, 242 .sudat_min = 100, 243 .l_min = 1300, 244 .h_min = 600, 245 }, 246 /* Fast Plus Speed - 1 MHz */ 247 [IC_SPEED_MODE_FAST_PLUS] = { 248 .rate = I2C_SPEED_FAST_PLUS_RATE, 249 .rate_min = 800000, 250 .rate_max = 1200000, 251 .fall_max = 100, 252 .rise_max = 120, 253 .hddat_min = 0, 254 .vddat_max = 450, 255 .sudat_min = 50, 256 .l_min = 500, 257 .h_min = 260, 258 }, 259}; 260 261static const struct stm32_i2c_data stm32f7_data = { 262 .fmp_clr_offset = 0x00, 263}; 264 265static const struct stm32_i2c_data stm32mp15_data = { 266 .fmp_clr_offset = 0x40, 267}; 268 269static const struct stm32_i2c_data stm32mp13_data = { 270 .fmp_clr_offset = 0x4, 271}; 272 273static int stm32_i2c_check_device_busy(struct stm32_i2c_priv *i2c_priv) 274{ 275 struct stm32_i2c_regs *regs = i2c_priv->regs; 276 u32 status = readl(®s->isr); 277 278 if (status & STM32_I2C_ISR_BUSY) 279 return -EBUSY; 280 281 return 0; 282} 283 284static void stm32_i2c_message_start(struct stm32_i2c_priv *i2c_priv, 285 struct i2c_msg *msg) 286{ 287 struct stm32_i2c_regs *regs = i2c_priv->regs; 288 u32 cr2 = readl(®s->cr2); 289 290 /* Set transfer direction */ 291 cr2 &= ~STM32_I2C_CR2_RD_WRN; 292 if (msg->flags & I2C_M_RD) 293 cr2 |= STM32_I2C_CR2_RD_WRN; 294 295 /* Set slave address */ 296 cr2 &= ~(STM32_I2C_CR2_HEAD10R | STM32_I2C_CR2_ADD10); 297 if (msg->flags & I2C_M_TEN) { 298 cr2 &= ~STM32_I2C_CR2_SADD10_MASK; 299 cr2 |= STM32_I2C_CR2_SADD10(msg->addr); 300 cr2 |= STM32_I2C_CR2_ADD10; 301 } else { 302 cr2 &= ~STM32_I2C_CR2_SADD7_MASK; 303 cr2 |= STM32_I2C_CR2_SADD7(msg->addr); 304 } 305 306 /* Set nb bytes to transfer and reload (if needed) */ 307 cr2 &= ~(STM32_I2C_CR2_NBYTES_MASK | STM32_I2C_CR2_RELOAD); 308 if (msg->len > STM32_I2C_MAX_LEN) { 309 cr2 |= STM32_I2C_CR2_NBYTES(STM32_I2C_MAX_LEN); 310 cr2 |= STM32_I2C_CR2_RELOAD; 311 } else { 312 cr2 |= STM32_I2C_CR2_NBYTES(msg->len); 313 } 314 315 /* Write configurations register */ 316 writel(cr2, ®s->cr2); 317 318 /* START/ReSTART generation */ 319 setbits_le32(®s->cr2, STM32_I2C_CR2_START); 320} 321 322/* 323 * RELOAD mode must be selected if total number of data bytes to be 324 * sent is greater than MAX_LEN 325 */ 326 327static void stm32_i2c_handle_reload(struct stm32_i2c_priv *i2c_priv, 328 struct i2c_msg *msg) 329{ 330 struct stm32_i2c_regs *regs = i2c_priv->regs; 331 u32 cr2 = readl(®s->cr2); 332 333 cr2 &= ~STM32_I2C_CR2_NBYTES_MASK; 334 335 if (msg->len > STM32_I2C_MAX_LEN) { 336 cr2 |= STM32_I2C_CR2_NBYTES(STM32_I2C_MAX_LEN); 337 } else { 338 cr2 &= ~STM32_I2C_CR2_RELOAD; 339 cr2 |= STM32_I2C_CR2_NBYTES(msg->len); 340 } 341 342 writel(cr2, ®s->cr2); 343} 344 345static int stm32_i2c_wait_flags(struct stm32_i2c_priv *i2c_priv, 346 u32 flags, u32 *status) 347{ 348 struct stm32_i2c_regs *regs = i2c_priv->regs; 349 u32 time_start = get_timer(0); 350 351 *status = readl(®s->isr); 352 while (!(*status & flags)) { 353 if (get_timer(time_start) > CONFIG_SYS_HZ) { 354 log_debug("i2c timeout\n"); 355 return -ETIMEDOUT; 356 } 357 358 *status = readl(®s->isr); 359 } 360 361 return 0; 362} 363 364static int stm32_i2c_check_end_of_message(struct stm32_i2c_priv *i2c_priv) 365{ 366 struct stm32_i2c_regs *regs = i2c_priv->regs; 367 u32 mask = STM32_I2C_ISR_ERRORS | STM32_I2C_ISR_NACKF | 368 STM32_I2C_ISR_STOPF; 369 u32 status; 370 int ret; 371 372 ret = stm32_i2c_wait_flags(i2c_priv, mask, &status); 373 if (ret) 374 return ret; 375 376 if (status & STM32_I2C_ISR_BERR) { 377 log_debug("Bus error\n"); 378 379 /* Clear BERR flag */ 380 setbits_le32(®s->icr, STM32_I2C_ICR_BERRCF); 381 382 return -EIO; 383 } 384 385 if (status & STM32_I2C_ISR_ARLO) { 386 log_debug("Arbitration lost\n"); 387 388 /* Clear ARLO flag */ 389 setbits_le32(®s->icr, STM32_I2C_ICR_ARLOCF); 390 391 return -EAGAIN; 392 } 393 394 if (status & STM32_I2C_ISR_NACKF) { 395 log_debug("Receive NACK\n"); 396 397 /* Clear NACK flag */ 398 setbits_le32(®s->icr, STM32_I2C_ICR_NACKCF); 399 400 /* Wait until STOPF flag is set */ 401 mask = STM32_I2C_ISR_STOPF; 402 ret = stm32_i2c_wait_flags(i2c_priv, mask, &status); 403 if (ret) 404 return ret; 405 406 ret = -EIO; 407 } 408 409 if (status & STM32_I2C_ISR_STOPF) { 410 /* Clear STOP flag */ 411 setbits_le32(®s->icr, STM32_I2C_ICR_STOPCF); 412 413 /* Clear control register 2 */ 414 clrbits_le32(®s->cr2, STM32_I2C_CR2_RESET_MASK); 415 } 416 417 return ret; 418} 419 420static int stm32_i2c_message_xfer(struct stm32_i2c_priv *i2c_priv, 421 struct i2c_msg *msg, bool stop) 422{ 423 struct stm32_i2c_regs *regs = i2c_priv->regs; 424 u32 status; 425 u32 mask = msg->flags & I2C_M_RD ? STM32_I2C_ISR_RXNE : 426 STM32_I2C_ISR_TXIS | STM32_I2C_ISR_NACKF; 427 int bytes_to_rw = msg->len > STM32_I2C_MAX_LEN ? 428 STM32_I2C_MAX_LEN : msg->len; 429 int ret = 0; 430 431 /* Add errors */ 432 mask |= STM32_I2C_ISR_ERRORS; 433 434 stm32_i2c_message_start(i2c_priv, msg); 435 436 while (msg->len) { 437 /* 438 * Wait until TXIS/NACKF/BERR/ARLO flags or 439 * RXNE/BERR/ARLO flags are set 440 */ 441 ret = stm32_i2c_wait_flags(i2c_priv, mask, &status); 442 if (ret) 443 break; 444 445 if (status & (STM32_I2C_ISR_NACKF | STM32_I2C_ISR_ERRORS)) 446 break; 447 448 if (status & STM32_I2C_ISR_RXNE) { 449 *msg->buf++ = readb(®s->rxdr); 450 msg->len--; 451 bytes_to_rw--; 452 } 453 454 if (status & STM32_I2C_ISR_TXIS) { 455 writeb(*msg->buf++, ®s->txdr); 456 msg->len--; 457 bytes_to_rw--; 458 } 459 460 if (!bytes_to_rw && msg->len) { 461 /* Wait until TCR flag is set */ 462 mask = STM32_I2C_ISR_TCR; 463 ret = stm32_i2c_wait_flags(i2c_priv, mask, &status); 464 if (ret) 465 break; 466 467 bytes_to_rw = msg->len > STM32_I2C_MAX_LEN ? 468 STM32_I2C_MAX_LEN : msg->len; 469 mask = msg->flags & I2C_M_RD ? STM32_I2C_ISR_RXNE : 470 STM32_I2C_ISR_TXIS | STM32_I2C_ISR_NACKF; 471 472 stm32_i2c_handle_reload(i2c_priv, msg); 473 } else if (!bytes_to_rw) { 474 /* Wait until TC flag is set */ 475 mask = STM32_I2C_ISR_TC; 476 ret = stm32_i2c_wait_flags(i2c_priv, mask, &status); 477 if (ret) 478 break; 479 480 if (!stop) 481 /* Message sent, new message has to be sent */ 482 return 0; 483 } 484 } 485 486 /* End of transfer, send stop condition if appropriate */ 487 if (!ret && !(status & (STM32_I2C_ISR_NACKF | STM32_I2C_ISR_ERRORS))) 488 setbits_le32(®s->cr2, STM32_I2C_CR2_STOP); 489 490 return stm32_i2c_check_end_of_message(i2c_priv); 491} 492 493static int stm32_i2c_xfer(struct udevice *bus, struct i2c_msg *msg, 494 int nmsgs) 495{ 496 struct stm32_i2c_priv *i2c_priv = dev_get_priv(bus); 497 int ret; 498 499 ret = stm32_i2c_check_device_busy(i2c_priv); 500 if (ret) 501 return ret; 502 503 for (; nmsgs > 0; nmsgs--, msg++) { 504 ret = stm32_i2c_message_xfer(i2c_priv, msg, nmsgs == 1); 505 if (ret) 506 return ret; 507 } 508 509 return 0; 510} 511 512static int stm32_i2c_compute_solutions(u32 i2cclk, 513 struct stm32_i2c_setup *setup, 514 const struct stm32_i2c_spec *specs, 515 struct list_head *solutions) 516{ 517 struct stm32_i2c_timings *v; 518 u32 p_prev = STM32_PRESC_MAX; 519 u32 af_delay_min, af_delay_max; 520 u16 p, l, a; 521 int sdadel_min, sdadel_max, scldel_min; 522 int ret = 0; 523 524 af_delay_min = setup->analog_filter ? 525 STM32_I2C_ANALOG_FILTER_DELAY_MIN : 0; 526 af_delay_max = setup->analog_filter ? 527 STM32_I2C_ANALOG_FILTER_DELAY_MAX : 0; 528 529 sdadel_min = specs->hddat_min + setup->fall_time - 530 af_delay_min - (setup->dnf + 3) * i2cclk; 531 532 sdadel_max = specs->vddat_max - setup->rise_time - 533 af_delay_max - (setup->dnf + 4) * i2cclk; 534 535 scldel_min = setup->rise_time + specs->sudat_min; 536 537 if (sdadel_min < 0) 538 sdadel_min = 0; 539 if (sdadel_max < 0) 540 sdadel_max = 0; 541 542 log_debug("SDADEL(min/max): %i/%i, SCLDEL(Min): %i\n", 543 sdadel_min, sdadel_max, scldel_min); 544 545 /* Compute possible values for PRESC, SCLDEL and SDADEL */ 546 for (p = 0; p < STM32_PRESC_MAX; p++) { 547 for (l = 0; l < STM32_SCLDEL_MAX; l++) { 548 int scldel = (l + 1) * (p + 1) * i2cclk; 549 550 if (scldel < scldel_min) 551 continue; 552 553 for (a = 0; a < STM32_SDADEL_MAX; a++) { 554 int sdadel = (a * (p + 1) + 1) * i2cclk; 555 556 if (((sdadel >= sdadel_min) && 557 (sdadel <= sdadel_max)) && 558 (p != p_prev)) { 559 v = calloc(1, sizeof(*v)); 560 if (!v) 561 return -ENOMEM; 562 563 v->presc = p; 564 v->scldel = l; 565 v->sdadel = a; 566 p_prev = p; 567 568 list_add_tail(&v->node, solutions); 569 break; 570 } 571 } 572 573 if (p_prev == p) 574 break; 575 } 576 } 577 578 if (list_empty(solutions)) { 579 log_err("no Prescaler solution\n"); 580 ret = -EPERM; 581 } 582 583 return ret; 584} 585 586static int stm32_i2c_choose_solution(u32 i2cclk, 587 struct stm32_i2c_setup *setup, 588 const struct stm32_i2c_spec *specs, 589 struct list_head *solutions, 590 struct stm32_i2c_timings *s) 591{ 592 struct stm32_i2c_timings *v; 593 u32 i2cbus = DIV_ROUND_CLOSEST(NSEC_PER_SEC, 594 setup->speed_freq); 595 u32 clk_error_prev = i2cbus; 596 u32 clk_min, clk_max; 597 u32 af_delay_min; 598 u32 dnf_delay; 599 u32 tsync; 600 u16 l, h; 601 bool sol_found = false; 602 int ret = 0; 603 604 af_delay_min = setup->analog_filter ? 605 STM32_I2C_ANALOG_FILTER_DELAY_MIN : 0; 606 dnf_delay = setup->dnf * i2cclk; 607 608 tsync = af_delay_min + dnf_delay + (2 * i2cclk); 609 clk_max = NSEC_PER_SEC / specs->rate_min; 610 clk_min = NSEC_PER_SEC / specs->rate_max; 611 612 /* 613 * Among Prescaler possibilities discovered above figures out SCL Low 614 * and High Period. Provided: 615 * - SCL Low Period has to be higher than Low Period of the SCL Clock 616 * defined by I2C Specification. I2C Clock has to be lower than 617 * (SCL Low Period - Analog/Digital filters) / 4. 618 * - SCL High Period has to be lower than High Period of the SCL Clock 619 * defined by I2C Specification 620 * - I2C Clock has to be lower than SCL High Period 621 */ 622 list_for_each_entry(v, solutions, node) { 623 u32 prescaler = (v->presc + 1) * i2cclk; 624 625 for (l = 0; l < STM32_SCLL_MAX; l++) { 626 u32 tscl_l = (l + 1) * prescaler + tsync; 627 628 if (tscl_l < specs->l_min || 629 (i2cclk >= 630 ((tscl_l - af_delay_min - dnf_delay) / 4))) { 631 continue; 632 } 633 634 for (h = 0; h < STM32_SCLH_MAX; h++) { 635 u32 tscl_h = (h + 1) * prescaler + tsync; 636 u32 tscl = tscl_l + tscl_h + 637 setup->rise_time + setup->fall_time; 638 639 if ((tscl >= clk_min) && (tscl <= clk_max) && 640 (tscl_h >= specs->h_min) && 641 (i2cclk < tscl_h)) { 642 u32 clk_error; 643 644 if (tscl > i2cbus) 645 clk_error = tscl - i2cbus; 646 else 647 clk_error = i2cbus - tscl; 648 649 if (clk_error < clk_error_prev) { 650 clk_error_prev = clk_error; 651 v->scll = l; 652 v->sclh = h; 653 sol_found = true; 654 memcpy(s, v, sizeof(*s)); 655 } 656 } 657 } 658 } 659 } 660 661 if (!sol_found) { 662 log_err("no solution at all\n"); 663 ret = -EPERM; 664 } 665 666 return ret; 667} 668 669static const struct stm32_i2c_spec *get_specs(u32 rate) 670{ 671 unsigned int i; 672 673 for (i = 0; i < ARRAY_SIZE(i2c_specs); i++) 674 if (rate <= i2c_specs[i].rate) 675 return &i2c_specs[i]; 676 677 /* NOT REACHED */ 678 return ERR_PTR(-EINVAL); 679} 680 681static int stm32_i2c_compute_timing(struct stm32_i2c_priv *i2c_priv, 682 struct stm32_i2c_timings *output) 683{ 684 struct stm32_i2c_setup *setup = &i2c_priv->setup; 685 const struct stm32_i2c_spec *specs; 686 struct stm32_i2c_timings *v, *_v; 687 struct list_head solutions; 688 u32 i2cclk = DIV_ROUND_CLOSEST(NSEC_PER_SEC, setup->clock_src); 689 int ret; 690 691 specs = get_specs(setup->speed_freq); 692 if (specs == ERR_PTR(-EINVAL)) { 693 log_err("speed out of bound {%d}\n", 694 setup->speed_freq); 695 return -EINVAL; 696 } 697 698 if (setup->rise_time > specs->rise_max || 699 setup->fall_time > specs->fall_max) { 700 log_err("timings out of bound Rise{%d>%d}/Fall{%d>%d}\n", 701 setup->rise_time, specs->rise_max, 702 setup->fall_time, specs->fall_max); 703 return -EINVAL; 704 } 705 706 /* Analog and Digital Filters */ 707 setup->dnf = DIV_ROUND_CLOSEST(i2c_priv->dnf_dt, i2cclk); 708 if (setup->dnf > STM32_I2C_DNF_MAX) { 709 log_err("DNF out of bound %d/%d\n", 710 setup->dnf, STM32_I2C_DNF_MAX); 711 return -EINVAL; 712 } 713 714 INIT_LIST_HEAD(&solutions); 715 ret = stm32_i2c_compute_solutions(i2cclk, setup, specs, &solutions); 716 if (ret) 717 goto exit; 718 719 ret = stm32_i2c_choose_solution(i2cclk, setup, specs, &solutions, output); 720 if (ret) 721 goto exit; 722 723 log_debug("Presc: %i, scldel: %i, sdadel: %i, scll: %i, sclh: %i\n", 724 output->presc, 725 output->scldel, output->sdadel, 726 output->scll, output->sclh); 727 728exit: 729 /* Release list and memory */ 730 list_for_each_entry_safe(v, _v, &solutions, node) { 731 list_del(&v->node); 732 free(v); 733 } 734 735 return ret; 736} 737 738static u32 get_lower_rate(u32 rate) 739{ 740 int i; 741 742 for (i = ARRAY_SIZE(i2c_specs) - 1; i >= 0; i--) 743 if (rate > i2c_specs[i].rate) 744 return i2c_specs[i].rate; 745 746 return i2c_specs[0].rate; 747} 748 749static int stm32_i2c_setup_timing(struct stm32_i2c_priv *i2c_priv, 750 struct stm32_i2c_timings *timing) 751{ 752 struct stm32_i2c_setup *setup = &i2c_priv->setup; 753 int ret = 0; 754 755 setup->speed_freq = i2c_priv->speed; 756 setup->clock_src = clk_get_rate(&i2c_priv->clk); 757 758 if (!setup->clock_src) { 759 log_err("clock rate is 0\n"); 760 return -EINVAL; 761 } 762 763 do { 764 ret = stm32_i2c_compute_timing(i2c_priv, timing); 765 if (ret) { 766 log_debug("failed to compute I2C timings.\n"); 767 if (setup->speed_freq > I2C_SPEED_STANDARD_RATE) { 768 setup->speed_freq = 769 get_lower_rate(setup->speed_freq); 770 log_debug("downgrade I2C Speed Freq to (%i)\n", 771 setup->speed_freq); 772 } else { 773 break; 774 } 775 } 776 } while (ret); 777 778 if (ret) { 779 log_err("impossible to compute I2C timings.\n"); 780 return ret; 781 } 782 783 log_debug("I2C Freq(%i), Clk Source(%i)\n", 784 setup->speed_freq, setup->clock_src); 785 log_debug("I2C Rise(%i) and Fall(%i) Time\n", 786 setup->rise_time, setup->fall_time); 787 log_debug("I2C Analog Filter(%s), DNF(%i)\n", 788 setup->analog_filter ? "On" : "Off", setup->dnf); 789 790 i2c_priv->speed = setup->speed_freq; 791 792 return 0; 793} 794 795static int stm32_i2c_write_fm_plus_bits(struct stm32_i2c_priv *i2c_priv) 796{ 797 int ret; 798 bool enable = i2c_priv->speed > I2C_SPEED_FAST_RATE; 799 800 /* Optional */ 801 if (IS_ERR_OR_NULL(i2c_priv->regmap)) 802 return 0; 803 804 if (i2c_priv->regmap_sreg == i2c_priv->regmap_creg) 805 ret = regmap_update_bits(i2c_priv->regmap, 806 i2c_priv->regmap_sreg, 807 i2c_priv->regmap_mask, 808 enable ? i2c_priv->regmap_mask : 0); 809 else 810 ret = regmap_write(i2c_priv->regmap, 811 enable ? i2c_priv->regmap_sreg : 812 i2c_priv->regmap_creg, 813 i2c_priv->regmap_mask); 814 815 return ret; 816} 817 818static int stm32_i2c_hw_config(struct stm32_i2c_priv *i2c_priv) 819{ 820 struct stm32_i2c_regs *regs = i2c_priv->regs; 821 struct stm32_i2c_timings t; 822 int ret; 823 u32 timing = 0; 824 825 ret = stm32_i2c_setup_timing(i2c_priv, &t); 826 if (ret) 827 return ret; 828 829 /* Disable I2C */ 830 clrbits_le32(®s->cr1, STM32_I2C_CR1_PE); 831 832 /* Setup Fast mode plus if necessary */ 833 ret = stm32_i2c_write_fm_plus_bits(i2c_priv); 834 if (ret) 835 return ret; 836 837 /* Timing settings */ 838 timing |= STM32_I2C_TIMINGR_PRESC(t.presc); 839 timing |= STM32_I2C_TIMINGR_SCLDEL(t.scldel); 840 timing |= STM32_I2C_TIMINGR_SDADEL(t.sdadel); 841 timing |= STM32_I2C_TIMINGR_SCLH(t.sclh); 842 timing |= STM32_I2C_TIMINGR_SCLL(t.scll); 843 writel(timing, ®s->timingr); 844 845 /* Enable I2C */ 846 if (i2c_priv->setup.analog_filter) 847 clrbits_le32(®s->cr1, STM32_I2C_CR1_ANFOFF); 848 else 849 setbits_le32(®s->cr1, STM32_I2C_CR1_ANFOFF); 850 851 /* Program the Digital Filter */ 852 clrsetbits_le32(®s->cr1, STM32_I2C_CR1_DNF_MASK, 853 STM32_I2C_CR1_DNF(i2c_priv->setup.dnf)); 854 855 setbits_le32(®s->cr1, STM32_I2C_CR1_PE); 856 857 return 0; 858} 859 860static int stm32_i2c_set_bus_speed(struct udevice *dev, unsigned int speed) 861{ 862 struct stm32_i2c_priv *i2c_priv = dev_get_priv(dev); 863 864 if (speed > I2C_SPEED_FAST_PLUS_RATE) { 865 dev_dbg(dev, "Speed %d not supported\n", speed); 866 return -EINVAL; 867 } 868 869 i2c_priv->speed = speed; 870 871 return stm32_i2c_hw_config(i2c_priv); 872} 873 874static int stm32_i2c_probe(struct udevice *dev) 875{ 876 struct stm32_i2c_priv *i2c_priv = dev_get_priv(dev); 877 struct reset_ctl reset_ctl; 878 fdt_addr_t addr; 879 int ret; 880 881 addr = dev_read_addr(dev); 882 if (addr == FDT_ADDR_T_NONE) 883 return -EINVAL; 884 885 i2c_priv->regs = (struct stm32_i2c_regs *)addr; 886 887 ret = clk_get_by_index(dev, 0, &i2c_priv->clk); 888 if (ret) 889 return ret; 890 891 ret = clk_enable(&i2c_priv->clk); 892 if (ret) 893 return ret; 894 895 ret = reset_get_by_index(dev, 0, &reset_ctl); 896 if (ret) 897 goto clk_disable; 898 899 reset_assert(&reset_ctl); 900 udelay(2); 901 reset_deassert(&reset_ctl); 902 903 return 0; 904 905clk_disable: 906 clk_disable(&i2c_priv->clk); 907 908 return ret; 909} 910 911static int stm32_of_to_plat(struct udevice *dev) 912{ 913 const struct stm32_i2c_data *data; 914 struct stm32_i2c_priv *i2c_priv = dev_get_priv(dev); 915 int ret; 916 917 data = (const struct stm32_i2c_data *)dev_get_driver_data(dev); 918 if (!data) 919 return -EINVAL; 920 921 i2c_priv->setup.rise_time = dev_read_u32_default(dev, 922 "i2c-scl-rising-time-ns", 923 STM32_I2C_RISE_TIME_DEFAULT); 924 925 i2c_priv->setup.fall_time = dev_read_u32_default(dev, 926 "i2c-scl-falling-time-ns", 927 STM32_I2C_FALL_TIME_DEFAULT); 928 929 i2c_priv->dnf_dt = dev_read_u32_default(dev, "i2c-digital-filter-width-ns", 0); 930 if (!dev_read_bool(dev, "i2c-digital-filter")) 931 i2c_priv->dnf_dt = 0; 932 933 i2c_priv->setup.analog_filter = dev_read_bool(dev, "i2c-analog-filter"); 934 935 /* Optional */ 936 i2c_priv->regmap = syscon_regmap_lookup_by_phandle(dev, 937 "st,syscfg-fmp"); 938 if (!IS_ERR(i2c_priv->regmap)) { 939 u32 fmp[3]; 940 941 ret = dev_read_u32_array(dev, "st,syscfg-fmp", fmp, 3); 942 if (ret) 943 return ret; 944 945 i2c_priv->regmap_sreg = fmp[1]; 946 i2c_priv->regmap_creg = fmp[1] + data->fmp_clr_offset; 947 i2c_priv->regmap_mask = fmp[2]; 948 } 949 950 return 0; 951} 952 953static const struct dm_i2c_ops stm32_i2c_ops = { 954 .xfer = stm32_i2c_xfer, 955 .set_bus_speed = stm32_i2c_set_bus_speed, 956}; 957 958static const struct udevice_id stm32_i2c_of_match[] = { 959 { .compatible = "st,stm32f7-i2c", .data = (ulong)&stm32f7_data }, 960 { .compatible = "st,stm32mp15-i2c", .data = (ulong)&stm32mp15_data }, 961 { .compatible = "st,stm32mp13-i2c", .data = (ulong)&stm32mp13_data }, 962 {} 963}; 964 965U_BOOT_DRIVER(stm32f7_i2c) = { 966 .name = "stm32f7-i2c", 967 .id = UCLASS_I2C, 968 .of_match = stm32_i2c_of_match, 969 .of_to_plat = stm32_of_to_plat, 970 .probe = stm32_i2c_probe, 971 .priv_auto = sizeof(struct stm32_i2c_priv), 972 .ops = &stm32_i2c_ops, 973}; 974