1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * (C) Copyright 2014  Angelo Dureghello <angelo@sysam.it>
4 *
5 */
6
7#include <cpu_func.h>
8#include <init.h>
9#include <watchdog.h>
10#include <asm/immap.h>
11#include <asm/io.h>
12
13#if defined(CONFIG_M5307)
14/*
15 * Simple mcf5307 chip select module init.
16 *
17 * Note: this chip has an issue reported in the device "errata":
18 * MCF5307ER Rev 4.2 reports @ section 35:
19 * Corrupted Return PC in Exception Stack Frame
20 * When processing an autovectored interrupt an error can occur that
21 * causes 0xFFFFFFFF to be written as the return PC value in the
22 * exception stack frame. The problem is caused by a conflict between
23 * an internal autovector access and a chip select mapped to the IACK
24 * address space (0xFFFFXXXX).
25 * Workaround:
26 * Set the C/I bit in the chip select mask register (CSMR) for the
27 * chip select that is mapped to 0xFFFFXXXX.
28 * This will prevent the chip select from asserting for IACK accesses.
29 */
30
31#define MCF5307_SP_ERR_FIX(cs_base, mask)				\
32	do {								\
33		if (((cs_base<<16)+(in_be32(&mask)&0xffff0000)) >=	\
34			0xffff0000)					\
35			setbits_be32(&mask, CSMR_CI);			\
36	} while (0)
37
38void init_csm(void)
39{
40	csm_t *csm = (csm_t *)(MMAP_CSM);
41
42#if (defined(CFG_SYS_CS0_BASE) && defined(CFG_SYS_CS0_MASK) && \
43	defined(CFG_SYS_CS0_CTRL))
44	out_be16(&csm->csar0, CFG_SYS_CS0_BASE);
45	out_be32(&csm->csmr0, CFG_SYS_CS0_MASK);
46	out_be16(&csm->cscr0, CFG_SYS_CS0_CTRL);
47	MCF5307_SP_ERR_FIX(CFG_SYS_CS0_BASE, csm->csmr0);
48#else
49#warning "Chip Select 0 are not initialized/used"
50#endif
51#if (defined(CFG_SYS_CS1_BASE) && defined(CFG_SYS_CS1_MASK) && \
52	defined(CFG_SYS_CS1_CTRL))
53	out_be16(&csm->csar1, CFG_SYS_CS1_BASE);
54	out_be32(&csm->csmr1, CFG_SYS_CS1_MASK);
55	out_be16(&csm->cscr1, CFG_SYS_CS1_CTRL);
56	MCF5307_SP_ERR_FIX(CFG_SYS_CS1_BASE, csm->csmr1);
57#endif
58#if (defined(CFG_SYS_CS2_BASE) && defined(CFG_SYS_CS2_MASK) && \
59	defined(CFG_SYS_CS2_CTRL))
60	out_be16(&csm->csar2, CFG_SYS_CS2_BASE);
61	out_be32(&csm->csmr2, CFG_SYS_CS2_MASK);
62	out_be16(&csm->cscr2, CFG_SYS_CS2_CTRL);
63	MCF5307_SP_ERR_FIX(CFG_SYS_CS2_BASE, csm->csmr2);
64#endif
65#if (defined(CFG_SYS_CS3_BASE) && defined(CFG_SYS_CS3_MASK) && \
66	defined(CFG_SYS_CS3_CTRL))
67	out_be16(&csm->csar3, CFG_SYS_CS3_BASE);
68	out_be32(&csm->csmr3, CFG_SYS_CS3_MASK);
69	out_be16(&csm->cscr3, CFG_SYS_CS3_CTRL);
70	MCF5307_SP_ERR_FIX(CFG_SYS_CS3_BASE, csm->csmr3);
71#endif
72#if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) && \
73	defined(CONFIG_SYS_CS4_CTRL))
74	out_be16(&csm->csar4, CONFIG_SYS_CS4_BASE);
75	out_be32(&csm->csmr4, CONFIG_SYS_CS4_MASK);
76	out_be16(&csm->cscr4, CONFIG_SYS_CS4_CTRL);
77	MCF5307_SP_ERR_FIX(CONFIG_SYS_CS4_BASE, csm->csmr4);
78#endif
79#if (defined(CONFIG_SYS_CS5_BASE) && defined(CONFIG_SYS_CS5_MASK) && \
80	defined(CONFIG_SYS_CS5_CTRL))
81	out_be16(&csm->csar5, CONFIG_SYS_CS5_BASE);
82	out_be32(&csm->csmr5, CONFIG_SYS_CS5_MASK);
83	out_be16(&csm->cscr5, CONFIG_SYS_CS5_CTRL);
84	MCF5307_SP_ERR_FIX(CONFIG_SYS_CS5_BASE, csm->csmr5);
85#endif
86#if (defined(CONFIG_SYS_CS6_BASE) && defined(CONFIG_SYS_CS6_MASK) && \
87	defined(CONFIG_SYS_CS6_CTRL))
88	out_be16(&csm->csar6, CONFIG_SYS_CS6_BASE);
89	out_be32(&csm->csmr6, CONFIG_SYS_CS6_MASK);
90	out_be16(&csm->cscr6, CONFIG_SYS_CS6_CTRL);
91	MCF5307_SP_ERR_FIX(CONFIG_SYS_CS6_BASE, csm->csmr6);
92#endif
93#if (defined(CONFIG_SYS_CS7_BASE) && defined(CONFIG_SYS_CS7_MASK) && \
94	defined(CONFIG_SYS_CS7_CTRL))
95	out_be16(&csm->csar7, CONFIG_SYS_CS7_BASE);
96	out_be32(&csm->csmr7, CONFIG_SYS_CS7_MASK);
97	out_be16(&csm->cscr7, CONFIG_SYS_CS7_CTRL);
98	MCF5307_SP_ERR_FIX(CONFIG_SYS_CS7_BASE, csm->csmr7);
99#endif
100}
101
102/*
103 * Set up the memory map and initialize registers
104 */
105void cpu_init_f(void)
106{
107	sim_t *sim = (sim_t *)(MMAP_SIM);
108
109	out_8(&sim->sypcr, 0x00);
110	out_8(&sim->swivr, 0x0f);
111	out_8(&sim->swsr,  0x00);
112	out_8(&sim->mpark, 0x00);
113
114	intctrl_t *icr = (intctrl_t *)(MMAP_INTC);
115
116	/* timer 2 not masked */
117	out_be32(&icr->imr, 0xfffffbff);
118
119	out_8(&icr->icr0, 0x00); /* sw watchdog */
120	out_8(&icr->icr1, 0x00); /* timer 1     */
121	out_8(&icr->icr2, 0x88); /* timer 2     */
122	out_8(&icr->icr3, 0x00); /* i2c         */
123	out_8(&icr->icr4, 0x00); /* uart 0      */
124	out_8(&icr->icr5, 0x00); /* uart 1      */
125	out_8(&icr->icr6, 0x00); /* dma  0      */
126	out_8(&icr->icr7, 0x00); /* dma  1      */
127	out_8(&icr->icr8, 0x00); /* dma  2      */
128	out_8(&icr->icr9, 0x00); /* dma  3      */
129
130	/* Chipselect Init */
131	init_csm();
132
133	/* enable data/instruction cache now */
134	icache_enable();
135}
136
137/*
138 * initialize higher level parts of CPU like timers
139 */
140int cpu_init_r(void)
141{
142	return 0;
143}
144
145void uart_port_conf(int port)
146{
147}
148
149void arch_preboot_os(void)
150{
151	/*
152	 * OS can change interrupt offsets and are about to boot the OS so
153	 * we need to make sure we disable all async interrupts.
154	 */
155	intctrl_t *icr = (intctrl_t *)(MMAP_INTC);
156
157	out_8(&icr->icr1, 0x00); /* timer 1     */
158	out_8(&icr->icr2, 0x00); /* timer 2     */
159}
160#endif
161