/u-boot/board/freescale/common/ |
H A D | cds_via.c | 10 void mpc85xx_config_via(struct pci_controller *hose, argument 17 pci_hose_write_config_byte(hose, dev, 0x48, 0x08); 19 pci_hose_read_config_dword(hose, dev, PCI_COMMAND, &cmdstat); 21 pci_hose_write_config_dword(hose, dev, PCI_COMMAND, cmdstat); 22 pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08); 23 pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80); 36 pci_hose_write_config_byte(hose, bridge, PCI_IO_BASE, 0); 37 pci_hose_write_config_word(hose, bridge, PCI_IO_BASE_UPPER16, 0); 38 pci_hose_write_config_byte(hose, bridge, PCI_IO_LIMIT, 0x10); 39 pci_hose_write_config_word(hose, bridg 43 mpc85xx_config_via_usbide(struct pci_controller *hose, pci_dev_t dev, struct pci_config_table *tab) argument 61 mpc85xx_config_via_usb(struct pci_controller *hose, pci_dev_t dev, struct pci_config_table *tab) argument 70 mpc85xx_config_via_usb2(struct pci_controller *hose, pci_dev_t dev, struct pci_config_table *tab) argument 79 mpc85xx_config_via_power(struct pci_controller *hose, pci_dev_t dev, struct pci_config_table *tab) argument 90 mpc85xx_config_via_ac97(struct pci_controller *hose, pci_dev_t dev, struct pci_config_table *tab) argument [all...] |
H A D | via.h | 2 void mpc85xx_config_via(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab); 5 void mpc85xx_config_via_usbide(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab); 8 void mpc85xx_config_via_usb(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab); 11 void mpc85xx_config_via_usb2(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab); 14 void mpc85xx_config_via_power(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab); 17 void mpc85xx_config_via_ac97(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab);
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/u-boot/arch/sh/include/asm/ |
H A D | pci.h | 15 int pci_sh7751_init(struct pci_controller *hose); 20 int pci_sh4_init(struct pci_controller *hose); 22 int pci_sh4_read_config_dword(struct pci_controller *hose, 26 int pci_sh4_write_config_dword(struct pci_controller *hose,
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/u-boot/drivers/pci/ |
H A D | pci_auto_common.c | 84 void pciauto_config_init(struct pci_controller *hose) argument 88 hose->pci_io = NULL; 89 hose->pci_mem = NULL; 90 hose->pci_prefetch = NULL; 92 for (i = 0; i < hose->region_count; i++) { 93 switch (hose->regions[i].flags) { 95 if (!hose->pci_io || 96 hose->pci_io->size < hose->regions[i].size) 97 hose [all...] |
H A D | pci_common.c | 82 __weak int pci_skip_dev(struct pci_controller *hose, pci_dev_t dev) argument 87 if (dev == PCI_BDF(hose->first_busno, 0, 0)) { 122 void pci_write_bar32(struct pci_controller *hose, pci_dev_t dev, int barnum, argument 128 pci_hose_write_config_dword(hose, dev, bar, addr_and_ctrl); 131 u32 pci_read_bar32(struct pci_controller *hose, pci_dev_t dev, int barnum) argument 137 pci_hose_read_config_dword(hose, dev, bar, &addr); 144 int __pci_hose_bus_to_phys(struct pci_controller *hose, argument 153 for (i = 0; i < hose->region_count; i++) { 154 res = &hose->regions[i]; 172 phys_addr_t pci_hose_bus_to_phys(struct pci_controller *hose, argument 203 __pci_hose_phys_to_bus(struct pci_controller *hose, phys_addr_t phys_addr, unsigned long flags, unsigned long skip_mask, pci_addr_t *ba) argument 241 pci_hose_phys_to_bus(struct pci_controller *hose, phys_addr_t phys_addr, unsigned long flags) argument 282 pci_hose_find_devices(struct pci_controller *hose, int busnum, struct pci_device_id *ids, int *indexp) argument [all...] |
H A D | pcie_fsl_fixup.c | 19 struct pci_controller *hose = dev_get_uclass_priv(pcie->bus); local 31 if (!hose || !pcie->enabled) 34 fdt_pci_dma_ranges(blob, off, hose);
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H A D | pcie_dw_common.c | 282 struct pci_controller *hose = dev_get_uclass_priv(ctlr); local 317 for (ret = 0; ret < hose->region_count; ret++) { 318 if (hose->regions[ret].flags == PCI_REGION_IO) { 319 pci->io.phys_start = hose->regions[ret].phys_start; /* IO base */ 320 pci->io.bus_start = hose->regions[ret].bus_start; /* IO_bus_addr */ 321 pci->io.size = hose->regions[ret].size; /* IO size */ 322 } else if (hose->regions[ret].flags == PCI_REGION_MEM) { 323 pci->mem.phys_start = hose->regions[ret].phys_start; /* MEM base */ 324 pci->mem.bus_start = hose->regions[ret].bus_start; /* MEM_bus_addr */ 325 pci->mem.size = hose [all...] |
H A D | pci_octeontx.c | 104 struct pci_controller *hose = dev_get_uclass_priv(bus); local 107 address = PCIE_ECAM_OFFSET(PCI_BUS(bdf) + pcie->bus.start - hose->first_busno, 122 struct pci_controller *hose = dev_get_uclass_priv(bus); local 125 address = PCIE_ECAM_OFFSET(PCI_BUS(bdf) + pcie->bus.start - hose->first_busno, 140 struct pci_controller *hose = dev_get_uclass_priv(bus); local 143 u8 pri_bus = pcie->bus.start + 1 - hose->first_busno; 151 address = PCIE_ECAM_OFFSET(PCI_BUS(bdf) + 1 - hose->first_busno, 170 struct pci_controller *hose = dev_get_uclass_priv(bus); local 173 u8 pri_bus = pcie->bus.start + 1 - hose->first_busno; 176 address = PCIE_ECAM_OFFSET(PCI_BUS(bdf) + 1 - hose 203 struct pci_controller *hose = dev_get_uclass_priv(bus); local 227 struct pci_controller *hose = dev_get_uclass_priv(bus); local [all...] |
H A D | pci_msc01.c | 18 struct pci_controller hose; member in struct:msc01_pci_controller 23 hose_to_msc01(struct pci_controller *hose) argument 25 return container_of(hose, struct msc01_pci_controller, hose);
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H A D | pcie_starfive_jh7110.c | 53 struct pci_controller *hose = dev_get_uclass_priv(ctlr); local 70 for (i = 0; i < hose->region_count; i++) { 71 if (hose->regions[i].flags == PCI_REGION_SYS_MEMORY) 75 if (hose->regions[i].bus_start != 76 hose->regions[i].phys_start) 80 hose->regions[i].phys_start, 81 hose->regions[i].bus_start, 82 hose->regions[i].size,
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H A D | pci-rcar-gen3.c | 331 struct pci_controller *hose = dev_get_uclass_priv(dev); local 344 for (i = 0; i < hose->region_count; i++) { 345 if (hose->regions[i].flags != PCI_REGION_SYS_MEMORY) 348 if (hose->regions[i].phys_start == 0) 351 mask = (roundup_pow_of_two(hose->regions[i].size) - 1) & ~0xf; 353 writel(rounddown_pow_of_two(hose->regions[i].phys_start), 355 writel(rounddown_pow_of_two(hose->regions[i].phys_start), 369 for (i = 0, cnt = 0; i < hose->region_count; i++) { 370 if (hose->regions[i].flags == PCI_REGION_SYS_MEMORY) 374 writel((hose [all...] |
H A D | pci-uclass.c | 541 struct pci_controller *hose = dev_get_uclass_priv(bus); local 548 pciauto_config_init(hose); 572 if (hose->last_busno < sub_bus) 573 hose->last_busno = sub_bus; 973 static int decode_regions(struct pci_controller *hose, ofnode parent_node, argument 1001 hose->region_count = 0; 1007 hose->regions = (struct pci_region *) 1009 if (!hose->regions) 1030 __func__, hose->region_count, pci_addr, addr, size, space_code); 1063 for (i = 0; i < hose 1098 struct pci_controller *hose; local 1147 struct pci_controller *hose = dev_get_uclass_priv(bus); local 1209 struct pci_controller *hose = dev_get_uclass_priv(bus); local 1218 struct pci_controller *hose = dev_get_uclass_priv(bus); local 1359 struct pci_controller *hose = dev_get_uclass_priv(bus); local 1418 struct pci_controller *hose; local 1458 struct pci_controller *hose; local [all...] |
H A D | pcie_octeon.c | 45 struct pci_controller *hose = dev_get_uclass_priv(bus); local 54 busno = PCI_BUS(bdf) - hose->first_busno + 1; 81 struct pci_controller *hose = dev_get_uclass_priv(bus); local 86 busno = PCI_BUS(bdf) - hose->first_busno + 1;
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H A D | pci_gt64120.c | 32 struct pci_controller hose; member in struct:gt64120_pci_controller 37 hose_to_gt64120(struct pci_controller *hose) argument 39 return container_of(hose, struct gt64120_pci_controller, hose);
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H A D | pcie_uniphier.c | 269 struct pci_controller *hose) 272 priv->io.phys_start = hose->regions[0].phys_start; /* IO base */ 273 priv->io.bus_start = hose->regions[0].bus_start; /* IO_bus_addr */ 274 priv->io.size = hose->regions[0].size; /* IO size */ 275 priv->mem.phys_start = hose->regions[1].phys_start; /* MEM base */ 276 priv->mem.bus_start = hose->regions[1].bus_start; /* MEM_bus_addr */ 277 priv->mem.size = hose->regions[1].size; /* MEM size */ 294 struct pci_controller *hose = dev_get_uclass_priv(ctlr); local 335 uniphier_pcie_setup_rc(priv, hose); 342 pcie_dw_get_link_width(priv), hose 268 uniphier_pcie_setup_rc(struct uniphier_pcie_priv *priv, struct pci_controller *hose) argument [all...] |
H A D | pcie_dw_mvebu.c | 484 struct pci_controller *hose = dev_get_uclass_priv(ctlr); local 516 hose->first_busno); 519 pcie->region_count = hose->region_count - CONFIG_NR_DRAM_BANKS; 524 pcie->io.phys_start = hose->regions[0].phys_start; 526 pcie->io.bus_start = hose->regions[0].bus_start; 528 pcie->io.size = hose->regions[0].size; 532 pcie->mem.phys_start = hose->regions[pcie->region_count - 1].phys_start; 534 pcie->mem.bus_start = hose->regions[pcie->region_count - 1].bus_start; 536 pcie->mem.size = hose->regions[pcie->region_count - 1].size;
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H A D | pci_compat.c | 18 int pci_hose_##rw##_config_##name(struct pci_controller *hose, \
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H A D | pcie_rockchip.c | 153 struct pci_controller *hose = dev_get_uclass_priv(ctlr); local 165 for (i = 0; i < hose->region_count; i++) { 166 if (hose->regions[i].flags == PCI_REGION_SYS_MEMORY) 169 if (hose->regions[i].flags == PCI_REGION_IO) 175 if (hose->regions[i].bus_start != 176 hose->regions[i].phys_start) 180 addr = hose->regions[i].bus_start; 185 size = hose->regions[i].size; 516 struct pci_controller *hose = dev_get_uclass_priv(ctlr); local 535 dev_seq(dev), hose [all...] |
H A D | pcie_ecam_synquacer.c | 550 struct pci_controller *hose = dev_get_uclass_priv(ctlr); local 556 pcie->io.phys_start = hose->regions[0].phys_start; /* IO base */ 557 pcie->io.bus_start = hose->regions[0].bus_start; /* IO_bus_addr */ 558 pcie->io.size = hose->regions[0].size; /* IO size */ 560 pcie->mem.phys_start = hose->regions[1].phys_start; /* MEM base */ 561 pcie->mem.bus_start = hose->regions[1].bus_start; /* MEM_bus_addr */ 562 pcie->mem.size = hose->regions[1].size; /* MEM size */ 564 pcie->mem64.phys_start = hose->regions[2].phys_start; /* MEM64 base */ 565 pcie->mem64.bus_start = hose->regions[2].bus_start; /* MEM64_bus_addr */ 566 pcie->mem64.size = hose [all...] |
H A D | pci_mvebu.c | 59 struct pci_controller hose; member in struct:mvebu_pcie 124 static inline struct mvebu_pcie *hose_to_pcie(struct pci_controller *hose) argument 126 return container_of(hose, struct mvebu_pcie, hose); 420 struct pci_controller *hose = dev_get_uclass_priv(ctlr); local 525 pci_set_region(hose->regions + 0, pcie->mem.start, 527 hose->region_count = 1; 530 pci_set_region(hose->regions + hose->region_count, 534 hose [all...] |
H A D | pcie_iproc.c | 871 struct pci_controller *hose = dev_get_uclass_priv(bus); local 874 for (i = 0; i < hose->region_count; i++) { 875 if (hose->regions[i].flags == PCI_REGION_MEM || 876 hose->regions[i].flags == PCI_REGION_PREFETCH) { 878 i, &hose->regions[i].bus_start, 879 &hose->regions[i].phys_start, 880 hose->regions[i].size); 882 hose->regions[i].phys_start, 883 hose->regions[i].bus_start, 884 hose [all...] |
/u-boot/include/ |
H A D | pci.h | 602 void (*config_device)(struct pci_controller* hose, pci_dev_t dev, 607 extern void pci_cfgfunc_do_nothing(struct pci_controller* hose, pci_dev_t dev, 609 extern void pci_cfgfunc_config_device(struct pci_controller* hose, pci_dev_t dev, 660 extern phys_addr_t pci_hose_bus_to_phys(struct pci_controller* hose, 662 extern pci_addr_t pci_hose_phys_to_bus(struct pci_controller* hose, 695 extern int pci_hose_read_config_byte(struct pci_controller *hose, 697 extern int pci_hose_read_config_word(struct pci_controller *hose, 699 extern int pci_hose_read_config_dword(struct pci_controller *hose, 701 extern int pci_hose_write_config_byte(struct pci_controller *hose, 703 extern int pci_hose_write_config_word(struct pci_controller *hose, [all...] |
/u-boot/arch/x86/cpu/ivybridge/ |
H A D | cpu.c | 59 struct pci_controller *hose; local 69 hose = dev_get_uclass_priv(bus); 71 /* TODO(sjg@chromium.org): Get rid of gd->hose */ 72 gd->hose = hose;
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/u-boot/arch/powerpc/include/asm/ |
H A D | fsl_pci.h | 27 int fsl_setup_hose(struct pci_controller *hose, unsigned long addr); 28 int fsl_is_pci_agent(struct pci_controller *hose); 29 void fsl_pci_config_unlock(struct pci_controller *hose); 187 void fsl_pci_init(struct pci_controller *hose, struct fsl_pci_info *pci_info); 189 struct pci_controller *hose, int busno);
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/u-boot/cmd/ |
H A D | pci.c | 459 struct pci_controller *hose = dev_get_uclass_priv(pci_get_controller(bus)); local 463 if (!hose) { 468 printf("Buses %02x-%02x\n", hose->first_busno, hose->last_busno); 471 for (i = 0, reg = hose->regions; i < hose->region_count; i++, reg++) {
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