#
04083470 |
|
09-Jan-2024 |
Moritz Fischer <moritzf@google.com> |
drivers: pci: Fix dm_pci_map_bar() to support 64b BARs This enables 64b BARs if CONFIG_SYS_PCI_64BIT is enabled. Reviewed-by: Philip Oberfichtner <pro@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Moritz Fischer <moritzf@google.com> |
#
59b1c9be |
|
10-Mar-2023 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
cmd: pci: Add command to set MPS of all PCIe devices Enable tuning of the PCI Express MPS (Maximum Payload Size) of each device. The Maximum Read Request Size is not altered. The SAFE method uses the largest MPS value supported by all devices in the system for each device. This method is the same algorithm as used by Linux pci=pcie_bus_safe. The PEER2PEER method sets all devices to the minimal (128 byte) MPS, which allows hot plug of devices later that might only support the minimum size, and ensures compatibility of DMA between two devices on the bus. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> |
#
1fcfadcb |
|
27-Sep-2022 |
Michal Suchanek <msuchanek@suse.de> |
dm: pci: Fix doc typo first -> next pci_find_first_device description says it can be used for iteration with itself but it should really be with pci_find_next_device Signed-off-by: Michal Suchanek <msuchanek@suse.de> |
#
2635e3b5 |
|
21-Apr-2022 |
Andrew Scull <ascull@google.com> |
pci: Add mask parameter to dm_pci_map_bar() Add a mask parameter to control the lookup of the PCI region from which the mapping can be made. Signed-off-by: Andrew Scull <ascull@google.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
a822d1de |
|
21-Apr-2022 |
Andrew Scull <ascull@google.com> |
pci: Update dm_pci_bus_to_virt() parameters Add mask parameter and reorder length parameter to match the other PCI address conversion functions. Using PCI_REGION_TYPE as the mask gives the old behaviour. It's converted from a macro to an inline function as the length parameter is now used twice, but should only be calculated once. Signed-off-by: Andrew Scull <ascull@google.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
7739d93d |
|
21-Apr-2022 |
Andrew Scull <ascull@google.com> |
pci: Match region flags using a mask When converting addresses, apply a mask to the region flags during lookup. This allows the caller to specify which flags are important and which are not, for example to exclude system memory regions. The behaviour of the function is changed such that they don't preferentially search for a non-system memory region. However, system memory regions are added after other regions in decode_regions() leading to a similar outcome. Signed-off-by: Andrew Scull <ascull@google.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
12507a2d |
|
21-Apr-2022 |
Andrew Scull <ascull@google.com> |
pci: Map bars with offset and length Evolve dm_pci_map_bar() to include an offset and length parameter. These allow a portion of the memory to be mapped and range checks to be applied. Passing both the offset and length as zero results in the previous behaviour and this is used to migrate the previous callers. Signed-off-by: Andrew Scull <ascull@google.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
398dc367 |
|
21-Apr-2022 |
Andrew Scull <ascull@google.com> |
pci: Range check address conversions When converting between PCI bus and physical addresses, include a length parameter that can be used to check that the entire range fits within one of the PCI regions. This prevents an address being returned that might be only partially valid for the range it is going to be used for. Where the range check is not wanted, passing a length of 0 will have the same behaviour as before this change. Signed-off-by: Andrew Scull <ascull@google.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
60f4142a |
|
21-Apr-2022 |
Andrew Scull <ascull@google.com> |
pci: Fix use of flags in dm_pci_map_bar() The flags parameter of dm_pci_map_bar() is used for PCI region flags rather than memory mapping flags. Fix the type to match that of the region flags and stop using the regions flags as memory mapping flags. Signed-off-by: Andrew Scull <ascull@google.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
d158fa1b |
|
18-Feb-2022 |
This contributor prefers not to receive mails <noreply@example.com> |
pci: Remove duplicate PCI_CLASS_CODE_* and PCI_CLASS_SUB_CODE_* macros Macros PCI_CLASS_CODE_* and PCI_CLASS_SUB_CODE_* are unused and are duplication of PCI_CLASS_* macros defined in pci_ids.h header file. So remove them. Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Stefan Roese <sr@denx.de> |
#
819a43c9 |
|
10-Feb-2022 |
This contributor prefers not to receive mails <noreply@example.com> |
arm: a37xx: pci: Use standard register macros from pci.h PCI config space of the aardvark PCIe Root Port is available only in internal aardvark memory space starting at offset 0x0. PCI Express registers (PCI_EXP_*) start at offset 0xc0. And Advanced Error Reporting registers (PCI_ERR_*) start at offset 0x100. Replace custom aardvark register macros by standard PCI macros from include/pci.h file with fixed offset. Some DEVCTL and AER macros are not defined in include/pci.h file, so define them in the same way as in linux uapi header file pci_regs.h. Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Stefan Roese <sr@denx.de> |
#
185f812c |
|
19-Jan-2022 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
doc: replace @return by Return: Sphinx expects Return: and not @return to indicate a return value. find . -name '*.c' -exec \ sed -i 's/^\(\s\)\*\(\s*\)@return\(\s\)/\1*\2Return:\3/' {} \; find . -name '*.h' -exec \ sed -i 's/^\(\s\)\*\(\s*\)@return\(\s\)/\1*\2Return:\3/' {} \; Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> |
#
a398a51c |
|
20-Nov-2021 |
Maciej W. Rozycki <macro@orcam.me.uk> |
pci: Work around PCIe link training failures Attempt to handle cases with a downstream port of a PCIe switch where link training never completes and the link continues switching between speeds indefinitely with the data link layer never reaching the active state. It has been observed with a downstream port of the ASMedia ASM2824 Gen 3 switch wired to the upstream port of the Pericom PI7C9X2G304 Gen 2 switch, using a Delock Riser Card PCI Express x1 > 2 x PCIe x1 device, P/N 41433, wired to a SiFive HiFive Unmatched board. In this setup the switches are supposed to negotiate the link speed of preferably 5.0GT/s, falling back to 2.5GT/s. However the link continues oscillating between the two speeds, at the rate of 34-35 times per second, with link training reported repeatedly active ~84% of the time, e.g.: 02:03.0 PCI bridge [0604]: ASMedia Technology Inc. ASM2824 PCIe Gen3 Packet Switch [1b21:2824] (rev 01) (prog-if 00 [Normal decode]) [...] Bus: primary=02, secondary=05, subordinate=05, sec-latency=0 [...] Capabilities: [80] Express (v2) Downstream Port (Slot+), MSI 00 [...] LnkSta: Speed 5GT/s (downgraded), Width x1 (ok) TrErr- Train+ SlotClk+ DLActive- BWMgmt+ ABWMgmt- [...] LnkCtl2: Target Link Speed: 8GT/s, EnterCompliance- SpeedDis+, Selectable De-emphasis: -3.5dB Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS- Compliance De-emphasis: -6dB [...] Forcibly limiting the target link speed to 2.5GT/s with the upstream ASM2824 device makes the two switches communicate correctly however: 02:03.0 PCI bridge [0604]: ASMedia Technology Inc. ASM2824 PCIe Gen3 Packet Switch [1b21:2824] (rev 01) (prog-if 00 [Normal decode]) [...] Bus: primary=02, secondary=05, subordinate=09, sec-latency=0 [...] Capabilities: [80] Express (v2) Downstream Port (Slot+), MSI 00 [...] LnkSta: Speed 2.5GT/s (downgraded), Width x1 (ok) TrErr- Train- SlotClk+ DLActive+ BWMgmt- ABWMgmt- [...] LnkCtl2: Target Link Speed: 2.5GT/s, EnterCompliance- SpeedDis+, Selectable De-emphasis: -3.5dB Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS- Compliance De-emphasis: -6dB [...] and then: 05:00.0 PCI bridge [0604]: Pericom Semiconductor PI7C9X2G304 EL/SL PCIe2 3-Port/4-Lane Packet Switch [12d8:2304] (rev 05) (prog-if 00 [Normal decode]) [...] Bus: primary=05, secondary=06, subordinate=09, sec-latency=0 [...] Capabilities: [c0] Express (v2) Upstream Port, MSI 00 [...] LnkSta: Speed 2.5GT/s (downgraded), Width x1 (downgraded) TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt- [...] LnkCtl2: Target Link Speed: 5GT/s, EnterCompliance- SpeedDis- Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS- Compliance De-emphasis: -6dB [...] Make use of this observation then and attempt to detect the inability to negotiate the link speed automatically, and then handle it by hand. Use the Data Link Layer Link Active status flag as the primary indicator of successful link speed negotiation, but given that the flag is optional by hardware to implement (the ASM2824 does have it though), resort to checking for the mandatory Link Bandwidth Management Status flag showing that the link speed or width has been changed in an attempt to correct unreliable link operation (the ASM2824 does set it too). If these checks indicate that link may not operate correctly, then poll the Data Link Layer Link Active status flag along with the Link Training flag for the duration of 200ms to see if the link has stabilised, that is either that the Data Link Layer Link Active status flag has been set or that Link Training has been inactive during at least the second half of the interval. If that has indicated failure, restrict the target speed to 2.5GT/s, request a link retrain and check again if the link has stabilised. If that does not work either, then restore the original speed setting and claim defeat, otherwise we are done. NB interestingly enough with the ASM2824 vs PI7C9X2G304 configuration referred above asking the ASM2824 to retrain with a higher target link speed once the 2.5GT/s speed has been negotiated makes the two devices successfully negotiate 5.0GT/s. Lifting the 2.5GT/s speed restriction would however prevent our workaround from working with an OS that issues a reset and that is unaware of the problem. This is because the devices would then try to negotiate a higher link speed from scratch and fail, while the sticky property of the Target Link Speed setting will keep the 2.5GT/s speed restriction across a reset. Keep the 2.5GT/s speed restriction then, conservatively, if functional once applied. Signed-off-by: Maciej W. Rozycki <macro@orcam.me.uk> Reviewed-by: Stefan Roese <sr@denx.de> |
#
2a8d4025 |
|
26-Nov-2021 |
This contributor prefers not to receive mails <noreply@example.com> |
pci: Add standard PCI Config Address macros Lot of PCI and PCIe controllers are using standard Config Address for PCI Configuration Mechanism #1 or its extended version. So add PCI_CONF1_ADDRESS() and PCI_CONF1_EXT_ADDRESS() macros into U-Boot's pci.h header file which can be suitable for most PCI and PCIe controller drivers. Drivers do not have to invent their own macros and can use these new U-Boot macros. Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
a4bc38da |
|
02-Nov-2021 |
This contributor prefers not to receive mails <noreply@example.com> |
pci: Add standard PCIe ECAM macros Lot of PCIe controllers are using ECAM addressing. So add common ECAM macros into U-Boot's pci.h header file which can be suitable for most PCI controller drivers. Replace custom ECAM address macros in every PCI controller driver by new ECAM macros from U-Boot's pci.h header file. Similar macros are defined also in Linux kernel. There is a small difference between Linux and these new U-Boot macros. U-Boot's PCIE_ECAM_OFFSET() takes device and function numbers in separate arguments. Linux's PCIE_ECAM_OFFSET() takes device and function numbers encoded in one argument. The reason is that U-Boot's PCI_DEVFN() macro is different than Linux's PCI_SLOT() macro. So having device and function numbers in separate arguments makes code more straightforward. Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Stefan Roese <sr@denx.de> |
#
1d7ad685 |
|
25-Sep-2021 |
This contributor prefers not to receive mails <noreply@example.com> |
arm: a37xx: pci: Handle propagation of CRSSVE bit from PCIe Root Port Now that PCI Bridge (PCIe Root Port) for Aardvark is emulated in U-Boot, add support for handling and propagation of CRSSVE bit. When CRSSVE bit is unset (default), driver has to reissue config read/write request on CRS response. CRSSVE bit is supported only when CRSVIS bit is provided in read-only Root Capabilities register. So manually inject this CRSVIS bit into read response for that register. Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Stefan Roese <sr@denx.de> |
#
2649f69f |
|
17-Sep-2021 |
Vladimir Oltean <vladimir.oltean@nxp.com> |
pci: provide prototype for pci_skip_dev outside of #if defined(CONFIG_DM_PCI_COMPAT) The weak definition of pci_skip_dev from drivers/pci/pci_common.c is not under CONFIG_DM_PCI_COMPAT, and that definition needs a previous function prototype declaration to avoid W=1 build warnings. That prototype is not available due to it being under CONFIG_DM_PCI_COMPAT, so move it outside of that preprocessor block. Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
23cacd57 |
|
01-Aug-2021 |
Simon Glass <sjg@chromium.org> |
pci: Drop PCI_INDIRECT_BRIDGE This does not work with driver model so can be removed. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
26543cc6 |
|
01-Aug-2021 |
Simon Glass <sjg@chromium.org> |
pci: Drop old code from header file We don't need this code anymore since when PCI is enabled, driver model is always used. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
63814a69 |
|
01-Aug-2021 |
Simon Glass <sjg@chromium.org> |
pci: imx: Drop DM_PCI check from cpu driver We don't need this check anymore since when PCI is enabled, driver model is always used. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
e8c09d69 |
|
01-Aug-2021 |
Simon Glass <sjg@chromium.org> |
pci: Remove guard around compatibility functions This prevents use of IS_ENABLED() in other files. Functions should be visible in headers even if they are not available at link time. Fix it. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
f5cbb5c7 |
|
27-Jun-2021 |
Simon Glass <sjg@chromium.org> |
x86: pci: Allow binding of some devices before relocation At present only bridge devices are bound before relocation, to save space in pre-relocation memory. In some cases we do actually want to bind a device, e.g. because it provides the console UART. Add a devicetree binding to support this. Use the PCI_VENDEV() macro to encode the cell value. This is present in U-Boot but not used, so move it to the binding header-file. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
e58f3a7d |
|
27-Jun-2021 |
Simon Glass <sjg@chromium.org> |
pci: Use const for pci_find_device_id() etc. These functions don't modify the device-ID struct that is passed in, so mark the argument as const, so the data structure can be declared that way. This allows it to be placed in the rodata section. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
c7b36007 |
|
14-May-2021 |
Tom Rini <trini@konsulko.com> |
pci: Remove non-DM board_pci_fixup_dev() declaration With the ventana boards migrated to DM_PCI and DM_ETH, we can remove this prototype. Cc: Stefano Babic <sbabic@denx.de> Signed-off-by: Tom Rini <trini@konsulko.com> |
#
cecd013f |
|
16-Apr-2021 |
Tim Harvey <tharvey@gateworks.com> |
pci: pci-uclass: Add board_pci_fixup_dev for DM_PCI Add a board_pci_fixup_dev weak function to allow PCI device fixups during enumeration. Signed-off-by: Tim Harvey <tharvey@gateworks.com> |
#
8b85dfc6 |
|
16-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: Avoid accessing seq directly At present various drivers etc. access the device's 'seq' member directly. This makes it harder to change the meaning of that member. Change access to go through a function instead. The drivers/i2c/lpc32xx_i2c.c file is left unchanged for now. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
caa4daa2 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename 'platdata' variables to just 'plat' We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
284d062e |
|
09-Sep-2020 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
pci: add a few ARI related defines Add a few defines related to PCI ARI configuration. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
51eeae91 |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add VF BAR map support for Enhanced Allocation Makes dm_pci_map_bar API available to map BAR for Virtual function PCI devices which support Enhanced Allocation. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> |
#
b8852dcf |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add support for Single-Root I/O Virtualization SR-IOV - Single Root I/O Virtualization PF - Physical Function VF - Virtual Function If SR-IOV capability is present, use it to initialize Virtual Function PCI device instances. pci_sriov_init function will read SR-IOV registers to create VF devices under the PF PCI device and also bind driver if available. This function needs to be invoked from Physical function device driver which expects VF device support, creating minimal impact on existing framework. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> |
#
e0024741 |
|
23-Jul-2020 |
Stefan Roese <sr@denx.de> |
pci: pci-uclass: Dynamically allocate the PCI regions Instead of using a fixed length pre-allocated array of regions, this patch moves to dynamically allocating the regions based on the number of available regions plus the necessary regions for DRAM banks. Since MAX_PCI_REGIONS is not needed any more, its removed completely with this patch. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Thierry Reding <treding@nvidia.com> Cc: Marek Vasut <marek.vasut+renesas@gmail.com> |
#
143eb5b1 |
|
12-May-2020 |
Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
drivers: pci: add api to get dma regions Add api to get dma regions. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com> |
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com> |
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com> |
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
7d994067 |
|
23-Apr-2019 |
Tom Rini <trini@konsulko.com> |
Merge tag 'pull-24apr19' of git://git.denx.de/u-boot-dm Various minor sandbox iumprovements Fixes for tracing with sandbox Refactoring for boot_get_fdt()
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
a8c5f8d3 |
|
15-Oct-2018 |
Bin Meng <bmeng.cn@gmail.com> |
dm: pci: Add APIs to find next capability and extended capability This introduces two new APIs dm_pci_find_next_capability() and dm_pci_find_next_ext_capability() to get PCI capability address and PCI express extended capability address for a given PCI device starting from a given offset. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
dac01fd8 |
|
03-Aug-2018 |
Bin Meng <bmeng.cn@gmail.com> |
dm: pci: Add APIs to find capability and extended capability This introduces two new APIs dm_pci_find_capability() and dm_pci_find_ext_capability() to get PCI capability address and PCI express extended capability address for a given PCI device. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
5d544f96 |
|
03-Aug-2018 |
Bin Meng <bmeng.cn@gmail.com> |
pci: Add all known capability and extended capability ids Currently we don't have a complete list of capability and extended capability ids. This adds them. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
4345998a |
|
03-Aug-2018 |
Bin Meng <bmeng.cn@gmail.com> |
pci: sandbox: Support dynamically binding device driver At present all emulated sandbox pci devices must be present in the device tree in order to be used. The real world pci uclass driver supports pci device driver matching, and we should add such support on sandbox too. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
01259c93 |
|
03-Aug-2018 |
Bin Meng <bmeng.cn@gmail.com> |
pci: Remove 440ep-specific macros These macros should not be put in the generic pci.h header file. Since they are not referenced anywhere, remove them completely. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
5ce9aca8 |
|
14-May-2018 |
Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi> |
PCI: Document pciauto_region_allocate() Add a doc comment for pciauto_region_allocate(). Signed-off-by: Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
d71975ae |
|
14-May-2018 |
Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi> |
PCI: autoconfig: Don't allocate 64-bit addresses to 32-bit only resources Currently, if we happen to allocate an address requiring 64 bits to a device only supporting 32-bit BARs, the address eventually gets silently truncated to 32 bits. Avoid this by adding a new flag to pciauto_region_allocate() to bail out in such situations. Signed-off-by: Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
83d290c5 |
|
06-May-2018 |
Tom Rini <trini@konsulko.com> |
SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com> |
#
ed68ccbf |
|
13-Mar-2018 |
Stefan Roese <sr@denx.de> |
pci: Remove unused ppc4xx variable from struct pci_controller ppc4xx support was removed some time ago. Lets remove the now unused "pci_fb" variable from "struct pci_controller" as well. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Simon Glass <sjg@chromium.org> |
#
badb9922 |
|
19-Sep-2017 |
Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi> |
pci: Add helper for implementing memory-mapped config space accesses This sort of pattern for implementing memory-mapped PCI config space accesses appears in U-Boot twice already, and a third user is coming up. So add helper functions to avoid code duplication, similar to how Linux has pci_generic_config_write and pci_generic_config_read. Signed-off-by: Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
6ecbe137 |
|
12-May-2017 |
Tim Harvey <tharvey@gateworks.com> |
drivers: pci: imx: add imx_pcie_remove function There is no dedicated reset signal wired up for the MX6QDL thus if the bootloader enables the link we need some special handling to get the core back into a state where it is safe to touch it for configuration. While there has been some special handling in the Linux kernel to do this, it was removed in 4.11 thus we need to do it properly in the bootloader and therefore without this if you enable PCI in the bootloader you will hang while booting the 4.11 kernel. This puts the PCIe controller back into a safe state for the kernel driver before launching the kernel. Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com> Tested-by: Peter Senna Tschudin <peter.senna@collabora.com> |
#
eeb5b1ad |
|
10-Mar-2016 |
Stuart Yoder <stuart.yoder@nxp.com> |
pci: make pci_get_hose_head() available to external users Put pci_get_hose_head() prototype in header so it is available to external users, allowing them to find and iterate over all pci controllers. Signed-off-by: Stuart Yoder <stuart.yoder@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
4974a6ff |
|
06-Mar-2016 |
Simon Glass <sjg@chromium.org> |
pci: Correct a few comments and nits Two comments are missing a parameter and there is an extra blank line. Also two of the region access macros are misnamed. Correct these problems. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
319dba1f |
|
06-Mar-2016 |
Simon Glass <sjg@chromium.org> |
pci: Add functions to update PCI configuration registers It is common to read a config register value, clear and set some bits, then write back the updated value. Add functions to do this in one step, for convenience. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
308143ef |
|
02-Feb-2016 |
Bin Meng <bmeng.cn@gmail.com> |
dm: pci: Add missing forward declarations When CONFIG_DM_PCI_COMPAT is not on, there is only a forward declaration for pci_write_config32(). Add other missing ones. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
9d731c82 |
|
18-Jan-2016 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to write a BAR Add a driver-model version of the pci_write_bar32 function so that this is supported in the new API. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
7e78b9ef |
|
29-Nov-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Switch to DM API for PCI address mapping We should use the new address mapping functions unless we are in compatibility mode. Disable the old functions by default. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
21d1fe7e |
|
29-Nov-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add driver model API functions for address mapping At present the PCI address map functions use the old API. Add new functions for this so that drivers can be converted. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
bab17cf1 |
|
29-Nov-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR Add a driver-model function for reading the PCI BAR from a device. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
a0eb8356 |
|
29-Nov-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a driver-model version of pci_find_class() Add a function which scans the driver model device information rather than scanning the PCI bus again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> |
#
5c0bf647 |
|
29-Nov-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a driver-model version of pci_find_device() Add a function which scans the driver model device information rather than scanning the PCI bus again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> |
#
5e23b8b4 |
|
29-Nov-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Use driver model PCI API in auto-config At present we are using legacy functions even in the auto-configuration code used by driver model. Add a new pci_auto.c version which uses the correct API. Create a new pci_internal.h header to hold functions that are used within the PCI subsystem, but are not exported to other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> |
#
f3f1faef |
|
29-Nov-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a dm_ prefix to pci_bus_find_bdf() Most driver model PCI functions have a dm_ prefix. At some point, when the old code is converted to driver model and the old functions are removed, we will drop that prefix. For consistency, we should use the dm_ prefix for all driver model functions. Update pci_bus_find_bdf() accordingly. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
21ccce1b |
|
29-Nov-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a dm_ prefix to pci_get_bdf() Most driver model PCI functions have a dm_ prefix. At some point, when the old code is converted to driver model and the old functions are removed, we will drop that prefix. For consistency, we should use the dm_ prefix for all driver model functions. Update pci_get_bdf() accordingly. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
3ba5f74a |
|
26-Nov-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Disable PCI compatibility functions by default We eventually need to drop the compatibility functions for driver model. As a first step, create a configuration option to enable them and hide them when the option is disabled. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
54fe7b1c |
|
26-Nov-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a comment about how to find struct pci_controller With driver mode, struct pci_controller is stored as uclass-private data. Add a comment to that effect. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
f9260336 |
|
19-Nov-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to find the regions for a PCI bus This function looks up the controller and returns a pointer to each region type. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Stephen Warren <swarren@nvidia.com> Tested-by: Stephen Warren <swarren@nvidia.com> |
#
9f60fb0d |
|
19-Nov-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to get the controller for a bus A PCI bus may be a bridge device where the controller is the bridge's parent. Add a function to return the controller device, given a PCI device. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Stephen Warren <swarren@nvidia.com> Tested-by: Stephen Warren <swarren@nvidia.com> |
#
9289db6c |
|
19-Nov-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add functions to emulate 8- and 16-bit access Provide a few functions to support using 32-bit access to emulate 8- and 16-bit access. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Stephen Warren <swarren@nvidia.com> Tested-by: Stephen Warren <swarren@nvidia.com> |
#
bcbe3d15 |
|
28-Sep-2015 |
Simon Glass <sjg@chromium.org> |
dm: Rename dev_get_parentdata() to dev_get_parent_priv() The current name is inconsistent with other driver model data access functions. Rename it and fix up all users. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Joe Hershberger <joe.hershberger@ni.com> |
#
dc5740df |
|
22-Aug-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a comment to help find pci_hose_read_config_byte, etc. These functions are defined by macros so do not show up with grep. Add a comment to help. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
76c3fbcd |
|
10-Aug-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a way to iterate through all PCI devices These functions allow iteration through all PCI devices including bridges. The children of each PCI bus are returned in turn. This can be useful for configuring, checking or enumerating all the devices. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
66afb4ed |
|
10-Aug-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Provide friendly config access functions At present there are no PCI functions which allow access to PCI configuration using a struct udevice. This is a sad situation for driver model as it makes use of PCI harder. Add these functions. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
5f48d798 |
|
27-Jul-2015 |
Simon Glass <sjg@chromium.org> |
pci: Add a constant for an invalid interrupt Rather than using 0xff in the code, add a constant. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
ed5b580b |
|
09-Jul-2015 |
Minghuan Lian <Minghuan.Lian@freescale.com> |
drivers/pci: Add function to find an extended capability PCIe extends device's configuration space to 4k and provides extended capability. The patch adds function to find them. The code is ported from Linux PCIe driver. Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
4b515e4f |
|
06-Jul-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to get the BDF for a device It is useful to be able to find the full PCI address (bus, device and function) for a PCI device. Add a function to provide this. Adjust the existing code to use this. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
aba92962 |
|
06-Jul-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add support for PCI driver matching At present all PCI devices must be present in the device tree in order to be used. Many or most PCI devices don't require any configuration other than that which is done automatically by U-Boot. It is inefficent to add a node with nothing but a compatible string in order to get a device working. Add a mechanism whereby PCI drivers can be declared along with the device parameters they support (vendor/device/class). When no suitable driver is found in the device tree the list of such devices is consulted to determine the correct driver. If this also fails, then a generic driver is used as before. The mechanism used is very similar to that provided by Linux and the header file defintions are copied from Linux 4.1. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Joe Hershberger <joe.hershberger@ni.com> |
#
6c89663c |
|
07-Jul-2015 |
Bin Meng <bmeng.cn@gmail.com> |
pci: Configure expansion ROM during auto config process Currently PCI expansion ROM address is assigned by a call to pciauto_setup_rom() outside of the pci auto config process. This does not work when expansion ROM is on a device behind PCI bridge where bridge's memory limit register was already programmed to a value that does not cover the newly assigned expansion ROM address. To fix this, we should configure the ROM address during the auto config process. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Acked-by: Simon Glass <sjg@chromium.org> |
#
aec241df |
|
07-Jun-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Use the correct hose when configuring devices Only the PCI controller has access to the PCI region information. Make sure to use the controller (rather than any attached bridges) when configuring devices. This corrects a failure to scan and configure devices when driver model is enabled for PCI. Also add a comment to explain the problem. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
36d0d3b4 |
|
05-Mar-2015 |
Simon Glass <sjg@chromium.org> |
dm: sandbox: pci: Add a PCI emulation uclass Since sandbox does not have real devices (unless it borrows those from the host) it must use emulations. Provide a uclass which permits PCI operations to be passed through to an emulation device. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
ff3e077b |
|
05-Mar-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a uclass for PCI Add a uclass for PCI controllers and a generic one for PCI devices. Adjust the 'pci' command and the existing PCI support to work with this new uclass. Keep most of the compatibility code in a separate file so that it can be removed one day. TODO: Add more header file comments to the new parts of pci.h Signed-off-by: Simon Glass <sjg@chromium.org> |
#
aab6724c |
|
05-Mar-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move common PCI functions into their own file Driver model will share many functions with the existing PCI implementation. Move these into their own file to avoid duplication and confusion. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
250e039d |
|
27-Jan-2015 |
Simon Glass <sjg@chromium.org> |
pci: Add a function to find a device by class There is an existing function prototype in the header file but it is not implemented. Implement something similar. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
4a2708a0 |
|
14-Jan-2015 |
Simon Glass <sjg@chromium.org> |
x86: Access the VGA ROM when needed Add code to the generic pci_rom file to access the VGA ROM in PCI space when needed. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
d622ac39 |
|
15-Dec-2014 |
Masahiro Yamada <masahiroy@kernel.org> |
powerpc: mpc824x: remove MPC824X cpu support All the MPC824X boards are still non-generic boards: A3000, CPC45, CU824, eXalion, MVBLUE, MUSENKI, Sandpoint824x, utx8245 Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Josef Wagner <Wagner@Microsys.de> Cc: Torsten Demke <torsten.demke@fci.com> Cc: Jim Thompson <jim@musenki.com> Cc: Greg Allen <gallen@arlut.utexas.edu> |
#
e8a552eb |
|
14-Nov-2014 |
Simon Glass <sjg@chromium.org> |
pci: Add functions to read and write a BAR address Some PCI functions cannot be auto-configured. Add a function to set up a fixed BAR which can be used in these situations. Also add a function to read the current address of a BAR. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
4efe52bf |
|
12-Nov-2014 |
Thierry Reding <treding@nvidia.com> |
pci: Honour pci_skip_dev() When enumerating devices, honour the pci_skip_dev() function. This can be used by PCI controller drivers to restrict which devices will be probed. This is required by the NVIDIA Tegra PCIe controller driver, which will fail with a data abort exception if an access is attempted to a device number larger than 0 outside of bus 0. pci_skip_dev() is therefore implemented to prevent any such accesses. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Simon Glass <sjg@chromium.org> |
#
0991866c |
|
07-Aug-2014 |
Tim Harvey <tharvey@gateworks.com> |
pci: add support for board_pci_fixup_dev function Some board-level drivers may wish to have per-device fixup functions for PCI devices. Signed-off-by: Tim Harvey <tharvey@gateworks.com> |
#
fa5cec03 |
|
08-Nov-2013 |
Paul Burton <paul.burton@mips.com> |
pci.h: allow inclusion in assembly source This patch simply #ifdef's out the C-specific parts of pci.h when it is included by an assembly file. This will allow the macros it contains to be used from assembly source as will be done in a followup commit adding support for more modern MIPS Malta boards. Signed-off-by: Paul Burton <paul.burton@imgtec.com> |
#
287df01e |
|
11-Oct-2013 |
Zhao Qiang <B45475@freescale.com> |
PCIe:change the method to get the address of a requested capability in configuration space. Previously, the address of a requested capability is define like that "#define PCI_DCR 0x78" But, the addresses of capabilities is different with regard to PCIe revs. So this method is not flexible. Now a function to get the address of a requested capability is added and used. It can get the address dynamically by capability ID. The step of this function: 1. Read Status register in PCIe configuration space to confirm that Capabilities List is valid. 2. Find the address of Capabilities Pointer Register. 3. Find the address of requested capability from the first capability. Signed-off-by: Zhao Qiang <B45475@freescale.com> |
#
7b4e5844 |
|
03-Jul-2013 |
Zang Roy-R61911 <tie-fei.zang@freescale.com> |
powerpc/pcie: add PCIe version 3.x support T4240 PCIe IP is version 3.0 and has some update comparing previous QorIQ products. 1. Move Freescale specific register define to arch/powerpc/include/asm/fsl_pci.h and update the register offset define for T4240. 2. add the status/control register define use status/control register to judge the link status 3. The original code uses 'Programming Interface' field to judge if PCIE is EP or RC mode, however, T4240 does not support this functionality. According to PCIE specification, 'Header Type' offset 0x0e is used to indicate header type, so for PCIE controller, the patch changes code to use 'Header Type' field to identify if the PCIE is RC or EP mode. This patch fixes the PCIe card link up issue on T4240QDS. Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com> |
#
1a459660 |
|
08-Jul-2013 |
Wolfgang Denk <wd@denx.de> |
Add GPL-2.0+ SPDX-License-Identifier to source files Signed-off-by: Wolfgang Denk <wd@denx.de> [trini: Fixup common/cmd_io.c] Signed-off-by: Tom Rini <trini@ti.com> |
#
bc3442aa |
|
11-Jun-2013 |
Simon Glass <sjg@chromium.org> |
pci: Convert extern inline functions to static inline I am not sure of the meaning of extern inline, but this gives errors when building with function instrumenting enabled. Change these functions to static inline. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
842033e6 |
|
30-May-2013 |
Gabor Juhos <juhosg@openwrt.org> |
pci: introduce CONFIG_PCI_INDIRECT_BRIDGE option The pci_indirect.c file is always compiled when CONFIG_PCI is defined although the indirect PCI bridge support is not needed by every board. Introduce a new CONFIG_PCI_INDIRECT_BRIDGE config option and only compile indirect PCI bridge support if this options is enabled. Also add the new option into the configuration files of the boards which needs that. Compile tested for powerpc, x86, arm and nds32. MAKEALL results: powerpc: --------------------- SUMMARY ---------------------------- Boards compiled: 641 Boards with warnings but no errors: 2 ( ELPPC MPC8323ERDB ) ---------------------------------------------------------- Note: the warnings for ELPPC and MPC8323ERDB are present even without the actual patch. x86: --------------------- SUMMARY ---------------------------- Boards compiled: 1 ---------------------------------------------------------- arm: --------------------- SUMMARY ---------------------------- Boards compiled: 311 ---------------------------------------------------------- nds32: --------------------- SUMMARY ---------------------------- Boards compiled: 3 ---------------------------------------------------------- Cc: Tom Rini <trini@ti.com> Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com> Signed-off-by: Gabor Juhos <juhosg@openwrt.org> |
#
55ae10f8 |
|
20-Oct-2012 |
Bill Richardson <wfrichar@chromium.org> |
x86: gpio: Add GPIO driver for Intel ICH6 and later. Implement <asm-generic/gpio.h> functions for Intel ICH6 and later. Only GPIOs 0-31 are handled by this code. Signed-off-by: Bill Richardson <wfrichar@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org> |
#
a3a70725 |
|
24-Mar-2012 |
Linus Walleij <linus.walleij@linaro.org> |
pci: declare pciauto functions in header The FSL PCI driver uses local prototypes for pciauto_[pre|post]scan_setup_bridge(), this does not seem right, so move them to the <pci.h> file. Fixed a small extern declaration too, this is harmless but distracts the view since all other prototypes are explicitly external. Signed-off-by: Linus Walleij <linus.walleij@linaro.org> |
#
a1e47b66 |
|
03-Mar-2012 |
Linus Walleij <linus.walleij@linaro.org> |
pci: move pciauto_config_init() to pci.h Fixing build regressions for the Integrator I get find that a few boards try to work around the missing declaration of pciauto_config_init() by declaring it in the local scope. This does not make sense when the sibling functions are in <pci.h> so move the function to the header, ridding the build error in the Integrator and getting rid of the local declarations here and there. Reported-by: Wolfgang Denk <wd@denx.de> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> |
#
b03a466d |
|
01-Feb-2011 |
Prabhakar Kushwaha <prabhakar@freescale.com> |
powerpc/85xx: Handle PCIe initialization requires for P1021 class SoCs The P1011, P1012, P1015, P1016, P1020, P1021, P1024, & P1025 SoCs require that we initialize the SERDES registers if the lanes are configured for PCIe. Additionally these devices PCIe controller do not support ASPM and we have to explicitly disable it. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
10fa8d7c |
|
19-Jan-2011 |
Leo Liu <liucai.lfn@gmail.com> |
mpc83xx: fix pcie configuration space read/write This patch fix a problem for the pcie enumeration when the mpc83xx pcie controller is connected with switch or we use both of the two pcie controller. Signed-off-by: Leo Liu <liucai.lfn@gmail.com> fix codingstyle and compiler warning: 'pcie_priv' defined but not used Signed-off-by: Kim Phillips <kim.phillips@freescale.com> |
#
3a0e3c27 |
|
17-Dec-2010 |
Kumar Gala <galak@kernel.crashing.org> |
powerpc/fsl-pci: Determine pci_controller based on cfg addr for dts fixup Previously we passed in a specifically named struct pci_controller to determine if we had setup the particular PCI bus. Now we can search for the struct so we dont have to depend on the name or the struct being statically allocated. Introduced new find_hose_by_cfg_addr() to get back a pci_controller struct back by searching for it means we can do things like dynamically allocate them or not have to expose the static structures to all users. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Wolfgang Denk <wd@denx.de> |
#
983eb9d1 |
|
29-Oct-2010 |
Peter Tyser <ptyser@xes-inc.com> |
pci: Clean up PCI info when CONFIG_PCI_SCAN_SHOW This change does the following: - Removes the printing of the PCI interrupt line value. This is normally set to 0 by U-Boot on bootup and is rarely used during everyday operation. - Prints out the PCI function number of a device. Previously a device with multiple functions would be printed identically 2 times, which is generally confusing. For example, on an Intel 2 port gigabit Ethernet card the following was displayed: ... 04 01 8086 1010 0200 00 04 01 8086 1010 0200 00 ... - Prints a text description of each device's PCI class instead of the raw PCI class code. The textual description makes it much easier to determine what devices are installed on a PCI bus. - Changes the general formatting of the PCI device output. Previous output: PCIE1: connected as Root Complex 04 01 8086 1010 0200 00 04 01 8086 1010 0200 00 03 00 10b5 8112 0604 00 02 01 10b5 8518 0604 00 02 02 10b5 8518 0604 00 08 00 1957 0040 0b20 00 07 00 10b5 8518 0604 00 09 00 10b5 8112 0604 00 07 01 10b5 8518 0604 00 07 02 10b5 8518 0604 00 06 00 10b5 8518 0604 00 02 03 10b5 8518 0604 00 01 00 10b5 8518 0604 00 PCIE1: Bus 00 - 0b PCIE2: connected as Root Complex 0d 00 1957 0040 0b20 00 PCIE2: Bus 0c - 0d Updated output: PCIE1: connected as Root Complex 04:01.0 - 8086:1010 - Network controller 04:01.1 - 8086:1010 - Network controller 03:00.0 - 10b5:8112 - Bridge device 02:01.0 - 10b5:8518 - Bridge device 02:02.0 - 10b5:8518 - Bridge device 08:00.0 - 1957:0040 - Processor 07:00.0 - 10b5:8518 - Bridge device 09:00.0 - 10b5:8112 - Bridge device 07:01.0 - 10b5:8518 - Bridge device 07:02.0 - 10b5:8518 - Bridge device 06:00.0 - 10b5:8518 - Bridge device 02:03.0 - 10b5:8518 - Bridge device 01:00.0 - 10b5:8518 - Bridge device PCIE1: Bus 00 - 0b PCIE2: connected as Root Complex 0d:00.0 - 1957:0040 - Processor PCIE2: Bus 0c - 0d Signed-off-by: Peter Tyser <ptyser@xes-inc.com> |
#
8295b944 |
|
05-Aug-2009 |
Kumar Gala <galak@kernel.crashing.org> |
pci/fsl_pci_init: Use PCIe capability to determine if controller is PCIe Change the code to use the PCIe capabilities register to determine if we are a PCIe controller or not. Additionally cleaned up some white space and formatting in the file. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
cc2a8c77 |
|
19-Feb-2009 |
Anton Vorontsov <avorontsov@ru.mvista.com> |
PCI: Add pci_last_busno() helper This is just a handy routine that reports last PCI busno: we walk down all the hoses and return last hose's last_busno. Will be used by PCI/PCIe initialization code. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com> |
#
6e61fae4 |
|
03-Feb-2009 |
Becky Bruce <beckyb@kernel.crashing.org> |
drivers/pci: Create pci_map_bar function It is no longer always true that the pci bus address can be used as the virtual address for pci accesses. pci_map_bar() is created to return the virtual address for a pci region. Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org> |
#
ff4e66e9 |
|
06-Feb-2009 |
Kumar Gala <galak@kernel.crashing.org> |
pci: Rename PCI_REGION_MEMORY to PCI_REGION_SYS_MEMORY for clarity The PCI_REGION_MEMORY and PCI_REGION_MEM are a bit to similar and can be confusing when reading the code. Rename PCI_REGION_MEMORY to PCI_REGION_SYS_MEMORY to clarify its used for system memory mapping purposes. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
fd6646c0 |
|
07-Jan-2009 |
Anton Vorontsov <avorontsov@ru.mvista.com> |
mpc83xx: Add support for MPC83xx PCI-E controllers This patch adds support for MPC83xx PCI-E controllers in Root Complex mode. The patch is based on Tony Li and Dave Liu work[1]. Though unlike the original patch, by default we don't register PCI-E buses for use in U-Boot, we only configure the controllers for future use in other OSes (Linux). This is done because we don't have enough of spare BATs to map all the PCI-E regions. To actually use PCI-E in U-Boot, users should explicitly define CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES symbol in the board file. And only then U-Boot will able to access PCI-E, but at the cost of disabled address translation. [1] http://lists.denx.de/pipermail/u-boot/2008-January/027630.html Signed-off-by: Tony Li <tony.li@freescale.com> Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Acked-by: Dave Liu <daveliu@freescale.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com> |
#
30e76d5e |
|
21-Oct-2008 |
Kumar Gala <galak@kernel.crashing.org> |
pci: Allow for PCI addresses to be 64-bit PCI bus is inherently 64-bit. While not all system require access to the full 64-bit PCI address range some do. This allows those systems to enable the full PCI address width via CONFIG_SYS_PCI_64BIT. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Andrew Fleming-AFLEMING <afleming@freescale.com> Acked-by: Wolfgang Denk <wd@denx.de> |
#
36f32675 |
|
07-May-2008 |
Becky Bruce <bgill@freescale.com> |
Update pci code to use phys_addr_t Physical addrs need to be represented by phys_addr_t, not unsigned long. Otherwise, systems that use CONFIG_PHYS_64BIT are going to fail mightily. Signed-off-by: Becky Bruce <becky.bruce@freescale.com> |
#
63cec581 |
|
02-Aug-2007 |
Ed Swarthout <Ed.Swarthout@freescale.com> |
Make MPC8641's PCI/PCI-E driver a common driver for many FSL parts. All of the PCI/PCI-Express driver and initialization code that was in the MPC8641HPCN port has now been moved into the common drivers/fsl_pci_init.c. In a subsequent patch, this will be utilized by the 85xx ports as well. Common PCI-E IMMAP register blocks for FSL 85xx/86xx are added. Also enable the second PCI-Express controller on 8641 by getting its BATS and CFG_ setup right. Fixed a u16 vendor compiler warning in AHCI driver too. Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com> Signed-off-by: Zhang Wei <wei.zhang@freescale.com> Signed-off-by: Jon Loeliger <jdl@freescale.com> |
#
13a7fcdf |
|
19-Oct-2006 |
Jon Loeliger <jdl@freescale.com> |
* Fix a bunch of compiler warnings for gcc 4.0 Signed-off-by: Matthew McClintock <msm@freescale.com> |
#
f0e6f57f |
|
28-Jun-2006 |
Matthew McClintock <msm@freescale.com> |
* Added PCI-X #defines for PCI-X initialization Patch by Andy Fleming on 17-Mar-2006 Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
7b230f61 |
|
12-Mar-2006 |
Wolfgang Denk <wd@denx.de> |
Merge with git://git.kernel.org/pub/scm/boot/u-boot/u-boot.git#pci
|
#
993a2275 |
|
12-Mar-2006 |
Wolfgang Denk <wd@denx.de> |
Fix bad declaration on pci_cfgfunc_nothing Patch by Sam Song, 19 Jun 2005 |
#
a179012e |
|
11-Jan-2006 |
Kumar Gala <galak@kernel.crashing.org> |
Added support for PCI prefetchable region and BARs If a host controller sets up a region as prefetchable and a device's BAR denotes it as prefetchable, allocate the BAR into the prefetch region. If a BAR is prefetchable and no prefetchable region has been setup by the controller we fall back to allocating the BAR into the normally memory region. Patch by Kumar Gala 11 Jan 2006 |
#
c157d8e2 |
|
01-Aug-2005 |
Stefan Roese <sr@denx.de> |
Add support for AMCC PPC440EP/GR eval boards Yosemite and Yellowstone. Patch by Steven Blakeslee, 27 Jul 2005 |
#
7a8e9bed |
|
31-May-2003 |
Wolfgang Denk <wd@denx.de> |
* Patch by Marc Singer, 29 May 2003: Fixed rarp boot method for IA32 and other little-endian CPUs. * Patch by Marc Singer, 28 May 2003: Added port I/O commands. * Patch by Matthew McClintock, 28 May 2003 - cpu/mpc824x/start.S: fix relocation code when booting from RAM - minor patches for utx8245 * Patch by Daniel Engstr�m, 28 May 2003: x86 update * Patch by Dave Ellis, 9 May 2003 + 27 May 2003: add nand flash support to SXNI855T configuration fix/extend nand flash support: - fix 'nand erase' command so does not erase bad blocks - fix 'nand write' command so does not write to bad blocks - fix nand_probe() so handles no flash detected properly - add doc/README.nand - add .jffs2 and .oob options to nand read/write - add 'nand bad' command to list bad blocks - add 'clean' option to 'nand erase' to write JFFS2 clean markers - make NAND read/write faster * Patch by Rune Torgersen, 23 May 2003: Update for MPC8266ADS board |
#
c7de829c |
|
19-Nov-2002 |
Wolfgang Denk <wd@denx.de> |
* Patch by Thomas Frieden, 13 Nov 2002: Add code for AmigaOne board (preliminary merge to U-Boot, still WIP) * Patch by Jon Diekema, 12 Nov 2002: - Adding URL for IEEE OUI lookup - Making the autoboot #defines dependent on CONFIG_AUTOBOOT_KEYED being defined. - In the CONFIG_EXTRA_ENV_SETTINGS #define, the root-on-initrd and root-on-nfs macros are designed to switch how the default boot method gets defined. |
#
c609719b |
|
02-Nov-2002 |
Wolfgang Denk <wd@denx.de> |
Initial revision |
#
59b1c9be |
|
10-Mar-2023 |
Stephen Carlson <stcarlso@linux.microsoft.com> |
cmd: pci: Add command to set MPS of all PCIe devices Enable tuning of the PCI Express MPS (Maximum Payload Size) of each device. The Maximum Read Request Size is not altered. The SAFE method uses the largest MPS value supported by all devices in the system for each device. This method is the same algorithm as used by Linux pci=pcie_bus_safe. The PEER2PEER method sets all devices to the minimal (128 byte) MPS, which allows hot plug of devices later that might only support the minimum size, and ensures compatibility of DMA between two devices on the bus. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> |
#
1fcfadcb |
|
27-Sep-2022 |
Michal Suchanek <msuchanek@suse.de> |
dm: pci: Fix doc typo first -> next pci_find_first_device description says it can be used for iteration with itself but it should really be with pci_find_next_device Signed-off-by: Michal Suchanek <msuchanek@suse.de> |
#
2635e3b5 |
|
21-Apr-2022 |
Andrew Scull <ascull@google.com> |
pci: Add mask parameter to dm_pci_map_bar() Add a mask parameter to control the lookup of the PCI region from which the mapping can be made. Signed-off-by: Andrew Scull <ascull@google.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
a822d1de |
|
21-Apr-2022 |
Andrew Scull <ascull@google.com> |
pci: Update dm_pci_bus_to_virt() parameters Add mask parameter and reorder length parameter to match the other PCI address conversion functions. Using PCI_REGION_TYPE as the mask gives the old behaviour. It's converted from a macro to an inline function as the length parameter is now used twice, but should only be calculated once. Signed-off-by: Andrew Scull <ascull@google.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
7739d93d |
|
21-Apr-2022 |
Andrew Scull <ascull@google.com> |
pci: Match region flags using a mask When converting addresses, apply a mask to the region flags during lookup. This allows the caller to specify which flags are important and which are not, for example to exclude system memory regions. The behaviour of the function is changed such that they don't preferentially search for a non-system memory region. However, system memory regions are added after other regions in decode_regions() leading to a similar outcome. Signed-off-by: Andrew Scull <ascull@google.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
12507a2d |
|
21-Apr-2022 |
Andrew Scull <ascull@google.com> |
pci: Map bars with offset and length Evolve dm_pci_map_bar() to include an offset and length parameter. These allow a portion of the memory to be mapped and range checks to be applied. Passing both the offset and length as zero results in the previous behaviour and this is used to migrate the previous callers. Signed-off-by: Andrew Scull <ascull@google.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
398dc367 |
|
21-Apr-2022 |
Andrew Scull <ascull@google.com> |
pci: Range check address conversions When converting between PCI bus and physical addresses, include a length parameter that can be used to check that the entire range fits within one of the PCI regions. This prevents an address being returned that might be only partially valid for the range it is going to be used for. Where the range check is not wanted, passing a length of 0 will have the same behaviour as before this change. Signed-off-by: Andrew Scull <ascull@google.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
60f4142a |
|
21-Apr-2022 |
Andrew Scull <ascull@google.com> |
pci: Fix use of flags in dm_pci_map_bar() The flags parameter of dm_pci_map_bar() is used for PCI region flags rather than memory mapping flags. Fix the type to match that of the region flags and stop using the regions flags as memory mapping flags. Signed-off-by: Andrew Scull <ascull@google.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
d158fa1b |
|
18-Feb-2022 |
Pali Rohár <pali@kernel.org> |
pci: Remove duplicate PCI_CLASS_CODE_* and PCI_CLASS_SUB_CODE_* macros Macros PCI_CLASS_CODE_* and PCI_CLASS_SUB_CODE_* are unused and are duplication of PCI_CLASS_* macros defined in pci_ids.h header file. So remove them. Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Stefan Roese <sr@denx.de> |
#
819a43c9 |
|
10-Feb-2022 |
Pali Rohár <pali@kernel.org> |
arm: a37xx: pci: Use standard register macros from pci.h PCI config space of the aardvark PCIe Root Port is available only in internal aardvark memory space starting at offset 0x0. PCI Express registers (PCI_EXP_*) start at offset 0xc0. And Advanced Error Reporting registers (PCI_ERR_*) start at offset 0x100. Replace custom aardvark register macros by standard PCI macros from include/pci.h file with fixed offset. Some DEVCTL and AER macros are not defined in include/pci.h file, so define them in the same way as in linux uapi header file pci_regs.h. Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Stefan Roese <sr@denx.de> |
#
185f812c |
|
19-Jan-2022 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
doc: replace @return by Return: Sphinx expects Return: and not @return to indicate a return value. find . -name '*.c' -exec \ sed -i 's/^\(\s\)\*\(\s*\)@return\(\s\)/\1*\2Return:\3/' {} \; find . -name '*.h' -exec \ sed -i 's/^\(\s\)\*\(\s*\)@return\(\s\)/\1*\2Return:\3/' {} \; Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> |
#
a398a51c |
|
20-Nov-2021 |
Maciej W. Rozycki <macro@orcam.me.uk> |
pci: Work around PCIe link training failures Attempt to handle cases with a downstream port of a PCIe switch where link training never completes and the link continues switching between speeds indefinitely with the data link layer never reaching the active state. It has been observed with a downstream port of the ASMedia ASM2824 Gen 3 switch wired to the upstream port of the Pericom PI7C9X2G304 Gen 2 switch, using a Delock Riser Card PCI Express x1 > 2 x PCIe x1 device, P/N 41433, wired to a SiFive HiFive Unmatched board. In this setup the switches are supposed to negotiate the link speed of preferably 5.0GT/s, falling back to 2.5GT/s. However the link continues oscillating between the two speeds, at the rate of 34-35 times per second, with link training reported repeatedly active ~84% of the time, e.g.: 02:03.0 PCI bridge [0604]: ASMedia Technology Inc. ASM2824 PCIe Gen3 Packet Switch [1b21:2824] (rev 01) (prog-if 00 [Normal decode]) [...] Bus: primary=02, secondary=05, subordinate=05, sec-latency=0 [...] Capabilities: [80] Express (v2) Downstream Port (Slot+), MSI 00 [...] LnkSta: Speed 5GT/s (downgraded), Width x1 (ok) TrErr- Train+ SlotClk+ DLActive- BWMgmt+ ABWMgmt- [...] LnkCtl2: Target Link Speed: 8GT/s, EnterCompliance- SpeedDis+, Selectable De-emphasis: -3.5dB Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS- Compliance De-emphasis: -6dB [...] Forcibly limiting the target link speed to 2.5GT/s with the upstream ASM2824 device makes the two switches communicate correctly however: 02:03.0 PCI bridge [0604]: ASMedia Technology Inc. ASM2824 PCIe Gen3 Packet Switch [1b21:2824] (rev 01) (prog-if 00 [Normal decode]) [...] Bus: primary=02, secondary=05, subordinate=09, sec-latency=0 [...] Capabilities: [80] Express (v2) Downstream Port (Slot+), MSI 00 [...] LnkSta: Speed 2.5GT/s (downgraded), Width x1 (ok) TrErr- Train- SlotClk+ DLActive+ BWMgmt- ABWMgmt- [...] LnkCtl2: Target Link Speed: 2.5GT/s, EnterCompliance- SpeedDis+, Selectable De-emphasis: -3.5dB Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS- Compliance De-emphasis: -6dB [...] and then: 05:00.0 PCI bridge [0604]: Pericom Semiconductor PI7C9X2G304 EL/SL PCIe2 3-Port/4-Lane Packet Switch [12d8:2304] (rev 05) (prog-if 00 [Normal decode]) [...] Bus: primary=05, secondary=06, subordinate=09, sec-latency=0 [...] Capabilities: [c0] Express (v2) Upstream Port, MSI 00 [...] LnkSta: Speed 2.5GT/s (downgraded), Width x1 (downgraded) TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt- [...] LnkCtl2: Target Link Speed: 5GT/s, EnterCompliance- SpeedDis- Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS- Compliance De-emphasis: -6dB [...] Make use of this observation then and attempt to detect the inability to negotiate the link speed automatically, and then handle it by hand. Use the Data Link Layer Link Active status flag as the primary indicator of successful link speed negotiation, but given that the flag is optional by hardware to implement (the ASM2824 does have it though), resort to checking for the mandatory Link Bandwidth Management Status flag showing that the link speed or width has been changed in an attempt to correct unreliable link operation (the ASM2824 does set it too). If these checks indicate that link may not operate correctly, then poll the Data Link Layer Link Active status flag along with the Link Training flag for the duration of 200ms to see if the link has stabilised, that is either that the Data Link Layer Link Active status flag has been set or that Link Training has been inactive during at least the second half of the interval. If that has indicated failure, restrict the target speed to 2.5GT/s, request a link retrain and check again if the link has stabilised. If that does not work either, then restore the original speed setting and claim defeat, otherwise we are done. NB interestingly enough with the ASM2824 vs PI7C9X2G304 configuration referred above asking the ASM2824 to retrain with a higher target link speed once the 2.5GT/s speed has been negotiated makes the two devices successfully negotiate 5.0GT/s. Lifting the 2.5GT/s speed restriction would however prevent our workaround from working with an OS that issues a reset and that is unaware of the problem. This is because the devices would then try to negotiate a higher link speed from scratch and fail, while the sticky property of the Target Link Speed setting will keep the 2.5GT/s speed restriction across a reset. Keep the 2.5GT/s speed restriction then, conservatively, if functional once applied. Signed-off-by: Maciej W. Rozycki <macro@orcam.me.uk> Reviewed-by: Stefan Roese <sr@denx.de> |
#
2a8d4025 |
|
26-Nov-2021 |
Pali Rohár <pali@kernel.org> |
pci: Add standard PCI Config Address macros Lot of PCI and PCIe controllers are using standard Config Address for PCI Configuration Mechanism #1 or its extended version. So add PCI_CONF1_ADDRESS() and PCI_CONF1_EXT_ADDRESS() macros into U-Boot's pci.h header file which can be suitable for most PCI and PCIe controller drivers. Drivers do not have to invent their own macros and can use these new U-Boot macros. Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
a4bc38da |
|
02-Nov-2021 |
Pali Rohár <pali@kernel.org> |
pci: Add standard PCIe ECAM macros Lot of PCIe controllers are using ECAM addressing. So add common ECAM macros into U-Boot's pci.h header file which can be suitable for most PCI controller drivers. Replace custom ECAM address macros in every PCI controller driver by new ECAM macros from U-Boot's pci.h header file. Similar macros are defined also in Linux kernel. There is a small difference between Linux and these new U-Boot macros. U-Boot's PCIE_ECAM_OFFSET() takes device and function numbers in separate arguments. Linux's PCIE_ECAM_OFFSET() takes device and function numbers encoded in one argument. The reason is that U-Boot's PCI_DEVFN() macro is different than Linux's PCI_SLOT() macro. So having device and function numbers in separate arguments makes code more straightforward. Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Stefan Roese <sr@denx.de> |
#
1d7ad685 |
|
25-Sep-2021 |
Pali Rohár <pali@kernel.org> |
arm: a37xx: pci: Handle propagation of CRSSVE bit from PCIe Root Port Now that PCI Bridge (PCIe Root Port) for Aardvark is emulated in U-Boot, add support for handling and propagation of CRSSVE bit. When CRSSVE bit is unset (default), driver has to reissue config read/write request on CRS response. CRSSVE bit is supported only when CRSVIS bit is provided in read-only Root Capabilities register. So manually inject this CRSVIS bit into read response for that register. Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Stefan Roese <sr@denx.de> |
#
2649f69f |
|
17-Sep-2021 |
Vladimir Oltean <vladimir.oltean@nxp.com> |
pci: provide prototype for pci_skip_dev outside of #if defined(CONFIG_DM_PCI_COMPAT) The weak definition of pci_skip_dev from drivers/pci/pci_common.c is not under CONFIG_DM_PCI_COMPAT, and that definition needs a previous function prototype declaration to avoid W=1 build warnings. That prototype is not available due to it being under CONFIG_DM_PCI_COMPAT, so move it outside of that preprocessor block. Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
23cacd57 |
|
01-Aug-2021 |
Simon Glass <sjg@chromium.org> |
pci: Drop PCI_INDIRECT_BRIDGE This does not work with driver model so can be removed. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
26543cc6 |
|
01-Aug-2021 |
Simon Glass <sjg@chromium.org> |
pci: Drop old code from header file We don't need this code anymore since when PCI is enabled, driver model is always used. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
63814a69 |
|
01-Aug-2021 |
Simon Glass <sjg@chromium.org> |
pci: imx: Drop DM_PCI check from cpu driver We don't need this check anymore since when PCI is enabled, driver model is always used. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
e8c09d69 |
|
01-Aug-2021 |
Simon Glass <sjg@chromium.org> |
pci: Remove guard around compatibility functions This prevents use of IS_ENABLED() in other files. Functions should be visible in headers even if they are not available at link time. Fix it. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
f5cbb5c7 |
|
27-Jun-2021 |
Simon Glass <sjg@chromium.org> |
x86: pci: Allow binding of some devices before relocation At present only bridge devices are bound before relocation, to save space in pre-relocation memory. In some cases we do actually want to bind a device, e.g. because it provides the console UART. Add a devicetree binding to support this. Use the PCI_VENDEV() macro to encode the cell value. This is present in U-Boot but not used, so move it to the binding header-file. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
e58f3a7d |
|
27-Jun-2021 |
Simon Glass <sjg@chromium.org> |
pci: Use const for pci_find_device_id() etc. These functions don't modify the device-ID struct that is passed in, so mark the argument as const, so the data structure can be declared that way. This allows it to be placed in the rodata section. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
c7b36007 |
|
14-May-2021 |
Tom Rini <trini@konsulko.com> |
pci: Remove non-DM board_pci_fixup_dev() declaration With the ventana boards migrated to DM_PCI and DM_ETH, we can remove this prototype. Cc: Stefano Babic <sbabic@denx.de> Signed-off-by: Tom Rini <trini@konsulko.com> |
#
cecd013f |
|
16-Apr-2021 |
Tim Harvey <tharvey@gateworks.com> |
pci: pci-uclass: Add board_pci_fixup_dev for DM_PCI Add a board_pci_fixup_dev weak function to allow PCI device fixups during enumeration. Signed-off-by: Tim Harvey <tharvey@gateworks.com> |
#
8b85dfc6 |
|
16-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: Avoid accessing seq directly At present various drivers etc. access the device's 'seq' member directly. This makes it harder to change the meaning of that member. Change access to go through a function instead. The drivers/i2c/lpc32xx_i2c.c file is left unchanged for now. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
caa4daa2 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename 'platdata' variables to just 'plat' We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
284d062e |
|
09-Sep-2020 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
pci: add a few ARI related defines Add a few defines related to PCI ARI configuration. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
51eeae91 |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add VF BAR map support for Enhanced Allocation Makes dm_pci_map_bar API available to map BAR for Virtual function PCI devices which support Enhanced Allocation. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> |
#
b8852dcf |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add support for Single-Root I/O Virtualization SR-IOV - Single Root I/O Virtualization PF - Physical Function VF - Virtual Function If SR-IOV capability is present, use it to initialize Virtual Function PCI device instances. pci_sriov_init function will read SR-IOV registers to create VF devices under the PF PCI device and also bind driver if available. This function needs to be invoked from Physical function device driver which expects VF device support, creating minimal impact on existing framework. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> |
#
e0024741 |
|
23-Jul-2020 |
Stefan Roese <sr@denx.de> |
pci: pci-uclass: Dynamically allocate the PCI regions Instead of using a fixed length pre-allocated array of regions, this patch moves to dynamically allocating the regions based on the number of available regions plus the necessary regions for DRAM banks. Since MAX_PCI_REGIONS is not needed any more, its removed completely with this patch. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Thierry Reding <treding@nvidia.com> Cc: Marek Vasut <marek.vasut+renesas@gmail.com> |
#
143eb5b1 |
|
12-May-2020 |
Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
drivers: pci: add api to get dma regions Add api to get dma regions. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com> |
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com> |
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com> |
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
7d994067 |
|
23-Apr-2019 |
Tom Rini <trini@konsulko.com> |
Merge tag 'pull-24apr19' of git://git.denx.de/u-boot-dm Various minor sandbox iumprovements Fixes for tracing with sandbox Refactoring for boot_get_fdt()
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
a8c5f8d3 |
|
15-Oct-2018 |
Bin Meng <bmeng.cn@gmail.com> |
dm: pci: Add APIs to find next capability and extended capability This introduces two new APIs dm_pci_find_next_capability() and dm_pci_find_next_ext_capability() to get PCI capability address and PCI express extended capability address for a given PCI device starting from a given offset. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
dac01fd8 |
|
03-Aug-2018 |
Bin Meng <bmeng.cn@gmail.com> |
dm: pci: Add APIs to find capability and extended capability This introduces two new APIs dm_pci_find_capability() and dm_pci_find_ext_capability() to get PCI capability address and PCI express extended capability address for a given PCI device. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
5d544f96 |
|
03-Aug-2018 |
Bin Meng <bmeng.cn@gmail.com> |
pci: Add all known capability and extended capability ids Currently we don't have a complete list of capability and extended capability ids. This adds them. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
4345998a |
|
03-Aug-2018 |
Bin Meng <bmeng.cn@gmail.com> |
pci: sandbox: Support dynamically binding device driver At present all emulated sandbox pci devices must be present in the device tree in order to be used. The real world pci uclass driver supports pci device driver matching, and we should add such support on sandbox too. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
01259c93 |
|
03-Aug-2018 |
Bin Meng <bmeng.cn@gmail.com> |
pci: Remove 440ep-specific macros These macros should not be put in the generic pci.h header file. Since they are not referenced anywhere, remove them completely. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
5ce9aca8 |
|
14-May-2018 |
Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi> |
PCI: Document pciauto_region_allocate() Add a doc comment for pciauto_region_allocate(). Signed-off-by: Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
d71975ae |
|
14-May-2018 |
Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi> |
PCI: autoconfig: Don't allocate 64-bit addresses to 32-bit only resources Currently, if we happen to allocate an address requiring 64 bits to a device only supporting 32-bit BARs, the address eventually gets silently truncated to 32 bits. Avoid this by adding a new flag to pciauto_region_allocate() to bail out in such situations. Signed-off-by: Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
83d290c5 |
|
06-May-2018 |
Tom Rini <trini@konsulko.com> |
SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com> |
#
ed68ccbf |
|
13-Mar-2018 |
Stefan Roese <sr@denx.de> |
pci: Remove unused ppc4xx variable from struct pci_controller ppc4xx support was removed some time ago. Lets remove the now unused "pci_fb" variable from "struct pci_controller" as well. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Simon Glass <sjg@chromium.org> |
#
badb9922 |
|
19-Sep-2017 |
Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi> |
pci: Add helper for implementing memory-mapped config space accesses This sort of pattern for implementing memory-mapped PCI config space accesses appears in U-Boot twice already, and a third user is coming up. So add helper functions to avoid code duplication, similar to how Linux has pci_generic_config_write and pci_generic_config_read. Signed-off-by: Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
6ecbe137 |
|
12-May-2017 |
Tim Harvey <tharvey@gateworks.com> |
drivers: pci: imx: add imx_pcie_remove function There is no dedicated reset signal wired up for the MX6QDL thus if the bootloader enables the link we need some special handling to get the core back into a state where it is safe to touch it for configuration. While there has been some special handling in the Linux kernel to do this, it was removed in 4.11 thus we need to do it properly in the bootloader and therefore without this if you enable PCI in the bootloader you will hang while booting the 4.11 kernel. This puts the PCIe controller back into a safe state for the kernel driver before launching the kernel. Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com> Tested-by: Peter Senna Tschudin <peter.senna@collabora.com> |
#
eeb5b1ad |
|
10-Mar-2016 |
Stuart Yoder <stuart.yoder@nxp.com> |
pci: make pci_get_hose_head() available to external users Put pci_get_hose_head() prototype in header so it is available to external users, allowing them to find and iterate over all pci controllers. Signed-off-by: Stuart Yoder <stuart.yoder@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
4974a6ff |
|
06-Mar-2016 |
Simon Glass <sjg@chromium.org> |
pci: Correct a few comments and nits Two comments are missing a parameter and there is an extra blank line. Also two of the region access macros are misnamed. Correct these problems. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
319dba1f |
|
06-Mar-2016 |
Simon Glass <sjg@chromium.org> |
pci: Add functions to update PCI configuration registers It is common to read a config register value, clear and set some bits, then write back the updated value. Add functions to do this in one step, for convenience. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
308143ef |
|
02-Feb-2016 |
Bin Meng <bmeng.cn@gmail.com> |
dm: pci: Add missing forward declarations When CONFIG_DM_PCI_COMPAT is not on, there is only a forward declaration for pci_write_config32(). Add other missing ones. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
9d731c82 |
|
18-Jan-2016 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to write a BAR Add a driver-model version of the pci_write_bar32 function so that this is supported in the new API. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
7e78b9ef |
|
29-Nov-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Switch to DM API for PCI address mapping We should use the new address mapping functions unless we are in compatibility mode. Disable the old functions by default. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
21d1fe7e |
|
29-Nov-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add driver model API functions for address mapping At present the PCI address map functions use the old API. Add new functions for this so that drivers can be converted. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
bab17cf1 |
|
29-Nov-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR Add a driver-model function for reading the PCI BAR from a device. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
a0eb8356 |
|
29-Nov-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a driver-model version of pci_find_class() Add a function which scans the driver model device information rather than scanning the PCI bus again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> |
#
5c0bf647 |
|
29-Nov-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a driver-model version of pci_find_device() Add a function which scans the driver model device information rather than scanning the PCI bus again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> |
#
5e23b8b4 |
|
29-Nov-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Use driver model PCI API in auto-config At present we are using legacy functions even in the auto-configuration code used by driver model. Add a new pci_auto.c version which uses the correct API. Create a new pci_internal.h header to hold functions that are used within the PCI subsystem, but are not exported to other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> |
#
f3f1faef |
|
29-Nov-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a dm_ prefix to pci_bus_find_bdf() Most driver model PCI functions have a dm_ prefix. At some point, when the old code is converted to driver model and the old functions are removed, we will drop that prefix. For consistency, we should use the dm_ prefix for all driver model functions. Update pci_bus_find_bdf() accordingly. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
21ccce1b |
|
29-Nov-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a dm_ prefix to pci_get_bdf() Most driver model PCI functions have a dm_ prefix. At some point, when the old code is converted to driver model and the old functions are removed, we will drop that prefix. For consistency, we should use the dm_ prefix for all driver model functions. Update pci_get_bdf() accordingly. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
3ba5f74a |
|
26-Nov-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Disable PCI compatibility functions by default We eventually need to drop the compatibility functions for driver model. As a first step, create a configuration option to enable them and hide them when the option is disabled. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
54fe7b1c |
|
26-Nov-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a comment about how to find struct pci_controller With driver mode, struct pci_controller is stored as uclass-private data. Add a comment to that effect. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
f9260336 |
|
19-Nov-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to find the regions for a PCI bus This function looks up the controller and returns a pointer to each region type. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Stephen Warren <swarren@nvidia.com> Tested-by: Stephen Warren <swarren@nvidia.com> |
#
9f60fb0d |
|
19-Nov-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to get the controller for a bus A PCI bus may be a bridge device where the controller is the bridge's parent. Add a function to return the controller device, given a PCI device. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Stephen Warren <swarren@nvidia.com> Tested-by: Stephen Warren <swarren@nvidia.com> |
#
9289db6c |
|
19-Nov-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add functions to emulate 8- and 16-bit access Provide a few functions to support using 32-bit access to emulate 8- and 16-bit access. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Stephen Warren <swarren@nvidia.com> Tested-by: Stephen Warren <swarren@nvidia.com> |
#
bcbe3d15 |
|
28-Sep-2015 |
Simon Glass <sjg@chromium.org> |
dm: Rename dev_get_parentdata() to dev_get_parent_priv() The current name is inconsistent with other driver model data access functions. Rename it and fix up all users. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Joe Hershberger <joe.hershberger@ni.com> |
#
dc5740df |
|
22-Aug-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a comment to help find pci_hose_read_config_byte, etc. These functions are defined by macros so do not show up with grep. Add a comment to help. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
76c3fbcd |
|
10-Aug-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a way to iterate through all PCI devices These functions allow iteration through all PCI devices including bridges. The children of each PCI bus are returned in turn. This can be useful for configuring, checking or enumerating all the devices. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
66afb4ed |
|
10-Aug-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Provide friendly config access functions At present there are no PCI functions which allow access to PCI configuration using a struct udevice. This is a sad situation for driver model as it makes use of PCI harder. Add these functions. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
5f48d798 |
|
27-Jul-2015 |
Simon Glass <sjg@chromium.org> |
pci: Add a constant for an invalid interrupt Rather than using 0xff in the code, add a constant. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
ed5b580b |
|
09-Jul-2015 |
Minghuan Lian <Minghuan.Lian@freescale.com> |
drivers/pci: Add function to find an extended capability PCIe extends device's configuration space to 4k and provides extended capability. The patch adds function to find them. The code is ported from Linux PCIe driver. Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
4b515e4f |
|
06-Jul-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to get the BDF for a device It is useful to be able to find the full PCI address (bus, device and function) for a PCI device. Add a function to provide this. Adjust the existing code to use this. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
aba92962 |
|
06-Jul-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add support for PCI driver matching At present all PCI devices must be present in the device tree in order to be used. Many or most PCI devices don't require any configuration other than that which is done automatically by U-Boot. It is inefficent to add a node with nothing but a compatible string in order to get a device working. Add a mechanism whereby PCI drivers can be declared along with the device parameters they support (vendor/device/class). When no suitable driver is found in the device tree the list of such devices is consulted to determine the correct driver. If this also fails, then a generic driver is used as before. The mechanism used is very similar to that provided by Linux and the header file defintions are copied from Linux 4.1. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Joe Hershberger <joe.hershberger@ni.com> |
#
6c89663c |
|
07-Jul-2015 |
Bin Meng <bmeng.cn@gmail.com> |
pci: Configure expansion ROM during auto config process Currently PCI expansion ROM address is assigned by a call to pciauto_setup_rom() outside of the pci auto config process. This does not work when expansion ROM is on a device behind PCI bridge where bridge's memory limit register was already programmed to a value that does not cover the newly assigned expansion ROM address. To fix this, we should configure the ROM address during the auto config process. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Acked-by: Simon Glass <sjg@chromium.org> |
#
aec241df |
|
07-Jun-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Use the correct hose when configuring devices Only the PCI controller has access to the PCI region information. Make sure to use the controller (rather than any attached bridges) when configuring devices. This corrects a failure to scan and configure devices when driver model is enabled for PCI. Also add a comment to explain the problem. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
36d0d3b4 |
|
05-Mar-2015 |
Simon Glass <sjg@chromium.org> |
dm: sandbox: pci: Add a PCI emulation uclass Since sandbox does not have real devices (unless it borrows those from the host) it must use emulations. Provide a uclass which permits PCI operations to be passed through to an emulation device. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
ff3e077b |
|
05-Mar-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a uclass for PCI Add a uclass for PCI controllers and a generic one for PCI devices. Adjust the 'pci' command and the existing PCI support to work with this new uclass. Keep most of the compatibility code in a separate file so that it can be removed one day. TODO: Add more header file comments to the new parts of pci.h Signed-off-by: Simon Glass <sjg@chromium.org> |
#
aab6724c |
|
05-Mar-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move common PCI functions into their own file Driver model will share many functions with the existing PCI implementation. Move these into their own file to avoid duplication and confusion. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
250e039d |
|
27-Jan-2015 |
Simon Glass <sjg@chromium.org> |
pci: Add a function to find a device by class There is an existing function prototype in the header file but it is not implemented. Implement something similar. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
4a2708a0 |
|
14-Jan-2015 |
Simon Glass <sjg@chromium.org> |
x86: Access the VGA ROM when needed Add code to the generic pci_rom file to access the VGA ROM in PCI space when needed. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
d622ac39 |
|
15-Dec-2014 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
powerpc: mpc824x: remove MPC824X cpu support All the MPC824X boards are still non-generic boards: A3000, CPC45, CU824, eXalion, MVBLUE, MUSENKI, Sandpoint824x, utx8245 Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Josef Wagner <Wagner@Microsys.de> Cc: Torsten Demke <torsten.demke@fci.com> Cc: Jim Thompson <jim@musenki.com> Cc: Greg Allen <gallen@arlut.utexas.edu> |
#
e8a552eb |
|
14-Nov-2014 |
Simon Glass <sjg@chromium.org> |
pci: Add functions to read and write a BAR address Some PCI functions cannot be auto-configured. Add a function to set up a fixed BAR which can be used in these situations. Also add a function to read the current address of a BAR. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
4efe52bf |
|
12-Nov-2014 |
Thierry Reding <treding@nvidia.com> |
pci: Honour pci_skip_dev() When enumerating devices, honour the pci_skip_dev() function. This can be used by PCI controller drivers to restrict which devices will be probed. This is required by the NVIDIA Tegra PCIe controller driver, which will fail with a data abort exception if an access is attempted to a device number larger than 0 outside of bus 0. pci_skip_dev() is therefore implemented to prevent any such accesses. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Simon Glass <sjg@chromium.org> |
#
0991866c |
|
07-Aug-2014 |
Tim Harvey <tharvey@gateworks.com> |
pci: add support for board_pci_fixup_dev function Some board-level drivers may wish to have per-device fixup functions for PCI devices. Signed-off-by: Tim Harvey <tharvey@gateworks.com> |
#
fa5cec03 |
|
08-Nov-2013 |
Paul Burton <paul.burton@mips.com> |
pci.h: allow inclusion in assembly source This patch simply #ifdef's out the C-specific parts of pci.h when it is included by an assembly file. This will allow the macros it contains to be used from assembly source as will be done in a followup commit adding support for more modern MIPS Malta boards. Signed-off-by: Paul Burton <paul.burton@imgtec.com> |
#
287df01e |
|
11-Oct-2013 |
Zhao Qiang <B45475@freescale.com> |
PCIe:change the method to get the address of a requested capability in configuration space. Previously, the address of a requested capability is define like that "#define PCI_DCR 0x78" But, the addresses of capabilities is different with regard to PCIe revs. So this method is not flexible. Now a function to get the address of a requested capability is added and used. It can get the address dynamically by capability ID. The step of this function: 1. Read Status register in PCIe configuration space to confirm that Capabilities List is valid. 2. Find the address of Capabilities Pointer Register. 3. Find the address of requested capability from the first capability. Signed-off-by: Zhao Qiang <B45475@freescale.com> |
#
7b4e5844 |
|
03-Jul-2013 |
Zang Roy-R61911 <tie-fei.zang@freescale.com> |
powerpc/pcie: add PCIe version 3.x support T4240 PCIe IP is version 3.0 and has some update comparing previous QorIQ products. 1. Move Freescale specific register define to arch/powerpc/include/asm/fsl_pci.h and update the register offset define for T4240. 2. add the status/control register define use status/control register to judge the link status 3. The original code uses 'Programming Interface' field to judge if PCIE is EP or RC mode, however, T4240 does not support this functionality. According to PCIE specification, 'Header Type' offset 0x0e is used to indicate header type, so for PCIE controller, the patch changes code to use 'Header Type' field to identify if the PCIE is RC or EP mode. This patch fixes the PCIe card link up issue on T4240QDS. Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com> |
#
1a459660 |
|
08-Jul-2013 |
Wolfgang Denk <wd@denx.de> |
Add GPL-2.0+ SPDX-License-Identifier to source files Signed-off-by: Wolfgang Denk <wd@denx.de> [trini: Fixup common/cmd_io.c] Signed-off-by: Tom Rini <trini@ti.com> |
#
bc3442aa |
|
11-Jun-2013 |
Simon Glass <sjg@chromium.org> |
pci: Convert extern inline functions to static inline I am not sure of the meaning of extern inline, but this gives errors when building with function instrumenting enabled. Change these functions to static inline. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
842033e6 |
|
30-May-2013 |
Gabor Juhos <juhosg@openwrt.org> |
pci: introduce CONFIG_PCI_INDIRECT_BRIDGE option The pci_indirect.c file is always compiled when CONFIG_PCI is defined although the indirect PCI bridge support is not needed by every board. Introduce a new CONFIG_PCI_INDIRECT_BRIDGE config option and only compile indirect PCI bridge support if this options is enabled. Also add the new option into the configuration files of the boards which needs that. Compile tested for powerpc, x86, arm and nds32. MAKEALL results: powerpc: --------------------- SUMMARY ---------------------------- Boards compiled: 641 Boards with warnings but no errors: 2 ( ELPPC MPC8323ERDB ) ---------------------------------------------------------- Note: the warnings for ELPPC and MPC8323ERDB are present even without the actual patch. x86: --------------------- SUMMARY ---------------------------- Boards compiled: 1 ---------------------------------------------------------- arm: --------------------- SUMMARY ---------------------------- Boards compiled: 311 ---------------------------------------------------------- nds32: --------------------- SUMMARY ---------------------------- Boards compiled: 3 ---------------------------------------------------------- Cc: Tom Rini <trini@ti.com> Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com> Signed-off-by: Gabor Juhos <juhosg@openwrt.org> |
#
55ae10f8 |
|
20-Oct-2012 |
Bill Richardson <wfrichar@chromium.org> |
x86: gpio: Add GPIO driver for Intel ICH6 and later. Implement <asm-generic/gpio.h> functions for Intel ICH6 and later. Only GPIOs 0-31 are handled by this code. Signed-off-by: Bill Richardson <wfrichar@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org> |
#
a3a70725 |
|
24-Mar-2012 |
Linus Walleij <linus.walleij@linaro.org> |
pci: declare pciauto functions in header The FSL PCI driver uses local prototypes for pciauto_[pre|post]scan_setup_bridge(), this does not seem right, so move them to the <pci.h> file. Fixed a small extern declaration too, this is harmless but distracts the view since all other prototypes are explicitly external. Signed-off-by: Linus Walleij <linus.walleij@linaro.org> |
#
a1e47b66 |
|
03-Mar-2012 |
Linus Walleij <linus.walleij@linaro.org> |
pci: move pciauto_config_init() to pci.h Fixing build regressions for the Integrator I get find that a few boards try to work around the missing declaration of pciauto_config_init() by declaring it in the local scope. This does not make sense when the sibling functions are in <pci.h> so move the function to the header, ridding the build error in the Integrator and getting rid of the local declarations here and there. Reported-by: Wolfgang Denk <wd@denx.de> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> |
#
b03a466d |
|
01-Feb-2011 |
Prabhakar Kushwaha <prabhakar@freescale.com> |
powerpc/85xx: Handle PCIe initialization requires for P1021 class SoCs The P1011, P1012, P1015, P1016, P1020, P1021, P1024, & P1025 SoCs require that we initialize the SERDES registers if the lanes are configured for PCIe. Additionally these devices PCIe controller do not support ASPM and we have to explicitly disable it. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
10fa8d7c |
|
19-Jan-2011 |
Leo Liu <liucai.lfn@gmail.com> |
mpc83xx: fix pcie configuration space read/write This patch fix a problem for the pcie enumeration when the mpc83xx pcie controller is connected with switch or we use both of the two pcie controller. Signed-off-by: Leo Liu <liucai.lfn@gmail.com> fix codingstyle and compiler warning: 'pcie_priv' defined but not used Signed-off-by: Kim Phillips <kim.phillips@freescale.com> |
#
3a0e3c27 |
|
17-Dec-2010 |
Kumar Gala <galak@kernel.crashing.org> |
powerpc/fsl-pci: Determine pci_controller based on cfg addr for dts fixup Previously we passed in a specifically named struct pci_controller to determine if we had setup the particular PCI bus. Now we can search for the struct so we dont have to depend on the name or the struct being statically allocated. Introduced new find_hose_by_cfg_addr() to get back a pci_controller struct back by searching for it means we can do things like dynamically allocate them or not have to expose the static structures to all users. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Wolfgang Denk <wd@denx.de> |
#
983eb9d1 |
|
29-Oct-2010 |
Peter Tyser <ptyser@xes-inc.com> |
pci: Clean up PCI info when CONFIG_PCI_SCAN_SHOW This change does the following: - Removes the printing of the PCI interrupt line value. This is normally set to 0 by U-Boot on bootup and is rarely used during everyday operation. - Prints out the PCI function number of a device. Previously a device with multiple functions would be printed identically 2 times, which is generally confusing. For example, on an Intel 2 port gigabit Ethernet card the following was displayed: ... 04 01 8086 1010 0200 00 04 01 8086 1010 0200 00 ... - Prints a text description of each device's PCI class instead of the raw PCI class code. The textual description makes it much easier to determine what devices are installed on a PCI bus. - Changes the general formatting of the PCI device output. Previous output: PCIE1: connected as Root Complex 04 01 8086 1010 0200 00 04 01 8086 1010 0200 00 03 00 10b5 8112 0604 00 02 01 10b5 8518 0604 00 02 02 10b5 8518 0604 00 08 00 1957 0040 0b20 00 07 00 10b5 8518 0604 00 09 00 10b5 8112 0604 00 07 01 10b5 8518 0604 00 07 02 10b5 8518 0604 00 06 00 10b5 8518 0604 00 02 03 10b5 8518 0604 00 01 00 10b5 8518 0604 00 PCIE1: Bus 00 - 0b PCIE2: connected as Root Complex 0d 00 1957 0040 0b20 00 PCIE2: Bus 0c - 0d Updated output: PCIE1: connected as Root Complex 04:01.0 - 8086:1010 - Network controller 04:01.1 - 8086:1010 - Network controller 03:00.0 - 10b5:8112 - Bridge device 02:01.0 - 10b5:8518 - Bridge device 02:02.0 - 10b5:8518 - Bridge device 08:00.0 - 1957:0040 - Processor 07:00.0 - 10b5:8518 - Bridge device 09:00.0 - 10b5:8112 - Bridge device 07:01.0 - 10b5:8518 - Bridge device 07:02.0 - 10b5:8518 - Bridge device 06:00.0 - 10b5:8518 - Bridge device 02:03.0 - 10b5:8518 - Bridge device 01:00.0 - 10b5:8518 - Bridge device PCIE1: Bus 00 - 0b PCIE2: connected as Root Complex 0d:00.0 - 1957:0040 - Processor PCIE2: Bus 0c - 0d Signed-off-by: Peter Tyser <ptyser@xes-inc.com> |
#
8295b944 |
|
05-Aug-2009 |
Kumar Gala <galak@kernel.crashing.org> |
pci/fsl_pci_init: Use PCIe capability to determine if controller is PCIe Change the code to use the PCIe capabilities register to determine if we are a PCIe controller or not. Additionally cleaned up some white space and formatting in the file. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
cc2a8c77 |
|
19-Feb-2009 |
Anton Vorontsov <avorontsov@ru.mvista.com> |
PCI: Add pci_last_busno() helper This is just a handy routine that reports last PCI busno: we walk down all the hoses and return last hose's last_busno. Will be used by PCI/PCIe initialization code. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com> |
#
6e61fae4 |
|
03-Feb-2009 |
Becky Bruce <beckyb@kernel.crashing.org> |
drivers/pci: Create pci_map_bar function It is no longer always true that the pci bus address can be used as the virtual address for pci accesses. pci_map_bar() is created to return the virtual address for a pci region. Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org> |
#
ff4e66e9 |
|
06-Feb-2009 |
Kumar Gala <galak@kernel.crashing.org> |
pci: Rename PCI_REGION_MEMORY to PCI_REGION_SYS_MEMORY for clarity The PCI_REGION_MEMORY and PCI_REGION_MEM are a bit to similar and can be confusing when reading the code. Rename PCI_REGION_MEMORY to PCI_REGION_SYS_MEMORY to clarify its used for system memory mapping purposes. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
fd6646c0 |
|
07-Jan-2009 |
Anton Vorontsov <avorontsov@ru.mvista.com> |
mpc83xx: Add support for MPC83xx PCI-E controllers This patch adds support for MPC83xx PCI-E controllers in Root Complex mode. The patch is based on Tony Li and Dave Liu work[1]. Though unlike the original patch, by default we don't register PCI-E buses for use in U-Boot, we only configure the controllers for future use in other OSes (Linux). This is done because we don't have enough of spare BATs to map all the PCI-E regions. To actually use PCI-E in U-Boot, users should explicitly define CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES symbol in the board file. And only then U-Boot will able to access PCI-E, but at the cost of disabled address translation. [1] http://lists.denx.de/pipermail/u-boot/2008-January/027630.html Signed-off-by: Tony Li <tony.li@freescale.com> Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Acked-by: Dave Liu <daveliu@freescale.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com> |
#
30e76d5e |
|
21-Oct-2008 |
Kumar Gala <galak@kernel.crashing.org> |
pci: Allow for PCI addresses to be 64-bit PCI bus is inherently 64-bit. While not all system require access to the full 64-bit PCI address range some do. This allows those systems to enable the full PCI address width via CONFIG_SYS_PCI_64BIT. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Andrew Fleming-AFLEMING <afleming@freescale.com> Acked-by: Wolfgang Denk <wd@denx.de> |
#
36f32675 |
|
07-May-2008 |
Becky Bruce <bgill@freescale.com> |
Update pci code to use phys_addr_t Physical addrs need to be represented by phys_addr_t, not unsigned long. Otherwise, systems that use CONFIG_PHYS_64BIT are going to fail mightily. Signed-off-by: Becky Bruce <becky.bruce@freescale.com> |
#
63cec581 |
|
02-Aug-2007 |
Ed Swarthout <Ed.Swarthout@freescale.com> |
Make MPC8641's PCI/PCI-E driver a common driver for many FSL parts. All of the PCI/PCI-Express driver and initialization code that was in the MPC8641HPCN port has now been moved into the common drivers/fsl_pci_init.c. In a subsequent patch, this will be utilized by the 85xx ports as well. Common PCI-E IMMAP register blocks for FSL 85xx/86xx are added. Also enable the second PCI-Express controller on 8641 by getting its BATS and CFG_ setup right. Fixed a u16 vendor compiler warning in AHCI driver too. Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com> Signed-off-by: Zhang Wei <wei.zhang@freescale.com> Signed-off-by: Jon Loeliger <jdl@freescale.com> |
#
13a7fcdf |
|
19-Oct-2006 |
Jon Loeliger <jdl@freescale.com> |
* Fix a bunch of compiler warnings for gcc 4.0 Signed-off-by: Matthew McClintock <msm@freescale.com> |
#
f0e6f57f |
|
28-Jun-2006 |
Matthew McClintock <msm@freescale.com> |
* Added PCI-X #defines for PCI-X initialization Patch by Andy Fleming on 17-Mar-2006 Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
7b230f61 |
|
12-Mar-2006 |
Wolfgang Denk <wd@denx.de> |
Merge with git://git.kernel.org/pub/scm/boot/u-boot/u-boot.git#pci
|
#
993a2275 |
|
12-Mar-2006 |
Wolfgang Denk <wd@denx.de> |
Fix bad declaration on pci_cfgfunc_nothing Patch by Sam Song, 19 Jun 2005 |
#
a179012e |
|
11-Jan-2006 |
Kumar Gala <galak@kernel.crashing.org> |
Added support for PCI prefetchable region and BARs If a host controller sets up a region as prefetchable and a device's BAR denotes it as prefetchable, allocate the BAR into the prefetch region. If a BAR is prefetchable and no prefetchable region has been setup by the controller we fall back to allocating the BAR into the normally memory region. Patch by Kumar Gala 11 Jan 2006 |
#
c157d8e2 |
|
01-Aug-2005 |
Stefan Roese <sr@denx.de> |
Add support for AMCC PPC440EP/GR eval boards Yosemite and Yellowstone. Patch by Steven Blakeslee, 27 Jul 2005 |
#
7a8e9bed |
|
31-May-2003 |
Wolfgang Denk <wd@denx.de> |
* Patch by Marc Singer, 29 May 2003: Fixed rarp boot method for IA32 and other little-endian CPUs. * Patch by Marc Singer, 28 May 2003: Added port I/O commands. * Patch by Matthew McClintock, 28 May 2003 - cpu/mpc824x/start.S: fix relocation code when booting from RAM - minor patches for utx8245 * Patch by Daniel Engstr�m, 28 May 2003: x86 update * Patch by Dave Ellis, 9 May 2003 + 27 May 2003: add nand flash support to SXNI855T configuration fix/extend nand flash support: - fix 'nand erase' command so does not erase bad blocks - fix 'nand write' command so does not write to bad blocks - fix nand_probe() so handles no flash detected properly - add doc/README.nand - add .jffs2 and .oob options to nand read/write - add 'nand bad' command to list bad blocks - add 'clean' option to 'nand erase' to write JFFS2 clean markers - make NAND read/write faster * Patch by Rune Torgersen, 23 May 2003: Update for MPC8266ADS board |
#
c7de829c |
|
19-Nov-2002 |
Wolfgang Denk <wd@denx.de> |
* Patch by Thomas Frieden, 13 Nov 2002: Add code for AmigaOne board (preliminary merge to U-Boot, still WIP) * Patch by Jon Diekema, 12 Nov 2002: - Adding URL for IEEE OUI lookup - Making the autoboot #defines dependent on CONFIG_AUTOBOOT_KEYED being defined. - In the CONFIG_EXTRA_ENV_SETTINGS #define, the root-on-initrd and root-on-nfs macros are designed to switch how the default boot method gets defined. |
#
c609719b |
|
02-Nov-2002 |
Wolfgang Denk <wd@denx.de> |
Initial revision |
#
1fcfadcb |
|
27-Sep-2022 |
Michal Suchanek <msuchanek@suse.de> |
dm: pci: Fix doc typo first -> next pci_find_first_device description says it can be used for iteration with itself but it should really be with pci_find_next_device Signed-off-by: Michal Suchanek <msuchanek@suse.de> |
#
2635e3b5 |
|
21-Apr-2022 |
Andrew Scull <ascull@google.com> |
pci: Add mask parameter to dm_pci_map_bar() Add a mask parameter to control the lookup of the PCI region from which the mapping can be made. Signed-off-by: Andrew Scull <ascull@google.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
a822d1de |
|
21-Apr-2022 |
Andrew Scull <ascull@google.com> |
pci: Update dm_pci_bus_to_virt() parameters Add mask parameter and reorder length parameter to match the other PCI address conversion functions. Using PCI_REGION_TYPE as the mask gives the old behaviour. It's converted from a macro to an inline function as the length parameter is now used twice, but should only be calculated once. Signed-off-by: Andrew Scull <ascull@google.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
7739d93d |
|
21-Apr-2022 |
Andrew Scull <ascull@google.com> |
pci: Match region flags using a mask When converting addresses, apply a mask to the region flags during lookup. This allows the caller to specify which flags are important and which are not, for example to exclude system memory regions. The behaviour of the function is changed such that they don't preferentially search for a non-system memory region. However, system memory regions are added after other regions in decode_regions() leading to a similar outcome. Signed-off-by: Andrew Scull <ascull@google.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
12507a2d |
|
21-Apr-2022 |
Andrew Scull <ascull@google.com> |
pci: Map bars with offset and length Evolve dm_pci_map_bar() to include an offset and length parameter. These allow a portion of the memory to be mapped and range checks to be applied. Passing both the offset and length as zero results in the previous behaviour and this is used to migrate the previous callers. Signed-off-by: Andrew Scull <ascull@google.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
398dc367 |
|
21-Apr-2022 |
Andrew Scull <ascull@google.com> |
pci: Range check address conversions When converting between PCI bus and physical addresses, include a length parameter that can be used to check that the entire range fits within one of the PCI regions. This prevents an address being returned that might be only partially valid for the range it is going to be used for. Where the range check is not wanted, passing a length of 0 will have the same behaviour as before this change. Signed-off-by: Andrew Scull <ascull@google.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
60f4142a |
|
21-Apr-2022 |
Andrew Scull <ascull@google.com> |
pci: Fix use of flags in dm_pci_map_bar() The flags parameter of dm_pci_map_bar() is used for PCI region flags rather than memory mapping flags. Fix the type to match that of the region flags and stop using the regions flags as memory mapping flags. Signed-off-by: Andrew Scull <ascull@google.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
d158fa1b |
|
18-Feb-2022 |
Pali Rohár <pali@kernel.org> |
pci: Remove duplicate PCI_CLASS_CODE_* and PCI_CLASS_SUB_CODE_* macros Macros PCI_CLASS_CODE_* and PCI_CLASS_SUB_CODE_* are unused and are duplication of PCI_CLASS_* macros defined in pci_ids.h header file. So remove them. Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Stefan Roese <sr@denx.de> |
#
819a43c9 |
|
10-Feb-2022 |
Pali Rohár <pali@kernel.org> |
arm: a37xx: pci: Use standard register macros from pci.h PCI config space of the aardvark PCIe Root Port is available only in internal aardvark memory space starting at offset 0x0. PCI Express registers (PCI_EXP_*) start at offset 0xc0. And Advanced Error Reporting registers (PCI_ERR_*) start at offset 0x100. Replace custom aardvark register macros by standard PCI macros from include/pci.h file with fixed offset. Some DEVCTL and AER macros are not defined in include/pci.h file, so define them in the same way as in linux uapi header file pci_regs.h. Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Stefan Roese <sr@denx.de> |
#
185f812c |
|
19-Jan-2022 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
doc: replace @return by Return: Sphinx expects Return: and not @return to indicate a return value. find . -name '*.c' -exec \ sed -i 's/^\(\s\)\*\(\s*\)@return\(\s\)/\1*\2Return:\3/' {} \; find . -name '*.h' -exec \ sed -i 's/^\(\s\)\*\(\s*\)@return\(\s\)/\1*\2Return:\3/' {} \; Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> |
#
a398a51c |
|
20-Nov-2021 |
Maciej W. Rozycki <macro@orcam.me.uk> |
pci: Work around PCIe link training failures Attempt to handle cases with a downstream port of a PCIe switch where link training never completes and the link continues switching between speeds indefinitely with the data link layer never reaching the active state. It has been observed with a downstream port of the ASMedia ASM2824 Gen 3 switch wired to the upstream port of the Pericom PI7C9X2G304 Gen 2 switch, using a Delock Riser Card PCI Express x1 > 2 x PCIe x1 device, P/N 41433, wired to a SiFive HiFive Unmatched board. In this setup the switches are supposed to negotiate the link speed of preferably 5.0GT/s, falling back to 2.5GT/s. However the link continues oscillating between the two speeds, at the rate of 34-35 times per second, with link training reported repeatedly active ~84% of the time, e.g.: 02:03.0 PCI bridge [0604]: ASMedia Technology Inc. ASM2824 PCIe Gen3 Packet Switch [1b21:2824] (rev 01) (prog-if 00 [Normal decode]) [...] Bus: primary=02, secondary=05, subordinate=05, sec-latency=0 [...] Capabilities: [80] Express (v2) Downstream Port (Slot+), MSI 00 [...] LnkSta: Speed 5GT/s (downgraded), Width x1 (ok) TrErr- Train+ SlotClk+ DLActive- BWMgmt+ ABWMgmt- [...] LnkCtl2: Target Link Speed: 8GT/s, EnterCompliance- SpeedDis+, Selectable De-emphasis: -3.5dB Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS- Compliance De-emphasis: -6dB [...] Forcibly limiting the target link speed to 2.5GT/s with the upstream ASM2824 device makes the two switches communicate correctly however: 02:03.0 PCI bridge [0604]: ASMedia Technology Inc. ASM2824 PCIe Gen3 Packet Switch [1b21:2824] (rev 01) (prog-if 00 [Normal decode]) [...] Bus: primary=02, secondary=05, subordinate=09, sec-latency=0 [...] Capabilities: [80] Express (v2) Downstream Port (Slot+), MSI 00 [...] LnkSta: Speed 2.5GT/s (downgraded), Width x1 (ok) TrErr- Train- SlotClk+ DLActive+ BWMgmt- ABWMgmt- [...] LnkCtl2: Target Link Speed: 2.5GT/s, EnterCompliance- SpeedDis+, Selectable De-emphasis: -3.5dB Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS- Compliance De-emphasis: -6dB [...] and then: 05:00.0 PCI bridge [0604]: Pericom Semiconductor PI7C9X2G304 EL/SL PCIe2 3-Port/4-Lane Packet Switch [12d8:2304] (rev 05) (prog-if 00 [Normal decode]) [...] Bus: primary=05, secondary=06, subordinate=09, sec-latency=0 [...] Capabilities: [c0] Express (v2) Upstream Port, MSI 00 [...] LnkSta: Speed 2.5GT/s (downgraded), Width x1 (downgraded) TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt- [...] LnkCtl2: Target Link Speed: 5GT/s, EnterCompliance- SpeedDis- Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS- Compliance De-emphasis: -6dB [...] Make use of this observation then and attempt to detect the inability to negotiate the link speed automatically, and then handle it by hand. Use the Data Link Layer Link Active status flag as the primary indicator of successful link speed negotiation, but given that the flag is optional by hardware to implement (the ASM2824 does have it though), resort to checking for the mandatory Link Bandwidth Management Status flag showing that the link speed or width has been changed in an attempt to correct unreliable link operation (the ASM2824 does set it too). If these checks indicate that link may not operate correctly, then poll the Data Link Layer Link Active status flag along with the Link Training flag for the duration of 200ms to see if the link has stabilised, that is either that the Data Link Layer Link Active status flag has been set or that Link Training has been inactive during at least the second half of the interval. If that has indicated failure, restrict the target speed to 2.5GT/s, request a link retrain and check again if the link has stabilised. If that does not work either, then restore the original speed setting and claim defeat, otherwise we are done. NB interestingly enough with the ASM2824 vs PI7C9X2G304 configuration referred above asking the ASM2824 to retrain with a higher target link speed once the 2.5GT/s speed has been negotiated makes the two devices successfully negotiate 5.0GT/s. Lifting the 2.5GT/s speed restriction would however prevent our workaround from working with an OS that issues a reset and that is unaware of the problem. This is because the devices would then try to negotiate a higher link speed from scratch and fail, while the sticky property of the Target Link Speed setting will keep the 2.5GT/s speed restriction across a reset. Keep the 2.5GT/s speed restriction then, conservatively, if functional once applied. Signed-off-by: Maciej W. Rozycki <macro@orcam.me.uk> Reviewed-by: Stefan Roese <sr@denx.de> |
#
2a8d4025 |
|
26-Nov-2021 |
Pali Rohár <pali@kernel.org> |
pci: Add standard PCI Config Address macros Lot of PCI and PCIe controllers are using standard Config Address for PCI Configuration Mechanism #1 or its extended version. So add PCI_CONF1_ADDRESS() and PCI_CONF1_EXT_ADDRESS() macros into U-Boot's pci.h header file which can be suitable for most PCI and PCIe controller drivers. Drivers do not have to invent their own macros and can use these new U-Boot macros. Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
a4bc38da |
|
02-Nov-2021 |
Pali Rohár <pali@kernel.org> |
pci: Add standard PCIe ECAM macros Lot of PCIe controllers are using ECAM addressing. So add common ECAM macros into U-Boot's pci.h header file which can be suitable for most PCI controller drivers. Replace custom ECAM address macros in every PCI controller driver by new ECAM macros from U-Boot's pci.h header file. Similar macros are defined also in Linux kernel. There is a small difference between Linux and these new U-Boot macros. U-Boot's PCIE_ECAM_OFFSET() takes device and function numbers in separate arguments. Linux's PCIE_ECAM_OFFSET() takes device and function numbers encoded in one argument. The reason is that U-Boot's PCI_DEVFN() macro is different than Linux's PCI_SLOT() macro. So having device and function numbers in separate arguments makes code more straightforward. Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Stefan Roese <sr@denx.de> |
#
1d7ad685 |
|
25-Sep-2021 |
Pali Rohár <pali@kernel.org> |
arm: a37xx: pci: Handle propagation of CRSSVE bit from PCIe Root Port Now that PCI Bridge (PCIe Root Port) for Aardvark is emulated in U-Boot, add support for handling and propagation of CRSSVE bit. When CRSSVE bit is unset (default), driver has to reissue config read/write request on CRS response. CRSSVE bit is supported only when CRSVIS bit is provided in read-only Root Capabilities register. So manually inject this CRSVIS bit into read response for that register. Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Stefan Roese <sr@denx.de> |
#
2649f69f |
|
17-Sep-2021 |
Vladimir Oltean <vladimir.oltean@nxp.com> |
pci: provide prototype for pci_skip_dev outside of #if defined(CONFIG_DM_PCI_COMPAT) The weak definition of pci_skip_dev from drivers/pci/pci_common.c is not under CONFIG_DM_PCI_COMPAT, and that definition needs a previous function prototype declaration to avoid W=1 build warnings. That prototype is not available due to it being under CONFIG_DM_PCI_COMPAT, so move it outside of that preprocessor block. Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
23cacd57 |
|
01-Aug-2021 |
Simon Glass <sjg@chromium.org> |
pci: Drop PCI_INDIRECT_BRIDGE This does not work with driver model so can be removed. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
26543cc6 |
|
01-Aug-2021 |
Simon Glass <sjg@chromium.org> |
pci: Drop old code from header file We don't need this code anymore since when PCI is enabled, driver model is always used. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
63814a69 |
|
01-Aug-2021 |
Simon Glass <sjg@chromium.org> |
pci: imx: Drop DM_PCI check from cpu driver We don't need this check anymore since when PCI is enabled, driver model is always used. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
e8c09d69 |
|
01-Aug-2021 |
Simon Glass <sjg@chromium.org> |
pci: Remove guard around compatibility functions This prevents use of IS_ENABLED() in other files. Functions should be visible in headers even if they are not available at link time. Fix it. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
f5cbb5c7 |
|
27-Jun-2021 |
Simon Glass <sjg@chromium.org> |
x86: pci: Allow binding of some devices before relocation At present only bridge devices are bound before relocation, to save space in pre-relocation memory. In some cases we do actually want to bind a device, e.g. because it provides the console UART. Add a devicetree binding to support this. Use the PCI_VENDEV() macro to encode the cell value. This is present in U-Boot but not used, so move it to the binding header-file. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
e58f3a7d |
|
27-Jun-2021 |
Simon Glass <sjg@chromium.org> |
pci: Use const for pci_find_device_id() etc. These functions don't modify the device-ID struct that is passed in, so mark the argument as const, so the data structure can be declared that way. This allows it to be placed in the rodata section. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
c7b36007 |
|
14-May-2021 |
Tom Rini <trini@konsulko.com> |
pci: Remove non-DM board_pci_fixup_dev() declaration With the ventana boards migrated to DM_PCI and DM_ETH, we can remove this prototype. Cc: Stefano Babic <sbabic@denx.de> Signed-off-by: Tom Rini <trini@konsulko.com> |
#
cecd013f |
|
16-Apr-2021 |
Tim Harvey <tharvey@gateworks.com> |
pci: pci-uclass: Add board_pci_fixup_dev for DM_PCI Add a board_pci_fixup_dev weak function to allow PCI device fixups during enumeration. Signed-off-by: Tim Harvey <tharvey@gateworks.com> |
#
8b85dfc6 |
|
16-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: Avoid accessing seq directly At present various drivers etc. access the device's 'seq' member directly. This makes it harder to change the meaning of that member. Change access to go through a function instead. The drivers/i2c/lpc32xx_i2c.c file is left unchanged for now. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
caa4daa2 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename 'platdata' variables to just 'plat' We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
284d062e |
|
09-Sep-2020 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
pci: add a few ARI related defines Add a few defines related to PCI ARI configuration. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
51eeae91 |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add VF BAR map support for Enhanced Allocation Makes dm_pci_map_bar API available to map BAR for Virtual function PCI devices which support Enhanced Allocation. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> |
#
b8852dcf |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add support for Single-Root I/O Virtualization SR-IOV - Single Root I/O Virtualization PF - Physical Function VF - Virtual Function If SR-IOV capability is present, use it to initialize Virtual Function PCI device instances. pci_sriov_init function will read SR-IOV registers to create VF devices under the PF PCI device and also bind driver if available. This function needs to be invoked from Physical function device driver which expects VF device support, creating minimal impact on existing framework. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> |
#
e0024741 |
|
23-Jul-2020 |
Stefan Roese <sr@denx.de> |
pci: pci-uclass: Dynamically allocate the PCI regions Instead of using a fixed length pre-allocated array of regions, this patch moves to dynamically allocating the regions based on the number of available regions plus the necessary regions for DRAM banks. Since MAX_PCI_REGIONS is not needed any more, its removed completely with this patch. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Thierry Reding <treding@nvidia.com> Cc: Marek Vasut <marek.vasut+renesas@gmail.com> |
#
143eb5b1 |
|
12-May-2020 |
Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
drivers: pci: add api to get dma regions Add api to get dma regions. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com> |
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com> |
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com> |
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
7d994067 |
|
23-Apr-2019 |
Tom Rini <trini@konsulko.com> |
Merge tag 'pull-24apr19' of git://git.denx.de/u-boot-dm Various minor sandbox iumprovements Fixes for tracing with sandbox Refactoring for boot_get_fdt()
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
a8c5f8d3 |
|
15-Oct-2018 |
Bin Meng <bmeng.cn@gmail.com> |
dm: pci: Add APIs to find next capability and extended capability This introduces two new APIs dm_pci_find_next_capability() and dm_pci_find_next_ext_capability() to get PCI capability address and PCI express extended capability address for a given PCI device starting from a given offset. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
dac01fd8 |
|
03-Aug-2018 |
Bin Meng <bmeng.cn@gmail.com> |
dm: pci: Add APIs to find capability and extended capability This introduces two new APIs dm_pci_find_capability() and dm_pci_find_ext_capability() to get PCI capability address and PCI express extended capability address for a given PCI device. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
5d544f96 |
|
03-Aug-2018 |
Bin Meng <bmeng.cn@gmail.com> |
pci: Add all known capability and extended capability ids Currently we don't have a complete list of capability and extended capability ids. This adds them. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
4345998a |
|
03-Aug-2018 |
Bin Meng <bmeng.cn@gmail.com> |
pci: sandbox: Support dynamically binding device driver At present all emulated sandbox pci devices must be present in the device tree in order to be used. The real world pci uclass driver supports pci device driver matching, and we should add such support on sandbox too. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
01259c93 |
|
03-Aug-2018 |
Bin Meng <bmeng.cn@gmail.com> |
pci: Remove 440ep-specific macros These macros should not be put in the generic pci.h header file. Since they are not referenced anywhere, remove them completely. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
5ce9aca8 |
|
14-May-2018 |
Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi> |
PCI: Document pciauto_region_allocate() Add a doc comment for pciauto_region_allocate(). Signed-off-by: Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
d71975ae |
|
14-May-2018 |
Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi> |
PCI: autoconfig: Don't allocate 64-bit addresses to 32-bit only resources Currently, if we happen to allocate an address requiring 64 bits to a device only supporting 32-bit BARs, the address eventually gets silently truncated to 32 bits. Avoid this by adding a new flag to pciauto_region_allocate() to bail out in such situations. Signed-off-by: Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
83d290c5 |
|
06-May-2018 |
Tom Rini <trini@konsulko.com> |
SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com> |
#
ed68ccbf |
|
13-Mar-2018 |
Stefan Roese <sr@denx.de> |
pci: Remove unused ppc4xx variable from struct pci_controller ppc4xx support was removed some time ago. Lets remove the now unused "pci_fb" variable from "struct pci_controller" as well. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Simon Glass <sjg@chromium.org> |
#
badb9922 |
|
19-Sep-2017 |
Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi> |
pci: Add helper for implementing memory-mapped config space accesses This sort of pattern for implementing memory-mapped PCI config space accesses appears in U-Boot twice already, and a third user is coming up. So add helper functions to avoid code duplication, similar to how Linux has pci_generic_config_write and pci_generic_config_read. Signed-off-by: Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
6ecbe137 |
|
12-May-2017 |
Tim Harvey <tharvey@gateworks.com> |
drivers: pci: imx: add imx_pcie_remove function There is no dedicated reset signal wired up for the MX6QDL thus if the bootloader enables the link we need some special handling to get the core back into a state where it is safe to touch it for configuration. While there has been some special handling in the Linux kernel to do this, it was removed in 4.11 thus we need to do it properly in the bootloader and therefore without this if you enable PCI in the bootloader you will hang while booting the 4.11 kernel. This puts the PCIe controller back into a safe state for the kernel driver before launching the kernel. Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com> Tested-by: Peter Senna Tschudin <peter.senna@collabora.com> |
#
eeb5b1ad |
|
10-Mar-2016 |
Stuart Yoder <stuart.yoder@nxp.com> |
pci: make pci_get_hose_head() available to external users Put pci_get_hose_head() prototype in header so it is available to external users, allowing them to find and iterate over all pci controllers. Signed-off-by: Stuart Yoder <stuart.yoder@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
4974a6ff |
|
06-Mar-2016 |
Simon Glass <sjg@chromium.org> |
pci: Correct a few comments and nits Two comments are missing a parameter and there is an extra blank line. Also two of the region access macros are misnamed. Correct these problems. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
319dba1f |
|
06-Mar-2016 |
Simon Glass <sjg@chromium.org> |
pci: Add functions to update PCI configuration registers It is common to read a config register value, clear and set some bits, then write back the updated value. Add functions to do this in one step, for convenience. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
308143ef |
|
02-Feb-2016 |
Bin Meng <bmeng.cn@gmail.com> |
dm: pci: Add missing forward declarations When CONFIG_DM_PCI_COMPAT is not on, there is only a forward declaration for pci_write_config32(). Add other missing ones. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
9d731c82 |
|
18-Jan-2016 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to write a BAR Add a driver-model version of the pci_write_bar32 function so that this is supported in the new API. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
7e78b9ef |
|
29-Nov-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Switch to DM API for PCI address mapping We should use the new address mapping functions unless we are in compatibility mode. Disable the old functions by default. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
21d1fe7e |
|
29-Nov-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add driver model API functions for address mapping At present the PCI address map functions use the old API. Add new functions for this so that drivers can be converted. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
bab17cf1 |
|
29-Nov-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR Add a driver-model function for reading the PCI BAR from a device. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
a0eb8356 |
|
29-Nov-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a driver-model version of pci_find_class() Add a function which scans the driver model device information rather than scanning the PCI bus again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> |
#
5c0bf647 |
|
29-Nov-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a driver-model version of pci_find_device() Add a function which scans the driver model device information rather than scanning the PCI bus again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> |
#
5e23b8b4 |
|
29-Nov-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Use driver model PCI API in auto-config At present we are using legacy functions even in the auto-configuration code used by driver model. Add a new pci_auto.c version which uses the correct API. Create a new pci_internal.h header to hold functions that are used within the PCI subsystem, but are not exported to other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> |
#
f3f1faef |
|
29-Nov-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a dm_ prefix to pci_bus_find_bdf() Most driver model PCI functions have a dm_ prefix. At some point, when the old code is converted to driver model and the old functions are removed, we will drop that prefix. For consistency, we should use the dm_ prefix for all driver model functions. Update pci_bus_find_bdf() accordingly. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
21ccce1b |
|
29-Nov-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a dm_ prefix to pci_get_bdf() Most driver model PCI functions have a dm_ prefix. At some point, when the old code is converted to driver model and the old functions are removed, we will drop that prefix. For consistency, we should use the dm_ prefix for all driver model functions. Update pci_get_bdf() accordingly. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
3ba5f74a |
|
26-Nov-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Disable PCI compatibility functions by default We eventually need to drop the compatibility functions for driver model. As a first step, create a configuration option to enable them and hide them when the option is disabled. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
54fe7b1c |
|
26-Nov-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a comment about how to find struct pci_controller With driver mode, struct pci_controller is stored as uclass-private data. Add a comment to that effect. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
f9260336 |
|
19-Nov-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to find the regions for a PCI bus This function looks up the controller and returns a pointer to each region type. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Stephen Warren <swarren@nvidia.com> Tested-by: Stephen Warren <swarren@nvidia.com> |
#
9f60fb0d |
|
19-Nov-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to get the controller for a bus A PCI bus may be a bridge device where the controller is the bridge's parent. Add a function to return the controller device, given a PCI device. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Stephen Warren <swarren@nvidia.com> Tested-by: Stephen Warren <swarren@nvidia.com> |
#
9289db6c |
|
19-Nov-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add functions to emulate 8- and 16-bit access Provide a few functions to support using 32-bit access to emulate 8- and 16-bit access. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Stephen Warren <swarren@nvidia.com> Tested-by: Stephen Warren <swarren@nvidia.com> |
#
bcbe3d15 |
|
28-Sep-2015 |
Simon Glass <sjg@chromium.org> |
dm: Rename dev_get_parentdata() to dev_get_parent_priv() The current name is inconsistent with other driver model data access functions. Rename it and fix up all users. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Joe Hershberger <joe.hershberger@ni.com> |
#
dc5740df |
|
22-Aug-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a comment to help find pci_hose_read_config_byte, etc. These functions are defined by macros so do not show up with grep. Add a comment to help. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
76c3fbcd |
|
10-Aug-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a way to iterate through all PCI devices These functions allow iteration through all PCI devices including bridges. The children of each PCI bus are returned in turn. This can be useful for configuring, checking or enumerating all the devices. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
66afb4ed |
|
10-Aug-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Provide friendly config access functions At present there are no PCI functions which allow access to PCI configuration using a struct udevice. This is a sad situation for driver model as it makes use of PCI harder. Add these functions. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
5f48d798 |
|
27-Jul-2015 |
Simon Glass <sjg@chromium.org> |
pci: Add a constant for an invalid interrupt Rather than using 0xff in the code, add a constant. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
ed5b580b |
|
09-Jul-2015 |
Minghuan Lian <Minghuan.Lian@freescale.com> |
drivers/pci: Add function to find an extended capability PCIe extends device's configuration space to 4k and provides extended capability. The patch adds function to find them. The code is ported from Linux PCIe driver. Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
4b515e4f |
|
06-Jul-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to get the BDF for a device It is useful to be able to find the full PCI address (bus, device and function) for a PCI device. Add a function to provide this. Adjust the existing code to use this. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
aba92962 |
|
06-Jul-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add support for PCI driver matching At present all PCI devices must be present in the device tree in order to be used. Many or most PCI devices don't require any configuration other than that which is done automatically by U-Boot. It is inefficent to add a node with nothing but a compatible string in order to get a device working. Add a mechanism whereby PCI drivers can be declared along with the device parameters they support (vendor/device/class). When no suitable driver is found in the device tree the list of such devices is consulted to determine the correct driver. If this also fails, then a generic driver is used as before. The mechanism used is very similar to that provided by Linux and the header file defintions are copied from Linux 4.1. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Joe Hershberger <joe.hershberger@ni.com> |
#
6c89663c |
|
07-Jul-2015 |
Bin Meng <bmeng.cn@gmail.com> |
pci: Configure expansion ROM during auto config process Currently PCI expansion ROM address is assigned by a call to pciauto_setup_rom() outside of the pci auto config process. This does not work when expansion ROM is on a device behind PCI bridge where bridge's memory limit register was already programmed to a value that does not cover the newly assigned expansion ROM address. To fix this, we should configure the ROM address during the auto config process. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Acked-by: Simon Glass <sjg@chromium.org> |
#
aec241df |
|
07-Jun-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Use the correct hose when configuring devices Only the PCI controller has access to the PCI region information. Make sure to use the controller (rather than any attached bridges) when configuring devices. This corrects a failure to scan and configure devices when driver model is enabled for PCI. Also add a comment to explain the problem. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
36d0d3b4 |
|
05-Mar-2015 |
Simon Glass <sjg@chromium.org> |
dm: sandbox: pci: Add a PCI emulation uclass Since sandbox does not have real devices (unless it borrows those from the host) it must use emulations. Provide a uclass which permits PCI operations to be passed through to an emulation device. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
ff3e077b |
|
05-Mar-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a uclass for PCI Add a uclass for PCI controllers and a generic one for PCI devices. Adjust the 'pci' command and the existing PCI support to work with this new uclass. Keep most of the compatibility code in a separate file so that it can be removed one day. TODO: Add more header file comments to the new parts of pci.h Signed-off-by: Simon Glass <sjg@chromium.org> |
#
aab6724c |
|
05-Mar-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move common PCI functions into their own file Driver model will share many functions with the existing PCI implementation. Move these into their own file to avoid duplication and confusion. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
250e039d |
|
27-Jan-2015 |
Simon Glass <sjg@chromium.org> |
pci: Add a function to find a device by class There is an existing function prototype in the header file but it is not implemented. Implement something similar. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
4a2708a0 |
|
14-Jan-2015 |
Simon Glass <sjg@chromium.org> |
x86: Access the VGA ROM when needed Add code to the generic pci_rom file to access the VGA ROM in PCI space when needed. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
d622ac39 |
|
15-Dec-2014 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
powerpc: mpc824x: remove MPC824X cpu support All the MPC824X boards are still non-generic boards: A3000, CPC45, CU824, eXalion, MVBLUE, MUSENKI, Sandpoint824x, utx8245 Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Josef Wagner <Wagner@Microsys.de> Cc: Torsten Demke <torsten.demke@fci.com> Cc: Jim Thompson <jim@musenki.com> Cc: Greg Allen <gallen@arlut.utexas.edu> |
#
e8a552eb |
|
14-Nov-2014 |
Simon Glass <sjg@chromium.org> |
pci: Add functions to read and write a BAR address Some PCI functions cannot be auto-configured. Add a function to set up a fixed BAR which can be used in these situations. Also add a function to read the current address of a BAR. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
4efe52bf |
|
12-Nov-2014 |
Thierry Reding <treding@nvidia.com> |
pci: Honour pci_skip_dev() When enumerating devices, honour the pci_skip_dev() function. This can be used by PCI controller drivers to restrict which devices will be probed. This is required by the NVIDIA Tegra PCIe controller driver, which will fail with a data abort exception if an access is attempted to a device number larger than 0 outside of bus 0. pci_skip_dev() is therefore implemented to prevent any such accesses. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Simon Glass <sjg@chromium.org> |
#
0991866c |
|
07-Aug-2014 |
Tim Harvey <tharvey@gateworks.com> |
pci: add support for board_pci_fixup_dev function Some board-level drivers may wish to have per-device fixup functions for PCI devices. Signed-off-by: Tim Harvey <tharvey@gateworks.com> |
#
fa5cec03 |
|
08-Nov-2013 |
Paul Burton <paul.burton@mips.com> |
pci.h: allow inclusion in assembly source This patch simply #ifdef's out the C-specific parts of pci.h when it is included by an assembly file. This will allow the macros it contains to be used from assembly source as will be done in a followup commit adding support for more modern MIPS Malta boards. Signed-off-by: Paul Burton <paul.burton@imgtec.com> |
#
287df01e |
|
11-Oct-2013 |
Zhao Qiang <B45475@freescale.com> |
PCIe:change the method to get the address of a requested capability in configuration space. Previously, the address of a requested capability is define like that "#define PCI_DCR 0x78" But, the addresses of capabilities is different with regard to PCIe revs. So this method is not flexible. Now a function to get the address of a requested capability is added and used. It can get the address dynamically by capability ID. The step of this function: 1. Read Status register in PCIe configuration space to confirm that Capabilities List is valid. 2. Find the address of Capabilities Pointer Register. 3. Find the address of requested capability from the first capability. Signed-off-by: Zhao Qiang <B45475@freescale.com> |
#
7b4e5844 |
|
03-Jul-2013 |
Zang Roy-R61911 <tie-fei.zang@freescale.com> |
powerpc/pcie: add PCIe version 3.x support T4240 PCIe IP is version 3.0 and has some update comparing previous QorIQ products. 1. Move Freescale specific register define to arch/powerpc/include/asm/fsl_pci.h and update the register offset define for T4240. 2. add the status/control register define use status/control register to judge the link status 3. The original code uses 'Programming Interface' field to judge if PCIE is EP or RC mode, however, T4240 does not support this functionality. According to PCIE specification, 'Header Type' offset 0x0e is used to indicate header type, so for PCIE controller, the patch changes code to use 'Header Type' field to identify if the PCIE is RC or EP mode. This patch fixes the PCIe card link up issue on T4240QDS. Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com> |
#
1a459660 |
|
08-Jul-2013 |
Wolfgang Denk <wd@denx.de> |
Add GPL-2.0+ SPDX-License-Identifier to source files Signed-off-by: Wolfgang Denk <wd@denx.de> [trini: Fixup common/cmd_io.c] Signed-off-by: Tom Rini <trini@ti.com> |
#
bc3442aa |
|
11-Jun-2013 |
Simon Glass <sjg@chromium.org> |
pci: Convert extern inline functions to static inline I am not sure of the meaning of extern inline, but this gives errors when building with function instrumenting enabled. Change these functions to static inline. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
842033e6 |
|
30-May-2013 |
Gabor Juhos <juhosg@openwrt.org> |
pci: introduce CONFIG_PCI_INDIRECT_BRIDGE option The pci_indirect.c file is always compiled when CONFIG_PCI is defined although the indirect PCI bridge support is not needed by every board. Introduce a new CONFIG_PCI_INDIRECT_BRIDGE config option and only compile indirect PCI bridge support if this options is enabled. Also add the new option into the configuration files of the boards which needs that. Compile tested for powerpc, x86, arm and nds32. MAKEALL results: powerpc: --------------------- SUMMARY ---------------------------- Boards compiled: 641 Boards with warnings but no errors: 2 ( ELPPC MPC8323ERDB ) ---------------------------------------------------------- Note: the warnings for ELPPC and MPC8323ERDB are present even without the actual patch. x86: --------------------- SUMMARY ---------------------------- Boards compiled: 1 ---------------------------------------------------------- arm: --------------------- SUMMARY ---------------------------- Boards compiled: 311 ---------------------------------------------------------- nds32: --------------------- SUMMARY ---------------------------- Boards compiled: 3 ---------------------------------------------------------- Cc: Tom Rini <trini@ti.com> Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com> Signed-off-by: Gabor Juhos <juhosg@openwrt.org> |
#
55ae10f8 |
|
20-Oct-2012 |
Bill Richardson <wfrichar@chromium.org> |
x86: gpio: Add GPIO driver for Intel ICH6 and later. Implement <asm-generic/gpio.h> functions for Intel ICH6 and later. Only GPIOs 0-31 are handled by this code. Signed-off-by: Bill Richardson <wfrichar@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org> |
#
a3a70725 |
|
24-Mar-2012 |
Linus Walleij <linus.walleij@linaro.org> |
pci: declare pciauto functions in header The FSL PCI driver uses local prototypes for pciauto_[pre|post]scan_setup_bridge(), this does not seem right, so move them to the <pci.h> file. Fixed a small extern declaration too, this is harmless but distracts the view since all other prototypes are explicitly external. Signed-off-by: Linus Walleij <linus.walleij@linaro.org> |
#
a1e47b66 |
|
03-Mar-2012 |
Linus Walleij <linus.walleij@linaro.org> |
pci: move pciauto_config_init() to pci.h Fixing build regressions for the Integrator I get find that a few boards try to work around the missing declaration of pciauto_config_init() by declaring it in the local scope. This does not make sense when the sibling functions are in <pci.h> so move the function to the header, ridding the build error in the Integrator and getting rid of the local declarations here and there. Reported-by: Wolfgang Denk <wd@denx.de> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> |
#
b03a466d |
|
01-Feb-2011 |
Prabhakar Kushwaha <prabhakar@freescale.com> |
powerpc/85xx: Handle PCIe initialization requires for P1021 class SoCs The P1011, P1012, P1015, P1016, P1020, P1021, P1024, & P1025 SoCs require that we initialize the SERDES registers if the lanes are configured for PCIe. Additionally these devices PCIe controller do not support ASPM and we have to explicitly disable it. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
10fa8d7c |
|
19-Jan-2011 |
Leo Liu <liucai.lfn@gmail.com> |
mpc83xx: fix pcie configuration space read/write This patch fix a problem for the pcie enumeration when the mpc83xx pcie controller is connected with switch or we use both of the two pcie controller. Signed-off-by: Leo Liu <liucai.lfn@gmail.com> fix codingstyle and compiler warning: 'pcie_priv' defined but not used Signed-off-by: Kim Phillips <kim.phillips@freescale.com> |
#
3a0e3c27 |
|
17-Dec-2010 |
Kumar Gala <galak@kernel.crashing.org> |
powerpc/fsl-pci: Determine pci_controller based on cfg addr for dts fixup Previously we passed in a specifically named struct pci_controller to determine if we had setup the particular PCI bus. Now we can search for the struct so we dont have to depend on the name or the struct being statically allocated. Introduced new find_hose_by_cfg_addr() to get back a pci_controller struct back by searching for it means we can do things like dynamically allocate them or not have to expose the static structures to all users. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Wolfgang Denk <wd@denx.de> |
#
983eb9d1 |
|
29-Oct-2010 |
Peter Tyser <ptyser@xes-inc.com> |
pci: Clean up PCI info when CONFIG_PCI_SCAN_SHOW This change does the following: - Removes the printing of the PCI interrupt line value. This is normally set to 0 by U-Boot on bootup and is rarely used during everyday operation. - Prints out the PCI function number of a device. Previously a device with multiple functions would be printed identically 2 times, which is generally confusing. For example, on an Intel 2 port gigabit Ethernet card the following was displayed: ... 04 01 8086 1010 0200 00 04 01 8086 1010 0200 00 ... - Prints a text description of each device's PCI class instead of the raw PCI class code. The textual description makes it much easier to determine what devices are installed on a PCI bus. - Changes the general formatting of the PCI device output. Previous output: PCIE1: connected as Root Complex 04 01 8086 1010 0200 00 04 01 8086 1010 0200 00 03 00 10b5 8112 0604 00 02 01 10b5 8518 0604 00 02 02 10b5 8518 0604 00 08 00 1957 0040 0b20 00 07 00 10b5 8518 0604 00 09 00 10b5 8112 0604 00 07 01 10b5 8518 0604 00 07 02 10b5 8518 0604 00 06 00 10b5 8518 0604 00 02 03 10b5 8518 0604 00 01 00 10b5 8518 0604 00 PCIE1: Bus 00 - 0b PCIE2: connected as Root Complex 0d 00 1957 0040 0b20 00 PCIE2: Bus 0c - 0d Updated output: PCIE1: connected as Root Complex 04:01.0 - 8086:1010 - Network controller 04:01.1 - 8086:1010 - Network controller 03:00.0 - 10b5:8112 - Bridge device 02:01.0 - 10b5:8518 - Bridge device 02:02.0 - 10b5:8518 - Bridge device 08:00.0 - 1957:0040 - Processor 07:00.0 - 10b5:8518 - Bridge device 09:00.0 - 10b5:8112 - Bridge device 07:01.0 - 10b5:8518 - Bridge device 07:02.0 - 10b5:8518 - Bridge device 06:00.0 - 10b5:8518 - Bridge device 02:03.0 - 10b5:8518 - Bridge device 01:00.0 - 10b5:8518 - Bridge device PCIE1: Bus 00 - 0b PCIE2: connected as Root Complex 0d:00.0 - 1957:0040 - Processor PCIE2: Bus 0c - 0d Signed-off-by: Peter Tyser <ptyser@xes-inc.com> |
#
8295b944 |
|
05-Aug-2009 |
Kumar Gala <galak@kernel.crashing.org> |
pci/fsl_pci_init: Use PCIe capability to determine if controller is PCIe Change the code to use the PCIe capabilities register to determine if we are a PCIe controller or not. Additionally cleaned up some white space and formatting in the file. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
cc2a8c77 |
|
19-Feb-2009 |
Anton Vorontsov <avorontsov@ru.mvista.com> |
PCI: Add pci_last_busno() helper This is just a handy routine that reports last PCI busno: we walk down all the hoses and return last hose's last_busno. Will be used by PCI/PCIe initialization code. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com> |
#
6e61fae4 |
|
03-Feb-2009 |
Becky Bruce <beckyb@kernel.crashing.org> |
drivers/pci: Create pci_map_bar function It is no longer always true that the pci bus address can be used as the virtual address for pci accesses. pci_map_bar() is created to return the virtual address for a pci region. Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org> |
#
ff4e66e9 |
|
06-Feb-2009 |
Kumar Gala <galak@kernel.crashing.org> |
pci: Rename PCI_REGION_MEMORY to PCI_REGION_SYS_MEMORY for clarity The PCI_REGION_MEMORY and PCI_REGION_MEM are a bit to similar and can be confusing when reading the code. Rename PCI_REGION_MEMORY to PCI_REGION_SYS_MEMORY to clarify its used for system memory mapping purposes. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
fd6646c0 |
|
07-Jan-2009 |
Anton Vorontsov <avorontsov@ru.mvista.com> |
mpc83xx: Add support for MPC83xx PCI-E controllers This patch adds support for MPC83xx PCI-E controllers in Root Complex mode. The patch is based on Tony Li and Dave Liu work[1]. Though unlike the original patch, by default we don't register PCI-E buses for use in U-Boot, we only configure the controllers for future use in other OSes (Linux). This is done because we don't have enough of spare BATs to map all the PCI-E regions. To actually use PCI-E in U-Boot, users should explicitly define CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES symbol in the board file. And only then U-Boot will able to access PCI-E, but at the cost of disabled address translation. [1] http://lists.denx.de/pipermail/u-boot/2008-January/027630.html Signed-off-by: Tony Li <tony.li@freescale.com> Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Acked-by: Dave Liu <daveliu@freescale.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com> |
#
30e76d5e |
|
21-Oct-2008 |
Kumar Gala <galak@kernel.crashing.org> |
pci: Allow for PCI addresses to be 64-bit PCI bus is inherently 64-bit. While not all system require access to the full 64-bit PCI address range some do. This allows those systems to enable the full PCI address width via CONFIG_SYS_PCI_64BIT. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Andrew Fleming-AFLEMING <afleming@freescale.com> Acked-by: Wolfgang Denk <wd@denx.de> |
#
36f32675 |
|
07-May-2008 |
Becky Bruce <bgill@freescale.com> |
Update pci code to use phys_addr_t Physical addrs need to be represented by phys_addr_t, not unsigned long. Otherwise, systems that use CONFIG_PHYS_64BIT are going to fail mightily. Signed-off-by: Becky Bruce <becky.bruce@freescale.com> |
#
63cec581 |
|
02-Aug-2007 |
Ed Swarthout <Ed.Swarthout@freescale.com> |
Make MPC8641's PCI/PCI-E driver a common driver for many FSL parts. All of the PCI/PCI-Express driver and initialization code that was in the MPC8641HPCN port has now been moved into the common drivers/fsl_pci_init.c. In a subsequent patch, this will be utilized by the 85xx ports as well. Common PCI-E IMMAP register blocks for FSL 85xx/86xx are added. Also enable the second PCI-Express controller on 8641 by getting its BATS and CFG_ setup right. Fixed a u16 vendor compiler warning in AHCI driver too. Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com> Signed-off-by: Zhang Wei <wei.zhang@freescale.com> Signed-off-by: Jon Loeliger <jdl@freescale.com> |
#
13a7fcdf |
|
19-Oct-2006 |
Jon Loeliger <jdl@freescale.com> |
* Fix a bunch of compiler warnings for gcc 4.0 Signed-off-by: Matthew McClintock <msm@freescale.com> |
#
f0e6f57f |
|
28-Jun-2006 |
Matthew McClintock <msm@freescale.com> |
* Added PCI-X #defines for PCI-X initialization Patch by Andy Fleming on 17-Mar-2006 Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
7b230f61 |
|
12-Mar-2006 |
Wolfgang Denk <wd@denx.de> |
Merge with git://git.kernel.org/pub/scm/boot/u-boot/u-boot.git#pci
|
#
993a2275 |
|
12-Mar-2006 |
Wolfgang Denk <wd@denx.de> |
Fix bad declaration on pci_cfgfunc_nothing Patch by Sam Song, 19 Jun 2005 |
#
a179012e |
|
11-Jan-2006 |
Kumar Gala <galak@kernel.crashing.org> |
Added support for PCI prefetchable region and BARs If a host controller sets up a region as prefetchable and a device's BAR denotes it as prefetchable, allocate the BAR into the prefetch region. If a BAR is prefetchable and no prefetchable region has been setup by the controller we fall back to allocating the BAR into the normally memory region. Patch by Kumar Gala 11 Jan 2006 |
#
c157d8e2 |
|
01-Aug-2005 |
Stefan Roese <sr@denx.de> |
Add support for AMCC PPC440EP/GR eval boards Yosemite and Yellowstone. Patch by Steven Blakeslee, 27 Jul 2005 |
#
7a8e9bed |
|
31-May-2003 |
Wolfgang Denk <wd@denx.de> |
* Patch by Marc Singer, 29 May 2003: Fixed rarp boot method for IA32 and other little-endian CPUs. * Patch by Marc Singer, 28 May 2003: Added port I/O commands. * Patch by Matthew McClintock, 28 May 2003 - cpu/mpc824x/start.S: fix relocation code when booting from RAM - minor patches for utx8245 * Patch by Daniel Engstr�m, 28 May 2003: x86 update * Patch by Dave Ellis, 9 May 2003 + 27 May 2003: add nand flash support to SXNI855T configuration fix/extend nand flash support: - fix 'nand erase' command so does not erase bad blocks - fix 'nand write' command so does not write to bad blocks - fix nand_probe() so handles no flash detected properly - add doc/README.nand - add .jffs2 and .oob options to nand read/write - add 'nand bad' command to list bad blocks - add 'clean' option to 'nand erase' to write JFFS2 clean markers - make NAND read/write faster * Patch by Rune Torgersen, 23 May 2003: Update for MPC8266ADS board |
#
c7de829c |
|
19-Nov-2002 |
Wolfgang Denk <wd@denx.de> |
* Patch by Thomas Frieden, 13 Nov 2002: Add code for AmigaOne board (preliminary merge to U-Boot, still WIP) * Patch by Jon Diekema, 12 Nov 2002: - Adding URL for IEEE OUI lookup - Making the autoboot #defines dependent on CONFIG_AUTOBOOT_KEYED being defined. - In the CONFIG_EXTRA_ENV_SETTINGS #define, the root-on-initrd and root-on-nfs macros are designed to switch how the default boot method gets defined. |
#
c609719b |
|
02-Nov-2002 |
Wolfgang Denk <wd@denx.de> |
Initial revision |
#
2635e3b5 |
|
21-Apr-2022 |
Andrew Scull <ascull@google.com> |
pci: Add mask parameter to dm_pci_map_bar() Add a mask parameter to control the lookup of the PCI region from which the mapping can be made. Signed-off-by: Andrew Scull <ascull@google.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
a822d1de |
|
21-Apr-2022 |
Andrew Scull <ascull@google.com> |
pci: Update dm_pci_bus_to_virt() parameters Add mask parameter and reorder length parameter to match the other PCI address conversion functions. Using PCI_REGION_TYPE as the mask gives the old behaviour. It's converted from a macro to an inline function as the length parameter is now used twice, but should only be calculated once. Signed-off-by: Andrew Scull <ascull@google.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
7739d93d |
|
21-Apr-2022 |
Andrew Scull <ascull@google.com> |
pci: Match region flags using a mask When converting addresses, apply a mask to the region flags during lookup. This allows the caller to specify which flags are important and which are not, for example to exclude system memory regions. The behaviour of the function is changed such that they don't preferentially search for a non-system memory region. However, system memory regions are added after other regions in decode_regions() leading to a similar outcome. Signed-off-by: Andrew Scull <ascull@google.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
12507a2d |
|
21-Apr-2022 |
Andrew Scull <ascull@google.com> |
pci: Map bars with offset and length Evolve dm_pci_map_bar() to include an offset and length parameter. These allow a portion of the memory to be mapped and range checks to be applied. Passing both the offset and length as zero results in the previous behaviour and this is used to migrate the previous callers. Signed-off-by: Andrew Scull <ascull@google.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
398dc367 |
|
21-Apr-2022 |
Andrew Scull <ascull@google.com> |
pci: Range check address conversions When converting between PCI bus and physical addresses, include a length parameter that can be used to check that the entire range fits within one of the PCI regions. This prevents an address being returned that might be only partially valid for the range it is going to be used for. Where the range check is not wanted, passing a length of 0 will have the same behaviour as before this change. Signed-off-by: Andrew Scull <ascull@google.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
60f4142a |
|
21-Apr-2022 |
Andrew Scull <ascull@google.com> |
pci: Fix use of flags in dm_pci_map_bar() The flags parameter of dm_pci_map_bar() is used for PCI region flags rather than memory mapping flags. Fix the type to match that of the region flags and stop using the regions flags as memory mapping flags. Signed-off-by: Andrew Scull <ascull@google.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
d158fa1b |
|
18-Feb-2022 |
Pali Rohár <pali@kernel.org> |
pci: Remove duplicate PCI_CLASS_CODE_* and PCI_CLASS_SUB_CODE_* macros Macros PCI_CLASS_CODE_* and PCI_CLASS_SUB_CODE_* are unused and are duplication of PCI_CLASS_* macros defined in pci_ids.h header file. So remove them. Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Stefan Roese <sr@denx.de> |
#
819a43c9 |
|
10-Feb-2022 |
Pali Rohár <pali@kernel.org> |
arm: a37xx: pci: Use standard register macros from pci.h PCI config space of the aardvark PCIe Root Port is available only in internal aardvark memory space starting at offset 0x0. PCI Express registers (PCI_EXP_*) start at offset 0xc0. And Advanced Error Reporting registers (PCI_ERR_*) start at offset 0x100. Replace custom aardvark register macros by standard PCI macros from include/pci.h file with fixed offset. Some DEVCTL and AER macros are not defined in include/pci.h file, so define them in the same way as in linux uapi header file pci_regs.h. Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Stefan Roese <sr@denx.de> |
#
185f812c |
|
19-Jan-2022 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
doc: replace @return by Return: Sphinx expects Return: and not @return to indicate a return value. find . -name '*.c' -exec \ sed -i 's/^\(\s\)\*\(\s*\)@return\(\s\)/\1*\2Return:\3/' {} \; find . -name '*.h' -exec \ sed -i 's/^\(\s\)\*\(\s*\)@return\(\s\)/\1*\2Return:\3/' {} \; Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> |
#
a398a51c |
|
20-Nov-2021 |
Maciej W. Rozycki <macro@orcam.me.uk> |
pci: Work around PCIe link training failures Attempt to handle cases with a downstream port of a PCIe switch where link training never completes and the link continues switching between speeds indefinitely with the data link layer never reaching the active state. It has been observed with a downstream port of the ASMedia ASM2824 Gen 3 switch wired to the upstream port of the Pericom PI7C9X2G304 Gen 2 switch, using a Delock Riser Card PCI Express x1 > 2 x PCIe x1 device, P/N 41433, wired to a SiFive HiFive Unmatched board. In this setup the switches are supposed to negotiate the link speed of preferably 5.0GT/s, falling back to 2.5GT/s. However the link continues oscillating between the two speeds, at the rate of 34-35 times per second, with link training reported repeatedly active ~84% of the time, e.g.: 02:03.0 PCI bridge [0604]: ASMedia Technology Inc. ASM2824 PCIe Gen3 Packet Switch [1b21:2824] (rev 01) (prog-if 00 [Normal decode]) [...] Bus: primary=02, secondary=05, subordinate=05, sec-latency=0 [...] Capabilities: [80] Express (v2) Downstream Port (Slot+), MSI 00 [...] LnkSta: Speed 5GT/s (downgraded), Width x1 (ok) TrErr- Train+ SlotClk+ DLActive- BWMgmt+ ABWMgmt- [...] LnkCtl2: Target Link Speed: 8GT/s, EnterCompliance- SpeedDis+, Selectable De-emphasis: -3.5dB Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS- Compliance De-emphasis: -6dB [...] Forcibly limiting the target link speed to 2.5GT/s with the upstream ASM2824 device makes the two switches communicate correctly however: 02:03.0 PCI bridge [0604]: ASMedia Technology Inc. ASM2824 PCIe Gen3 Packet Switch [1b21:2824] (rev 01) (prog-if 00 [Normal decode]) [...] Bus: primary=02, secondary=05, subordinate=09, sec-latency=0 [...] Capabilities: [80] Express (v2) Downstream Port (Slot+), MSI 00 [...] LnkSta: Speed 2.5GT/s (downgraded), Width x1 (ok) TrErr- Train- SlotClk+ DLActive+ BWMgmt- ABWMgmt- [...] LnkCtl2: Target Link Speed: 2.5GT/s, EnterCompliance- SpeedDis+, Selectable De-emphasis: -3.5dB Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS- Compliance De-emphasis: -6dB [...] and then: 05:00.0 PCI bridge [0604]: Pericom Semiconductor PI7C9X2G304 EL/SL PCIe2 3-Port/4-Lane Packet Switch [12d8:2304] (rev 05) (prog-if 00 [Normal decode]) [...] Bus: primary=05, secondary=06, subordinate=09, sec-latency=0 [...] Capabilities: [c0] Express (v2) Upstream Port, MSI 00 [...] LnkSta: Speed 2.5GT/s (downgraded), Width x1 (downgraded) TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt- [...] LnkCtl2: Target Link Speed: 5GT/s, EnterCompliance- SpeedDis- Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS- Compliance De-emphasis: -6dB [...] Make use of this observation then and attempt to detect the inability to negotiate the link speed automatically, and then handle it by hand. Use the Data Link Layer Link Active status flag as the primary indicator of successful link speed negotiation, but given that the flag is optional by hardware to implement (the ASM2824 does have it though), resort to checking for the mandatory Link Bandwidth Management Status flag showing that the link speed or width has been changed in an attempt to correct unreliable link operation (the ASM2824 does set it too). If these checks indicate that link may not operate correctly, then poll the Data Link Layer Link Active status flag along with the Link Training flag for the duration of 200ms to see if the link has stabilised, that is either that the Data Link Layer Link Active status flag has been set or that Link Training has been inactive during at least the second half of the interval. If that has indicated failure, restrict the target speed to 2.5GT/s, request a link retrain and check again if the link has stabilised. If that does not work either, then restore the original speed setting and claim defeat, otherwise we are done. NB interestingly enough with the ASM2824 vs PI7C9X2G304 configuration referred above asking the ASM2824 to retrain with a higher target link speed once the 2.5GT/s speed has been negotiated makes the two devices successfully negotiate 5.0GT/s. Lifting the 2.5GT/s speed restriction would however prevent our workaround from working with an OS that issues a reset and that is unaware of the problem. This is because the devices would then try to negotiate a higher link speed from scratch and fail, while the sticky property of the Target Link Speed setting will keep the 2.5GT/s speed restriction across a reset. Keep the 2.5GT/s speed restriction then, conservatively, if functional once applied. Signed-off-by: Maciej W. Rozycki <macro@orcam.me.uk> Reviewed-by: Stefan Roese <sr@denx.de> |
#
2a8d4025 |
|
26-Nov-2021 |
Pali Rohár <pali@kernel.org> |
pci: Add standard PCI Config Address macros Lot of PCI and PCIe controllers are using standard Config Address for PCI Configuration Mechanism #1 or its extended version. So add PCI_CONF1_ADDRESS() and PCI_CONF1_EXT_ADDRESS() macros into U-Boot's pci.h header file which can be suitable for most PCI and PCIe controller drivers. Drivers do not have to invent their own macros and can use these new U-Boot macros. Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
a4bc38da |
|
02-Nov-2021 |
Pali Rohár <pali@kernel.org> |
pci: Add standard PCIe ECAM macros Lot of PCIe controllers are using ECAM addressing. So add common ECAM macros into U-Boot's pci.h header file which can be suitable for most PCI controller drivers. Replace custom ECAM address macros in every PCI controller driver by new ECAM macros from U-Boot's pci.h header file. Similar macros are defined also in Linux kernel. There is a small difference between Linux and these new U-Boot macros. U-Boot's PCIE_ECAM_OFFSET() takes device and function numbers in separate arguments. Linux's PCIE_ECAM_OFFSET() takes device and function numbers encoded in one argument. The reason is that U-Boot's PCI_DEVFN() macro is different than Linux's PCI_SLOT() macro. So having device and function numbers in separate arguments makes code more straightforward. Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Stefan Roese <sr@denx.de> |
#
1d7ad685 |
|
25-Sep-2021 |
Pali Rohár <pali@kernel.org> |
arm: a37xx: pci: Handle propagation of CRSSVE bit from PCIe Root Port Now that PCI Bridge (PCIe Root Port) for Aardvark is emulated in U-Boot, add support for handling and propagation of CRSSVE bit. When CRSSVE bit is unset (default), driver has to reissue config read/write request on CRS response. CRSSVE bit is supported only when CRSVIS bit is provided in read-only Root Capabilities register. So manually inject this CRSVIS bit into read response for that register. Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Stefan Roese <sr@denx.de> |
#
2649f69f |
|
17-Sep-2021 |
Vladimir Oltean <vladimir.oltean@nxp.com> |
pci: provide prototype for pci_skip_dev outside of #if defined(CONFIG_DM_PCI_COMPAT) The weak definition of pci_skip_dev from drivers/pci/pci_common.c is not under CONFIG_DM_PCI_COMPAT, and that definition needs a previous function prototype declaration to avoid W=1 build warnings. That prototype is not available due to it being under CONFIG_DM_PCI_COMPAT, so move it outside of that preprocessor block. Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
23cacd57 |
|
01-Aug-2021 |
Simon Glass <sjg@chromium.org> |
pci: Drop PCI_INDIRECT_BRIDGE This does not work with driver model so can be removed. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
26543cc6 |
|
01-Aug-2021 |
Simon Glass <sjg@chromium.org> |
pci: Drop old code from header file We don't need this code anymore since when PCI is enabled, driver model is always used. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
63814a69 |
|
01-Aug-2021 |
Simon Glass <sjg@chromium.org> |
pci: imx: Drop DM_PCI check from cpu driver We don't need this check anymore since when PCI is enabled, driver model is always used. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
e8c09d69 |
|
01-Aug-2021 |
Simon Glass <sjg@chromium.org> |
pci: Remove guard around compatibility functions This prevents use of IS_ENABLED() in other files. Functions should be visible in headers even if they are not available at link time. Fix it. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
f5cbb5c7 |
|
27-Jun-2021 |
Simon Glass <sjg@chromium.org> |
x86: pci: Allow binding of some devices before relocation At present only bridge devices are bound before relocation, to save space in pre-relocation memory. In some cases we do actually want to bind a device, e.g. because it provides the console UART. Add a devicetree binding to support this. Use the PCI_VENDEV() macro to encode the cell value. This is present in U-Boot but not used, so move it to the binding header-file. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
e58f3a7d |
|
27-Jun-2021 |
Simon Glass <sjg@chromium.org> |
pci: Use const for pci_find_device_id() etc. These functions don't modify the device-ID struct that is passed in, so mark the argument as const, so the data structure can be declared that way. This allows it to be placed in the rodata section. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
c7b36007 |
|
14-May-2021 |
Tom Rini <trini@konsulko.com> |
pci: Remove non-DM board_pci_fixup_dev() declaration With the ventana boards migrated to DM_PCI and DM_ETH, we can remove this prototype. Cc: Stefano Babic <sbabic@denx.de> Signed-off-by: Tom Rini <trini@konsulko.com> |
#
cecd013f |
|
16-Apr-2021 |
Tim Harvey <tharvey@gateworks.com> |
pci: pci-uclass: Add board_pci_fixup_dev for DM_PCI Add a board_pci_fixup_dev weak function to allow PCI device fixups during enumeration. Signed-off-by: Tim Harvey <tharvey@gateworks.com> |
#
8b85dfc6 |
|
16-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: Avoid accessing seq directly At present various drivers etc. access the device's 'seq' member directly. This makes it harder to change the meaning of that member. Change access to go through a function instead. The drivers/i2c/lpc32xx_i2c.c file is left unchanged for now. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
caa4daa2 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename 'platdata' variables to just 'plat' We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
284d062e |
|
09-Sep-2020 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
pci: add a few ARI related defines Add a few defines related to PCI ARI configuration. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
51eeae91 |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add VF BAR map support for Enhanced Allocation Makes dm_pci_map_bar API available to map BAR for Virtual function PCI devices which support Enhanced Allocation. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> |
#
b8852dcf |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add support for Single-Root I/O Virtualization SR-IOV - Single Root I/O Virtualization PF - Physical Function VF - Virtual Function If SR-IOV capability is present, use it to initialize Virtual Function PCI device instances. pci_sriov_init function will read SR-IOV registers to create VF devices under the PF PCI device and also bind driver if available. This function needs to be invoked from Physical function device driver which expects VF device support, creating minimal impact on existing framework. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> |
#
e0024741 |
|
23-Jul-2020 |
Stefan Roese <sr@denx.de> |
pci: pci-uclass: Dynamically allocate the PCI regions Instead of using a fixed length pre-allocated array of regions, this patch moves to dynamically allocating the regions based on the number of available regions plus the necessary regions for DRAM banks. Since MAX_PCI_REGIONS is not needed any more, its removed completely with this patch. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Thierry Reding <treding@nvidia.com> Cc: Marek Vasut <marek.vasut+renesas@gmail.com> |
#
143eb5b1 |
|
12-May-2020 |
Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
drivers: pci: add api to get dma regions Add api to get dma regions. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com> |
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com> |
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com> |
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
7d994067 |
|
23-Apr-2019 |
Tom Rini <trini@konsulko.com> |
Merge tag 'pull-24apr19' of git://git.denx.de/u-boot-dm Various minor sandbox iumprovements Fixes for tracing with sandbox Refactoring for boot_get_fdt()
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
a8c5f8d3 |
|
15-Oct-2018 |
Bin Meng <bmeng.cn@gmail.com> |
dm: pci: Add APIs to find next capability and extended capability This introduces two new APIs dm_pci_find_next_capability() and dm_pci_find_next_ext_capability() to get PCI capability address and PCI express extended capability address for a given PCI device starting from a given offset. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
dac01fd8 |
|
03-Aug-2018 |
Bin Meng <bmeng.cn@gmail.com> |
dm: pci: Add APIs to find capability and extended capability This introduces two new APIs dm_pci_find_capability() and dm_pci_find_ext_capability() to get PCI capability address and PCI express extended capability address for a given PCI device. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
5d544f96 |
|
03-Aug-2018 |
Bin Meng <bmeng.cn@gmail.com> |
pci: Add all known capability and extended capability ids Currently we don't have a complete list of capability and extended capability ids. This adds them. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
4345998a |
|
03-Aug-2018 |
Bin Meng <bmeng.cn@gmail.com> |
pci: sandbox: Support dynamically binding device driver At present all emulated sandbox pci devices must be present in the device tree in order to be used. The real world pci uclass driver supports pci device driver matching, and we should add such support on sandbox too. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
01259c93 |
|
03-Aug-2018 |
Bin Meng <bmeng.cn@gmail.com> |
pci: Remove 440ep-specific macros These macros should not be put in the generic pci.h header file. Since they are not referenced anywhere, remove them completely. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
5ce9aca8 |
|
14-May-2018 |
Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi> |
PCI: Document pciauto_region_allocate() Add a doc comment for pciauto_region_allocate(). Signed-off-by: Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
d71975ae |
|
14-May-2018 |
Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi> |
PCI: autoconfig: Don't allocate 64-bit addresses to 32-bit only resources Currently, if we happen to allocate an address requiring 64 bits to a device only supporting 32-bit BARs, the address eventually gets silently truncated to 32 bits. Avoid this by adding a new flag to pciauto_region_allocate() to bail out in such situations. Signed-off-by: Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
83d290c5 |
|
06-May-2018 |
Tom Rini <trini@konsulko.com> |
SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com> |
#
ed68ccbf |
|
13-Mar-2018 |
Stefan Roese <sr@denx.de> |
pci: Remove unused ppc4xx variable from struct pci_controller ppc4xx support was removed some time ago. Lets remove the now unused "pci_fb" variable from "struct pci_controller" as well. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Simon Glass <sjg@chromium.org> |
#
badb9922 |
|
19-Sep-2017 |
Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi> |
pci: Add helper for implementing memory-mapped config space accesses This sort of pattern for implementing memory-mapped PCI config space accesses appears in U-Boot twice already, and a third user is coming up. So add helper functions to avoid code duplication, similar to how Linux has pci_generic_config_write and pci_generic_config_read. Signed-off-by: Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
6ecbe137 |
|
12-May-2017 |
Tim Harvey <tharvey@gateworks.com> |
drivers: pci: imx: add imx_pcie_remove function There is no dedicated reset signal wired up for the MX6QDL thus if the bootloader enables the link we need some special handling to get the core back into a state where it is safe to touch it for configuration. While there has been some special handling in the Linux kernel to do this, it was removed in 4.11 thus we need to do it properly in the bootloader and therefore without this if you enable PCI in the bootloader you will hang while booting the 4.11 kernel. This puts the PCIe controller back into a safe state for the kernel driver before launching the kernel. Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com> Tested-by: Peter Senna Tschudin <peter.senna@collabora.com> |
#
eeb5b1ad |
|
10-Mar-2016 |
Stuart Yoder <stuart.yoder@nxp.com> |
pci: make pci_get_hose_head() available to external users Put pci_get_hose_head() prototype in header so it is available to external users, allowing them to find and iterate over all pci controllers. Signed-off-by: Stuart Yoder <stuart.yoder@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
4974a6ff |
|
06-Mar-2016 |
Simon Glass <sjg@chromium.org> |
pci: Correct a few comments and nits Two comments are missing a parameter and there is an extra blank line. Also two of the region access macros are misnamed. Correct these problems. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
319dba1f |
|
06-Mar-2016 |
Simon Glass <sjg@chromium.org> |
pci: Add functions to update PCI configuration registers It is common to read a config register value, clear and set some bits, then write back the updated value. Add functions to do this in one step, for convenience. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
308143ef |
|
02-Feb-2016 |
Bin Meng <bmeng.cn@gmail.com> |
dm: pci: Add missing forward declarations When CONFIG_DM_PCI_COMPAT is not on, there is only a forward declaration for pci_write_config32(). Add other missing ones. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
9d731c82 |
|
18-Jan-2016 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to write a BAR Add a driver-model version of the pci_write_bar32 function so that this is supported in the new API. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
7e78b9ef |
|
29-Nov-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Switch to DM API for PCI address mapping We should use the new address mapping functions unless we are in compatibility mode. Disable the old functions by default. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
21d1fe7e |
|
29-Nov-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add driver model API functions for address mapping At present the PCI address map functions use the old API. Add new functions for this so that drivers can be converted. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
bab17cf1 |
|
29-Nov-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR Add a driver-model function for reading the PCI BAR from a device. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
a0eb8356 |
|
29-Nov-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a driver-model version of pci_find_class() Add a function which scans the driver model device information rather than scanning the PCI bus again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> |
#
5c0bf647 |
|
29-Nov-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a driver-model version of pci_find_device() Add a function which scans the driver model device information rather than scanning the PCI bus again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> |
#
5e23b8b4 |
|
29-Nov-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Use driver model PCI API in auto-config At present we are using legacy functions even in the auto-configuration code used by driver model. Add a new pci_auto.c version which uses the correct API. Create a new pci_internal.h header to hold functions that are used within the PCI subsystem, but are not exported to other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> |
#
f3f1faef |
|
29-Nov-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a dm_ prefix to pci_bus_find_bdf() Most driver model PCI functions have a dm_ prefix. At some point, when the old code is converted to driver model and the old functions are removed, we will drop that prefix. For consistency, we should use the dm_ prefix for all driver model functions. Update pci_bus_find_bdf() accordingly. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
21ccce1b |
|
29-Nov-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a dm_ prefix to pci_get_bdf() Most driver model PCI functions have a dm_ prefix. At some point, when the old code is converted to driver model and the old functions are removed, we will drop that prefix. For consistency, we should use the dm_ prefix for all driver model functions. Update pci_get_bdf() accordingly. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
3ba5f74a |
|
26-Nov-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Disable PCI compatibility functions by default We eventually need to drop the compatibility functions for driver model. As a first step, create a configuration option to enable them and hide them when the option is disabled. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
54fe7b1c |
|
26-Nov-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a comment about how to find struct pci_controller With driver mode, struct pci_controller is stored as uclass-private data. Add a comment to that effect. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
f9260336 |
|
19-Nov-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to find the regions for a PCI bus This function looks up the controller and returns a pointer to each region type. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Stephen Warren <swarren@nvidia.com> Tested-by: Stephen Warren <swarren@nvidia.com> |
#
9f60fb0d |
|
19-Nov-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to get the controller for a bus A PCI bus may be a bridge device where the controller is the bridge's parent. Add a function to return the controller device, given a PCI device. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Stephen Warren <swarren@nvidia.com> Tested-by: Stephen Warren <swarren@nvidia.com> |
#
9289db6c |
|
19-Nov-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add functions to emulate 8- and 16-bit access Provide a few functions to support using 32-bit access to emulate 8- and 16-bit access. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Stephen Warren <swarren@nvidia.com> Tested-by: Stephen Warren <swarren@nvidia.com> |
#
bcbe3d15 |
|
28-Sep-2015 |
Simon Glass <sjg@chromium.org> |
dm: Rename dev_get_parentdata() to dev_get_parent_priv() The current name is inconsistent with other driver model data access functions. Rename it and fix up all users. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Joe Hershberger <joe.hershberger@ni.com> |
#
dc5740df |
|
22-Aug-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a comment to help find pci_hose_read_config_byte, etc. These functions are defined by macros so do not show up with grep. Add a comment to help. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
76c3fbcd |
|
10-Aug-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a way to iterate through all PCI devices These functions allow iteration through all PCI devices including bridges. The children of each PCI bus are returned in turn. This can be useful for configuring, checking or enumerating all the devices. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
66afb4ed |
|
10-Aug-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Provide friendly config access functions At present there are no PCI functions which allow access to PCI configuration using a struct udevice. This is a sad situation for driver model as it makes use of PCI harder. Add these functions. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
5f48d798 |
|
27-Jul-2015 |
Simon Glass <sjg@chromium.org> |
pci: Add a constant for an invalid interrupt Rather than using 0xff in the code, add a constant. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
ed5b580b |
|
09-Jul-2015 |
Minghuan Lian <Minghuan.Lian@freescale.com> |
drivers/pci: Add function to find an extended capability PCIe extends device's configuration space to 4k and provides extended capability. The patch adds function to find them. The code is ported from Linux PCIe driver. Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
4b515e4f |
|
06-Jul-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to get the BDF for a device It is useful to be able to find the full PCI address (bus, device and function) for a PCI device. Add a function to provide this. Adjust the existing code to use this. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
aba92962 |
|
06-Jul-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add support for PCI driver matching At present all PCI devices must be present in the device tree in order to be used. Many or most PCI devices don't require any configuration other than that which is done automatically by U-Boot. It is inefficent to add a node with nothing but a compatible string in order to get a device working. Add a mechanism whereby PCI drivers can be declared along with the device parameters they support (vendor/device/class). When no suitable driver is found in the device tree the list of such devices is consulted to determine the correct driver. If this also fails, then a generic driver is used as before. The mechanism used is very similar to that provided by Linux and the header file defintions are copied from Linux 4.1. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Joe Hershberger <joe.hershberger@ni.com> |
#
6c89663c |
|
07-Jul-2015 |
Bin Meng <bmeng.cn@gmail.com> |
pci: Configure expansion ROM during auto config process Currently PCI expansion ROM address is assigned by a call to pciauto_setup_rom() outside of the pci auto config process. This does not work when expansion ROM is on a device behind PCI bridge where bridge's memory limit register was already programmed to a value that does not cover the newly assigned expansion ROM address. To fix this, we should configure the ROM address during the auto config process. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Acked-by: Simon Glass <sjg@chromium.org> |
#
aec241df |
|
07-Jun-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Use the correct hose when configuring devices Only the PCI controller has access to the PCI region information. Make sure to use the controller (rather than any attached bridges) when configuring devices. This corrects a failure to scan and configure devices when driver model is enabled for PCI. Also add a comment to explain the problem. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
36d0d3b4 |
|
05-Mar-2015 |
Simon Glass <sjg@chromium.org> |
dm: sandbox: pci: Add a PCI emulation uclass Since sandbox does not have real devices (unless it borrows those from the host) it must use emulations. Provide a uclass which permits PCI operations to be passed through to an emulation device. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
ff3e077b |
|
05-Mar-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a uclass for PCI Add a uclass for PCI controllers and a generic one for PCI devices. Adjust the 'pci' command and the existing PCI support to work with this new uclass. Keep most of the compatibility code in a separate file so that it can be removed one day. TODO: Add more header file comments to the new parts of pci.h Signed-off-by: Simon Glass <sjg@chromium.org> |
#
aab6724c |
|
05-Mar-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move common PCI functions into their own file Driver model will share many functions with the existing PCI implementation. Move these into their own file to avoid duplication and confusion. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
250e039d |
|
27-Jan-2015 |
Simon Glass <sjg@chromium.org> |
pci: Add a function to find a device by class There is an existing function prototype in the header file but it is not implemented. Implement something similar. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
4a2708a0 |
|
14-Jan-2015 |
Simon Glass <sjg@chromium.org> |
x86: Access the VGA ROM when needed Add code to the generic pci_rom file to access the VGA ROM in PCI space when needed. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
d622ac39 |
|
15-Dec-2014 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
powerpc: mpc824x: remove MPC824X cpu support All the MPC824X boards are still non-generic boards: A3000, CPC45, CU824, eXalion, MVBLUE, MUSENKI, Sandpoint824x, utx8245 Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Josef Wagner <Wagner@Microsys.de> Cc: Torsten Demke <torsten.demke@fci.com> Cc: Jim Thompson <jim@musenki.com> Cc: Greg Allen <gallen@arlut.utexas.edu> |
#
e8a552eb |
|
14-Nov-2014 |
Simon Glass <sjg@chromium.org> |
pci: Add functions to read and write a BAR address Some PCI functions cannot be auto-configured. Add a function to set up a fixed BAR which can be used in these situations. Also add a function to read the current address of a BAR. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
4efe52bf |
|
12-Nov-2014 |
Thierry Reding <treding@nvidia.com> |
pci: Honour pci_skip_dev() When enumerating devices, honour the pci_skip_dev() function. This can be used by PCI controller drivers to restrict which devices will be probed. This is required by the NVIDIA Tegra PCIe controller driver, which will fail with a data abort exception if an access is attempted to a device number larger than 0 outside of bus 0. pci_skip_dev() is therefore implemented to prevent any such accesses. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Simon Glass <sjg@chromium.org> |
#
0991866c |
|
07-Aug-2014 |
Tim Harvey <tharvey@gateworks.com> |
pci: add support for board_pci_fixup_dev function Some board-level drivers may wish to have per-device fixup functions for PCI devices. Signed-off-by: Tim Harvey <tharvey@gateworks.com> |
#
fa5cec03 |
|
08-Nov-2013 |
Paul Burton <paul.burton@mips.com> |
pci.h: allow inclusion in assembly source This patch simply #ifdef's out the C-specific parts of pci.h when it is included by an assembly file. This will allow the macros it contains to be used from assembly source as will be done in a followup commit adding support for more modern MIPS Malta boards. Signed-off-by: Paul Burton <paul.burton@imgtec.com> |
#
287df01e |
|
11-Oct-2013 |
Zhao Qiang <B45475@freescale.com> |
PCIe:change the method to get the address of a requested capability in configuration space. Previously, the address of a requested capability is define like that "#define PCI_DCR 0x78" But, the addresses of capabilities is different with regard to PCIe revs. So this method is not flexible. Now a function to get the address of a requested capability is added and used. It can get the address dynamically by capability ID. The step of this function: 1. Read Status register in PCIe configuration space to confirm that Capabilities List is valid. 2. Find the address of Capabilities Pointer Register. 3. Find the address of requested capability from the first capability. Signed-off-by: Zhao Qiang <B45475@freescale.com> |
#
7b4e5844 |
|
03-Jul-2013 |
Zang Roy-R61911 <tie-fei.zang@freescale.com> |
powerpc/pcie: add PCIe version 3.x support T4240 PCIe IP is version 3.0 and has some update comparing previous QorIQ products. 1. Move Freescale specific register define to arch/powerpc/include/asm/fsl_pci.h and update the register offset define for T4240. 2. add the status/control register define use status/control register to judge the link status 3. The original code uses 'Programming Interface' field to judge if PCIE is EP or RC mode, however, T4240 does not support this functionality. According to PCIE specification, 'Header Type' offset 0x0e is used to indicate header type, so for PCIE controller, the patch changes code to use 'Header Type' field to identify if the PCIE is RC or EP mode. This patch fixes the PCIe card link up issue on T4240QDS. Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com> |
#
1a459660 |
|
08-Jul-2013 |
Wolfgang Denk <wd@denx.de> |
Add GPL-2.0+ SPDX-License-Identifier to source files Signed-off-by: Wolfgang Denk <wd@denx.de> [trini: Fixup common/cmd_io.c] Signed-off-by: Tom Rini <trini@ti.com> |
#
bc3442aa |
|
11-Jun-2013 |
Simon Glass <sjg@chromium.org> |
pci: Convert extern inline functions to static inline I am not sure of the meaning of extern inline, but this gives errors when building with function instrumenting enabled. Change these functions to static inline. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
842033e6 |
|
30-May-2013 |
Gabor Juhos <juhosg@openwrt.org> |
pci: introduce CONFIG_PCI_INDIRECT_BRIDGE option The pci_indirect.c file is always compiled when CONFIG_PCI is defined although the indirect PCI bridge support is not needed by every board. Introduce a new CONFIG_PCI_INDIRECT_BRIDGE config option and only compile indirect PCI bridge support if this options is enabled. Also add the new option into the configuration files of the boards which needs that. Compile tested for powerpc, x86, arm and nds32. MAKEALL results: powerpc: --------------------- SUMMARY ---------------------------- Boards compiled: 641 Boards with warnings but no errors: 2 ( ELPPC MPC8323ERDB ) ---------------------------------------------------------- Note: the warnings for ELPPC and MPC8323ERDB are present even without the actual patch. x86: --------------------- SUMMARY ---------------------------- Boards compiled: 1 ---------------------------------------------------------- arm: --------------------- SUMMARY ---------------------------- Boards compiled: 311 ---------------------------------------------------------- nds32: --------------------- SUMMARY ---------------------------- Boards compiled: 3 ---------------------------------------------------------- Cc: Tom Rini <trini@ti.com> Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com> Signed-off-by: Gabor Juhos <juhosg@openwrt.org> |
#
55ae10f8 |
|
20-Oct-2012 |
Bill Richardson <wfrichar@chromium.org> |
x86: gpio: Add GPIO driver for Intel ICH6 and later. Implement <asm-generic/gpio.h> functions for Intel ICH6 and later. Only GPIOs 0-31 are handled by this code. Signed-off-by: Bill Richardson <wfrichar@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org> |
#
a3a70725 |
|
24-Mar-2012 |
Linus Walleij <linus.walleij@linaro.org> |
pci: declare pciauto functions in header The FSL PCI driver uses local prototypes for pciauto_[pre|post]scan_setup_bridge(), this does not seem right, so move them to the <pci.h> file. Fixed a small extern declaration too, this is harmless but distracts the view since all other prototypes are explicitly external. Signed-off-by: Linus Walleij <linus.walleij@linaro.org> |
#
a1e47b66 |
|
03-Mar-2012 |
Linus Walleij <linus.walleij@linaro.org> |
pci: move pciauto_config_init() to pci.h Fixing build regressions for the Integrator I get find that a few boards try to work around the missing declaration of pciauto_config_init() by declaring it in the local scope. This does not make sense when the sibling functions are in <pci.h> so move the function to the header, ridding the build error in the Integrator and getting rid of the local declarations here and there. Reported-by: Wolfgang Denk <wd@denx.de> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> |
#
b03a466d |
|
01-Feb-2011 |
Prabhakar Kushwaha <prabhakar@freescale.com> |
powerpc/85xx: Handle PCIe initialization requires for P1021 class SoCs The P1011, P1012, P1015, P1016, P1020, P1021, P1024, & P1025 SoCs require that we initialize the SERDES registers if the lanes are configured for PCIe. Additionally these devices PCIe controller do not support ASPM and we have to explicitly disable it. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
10fa8d7c |
|
19-Jan-2011 |
Leo Liu <liucai.lfn@gmail.com> |
mpc83xx: fix pcie configuration space read/write This patch fix a problem for the pcie enumeration when the mpc83xx pcie controller is connected with switch or we use both of the two pcie controller. Signed-off-by: Leo Liu <liucai.lfn@gmail.com> fix codingstyle and compiler warning: 'pcie_priv' defined but not used Signed-off-by: Kim Phillips <kim.phillips@freescale.com> |
#
3a0e3c27 |
|
17-Dec-2010 |
Kumar Gala <galak@kernel.crashing.org> |
powerpc/fsl-pci: Determine pci_controller based on cfg addr for dts fixup Previously we passed in a specifically named struct pci_controller to determine if we had setup the particular PCI bus. Now we can search for the struct so we dont have to depend on the name or the struct being statically allocated. Introduced new find_hose_by_cfg_addr() to get back a pci_controller struct back by searching for it means we can do things like dynamically allocate them or not have to expose the static structures to all users. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Wolfgang Denk <wd@denx.de> |
#
983eb9d1 |
|
29-Oct-2010 |
Peter Tyser <ptyser@xes-inc.com> |
pci: Clean up PCI info when CONFIG_PCI_SCAN_SHOW This change does the following: - Removes the printing of the PCI interrupt line value. This is normally set to 0 by U-Boot on bootup and is rarely used during everyday operation. - Prints out the PCI function number of a device. Previously a device with multiple functions would be printed identically 2 times, which is generally confusing. For example, on an Intel 2 port gigabit Ethernet card the following was displayed: ... 04 01 8086 1010 0200 00 04 01 8086 1010 0200 00 ... - Prints a text description of each device's PCI class instead of the raw PCI class code. The textual description makes it much easier to determine what devices are installed on a PCI bus. - Changes the general formatting of the PCI device output. Previous output: PCIE1: connected as Root Complex 04 01 8086 1010 0200 00 04 01 8086 1010 0200 00 03 00 10b5 8112 0604 00 02 01 10b5 8518 0604 00 02 02 10b5 8518 0604 00 08 00 1957 0040 0b20 00 07 00 10b5 8518 0604 00 09 00 10b5 8112 0604 00 07 01 10b5 8518 0604 00 07 02 10b5 8518 0604 00 06 00 10b5 8518 0604 00 02 03 10b5 8518 0604 00 01 00 10b5 8518 0604 00 PCIE1: Bus 00 - 0b PCIE2: connected as Root Complex 0d 00 1957 0040 0b20 00 PCIE2: Bus 0c - 0d Updated output: PCIE1: connected as Root Complex 04:01.0 - 8086:1010 - Network controller 04:01.1 - 8086:1010 - Network controller 03:00.0 - 10b5:8112 - Bridge device 02:01.0 - 10b5:8518 - Bridge device 02:02.0 - 10b5:8518 - Bridge device 08:00.0 - 1957:0040 - Processor 07:00.0 - 10b5:8518 - Bridge device 09:00.0 - 10b5:8112 - Bridge device 07:01.0 - 10b5:8518 - Bridge device 07:02.0 - 10b5:8518 - Bridge device 06:00.0 - 10b5:8518 - Bridge device 02:03.0 - 10b5:8518 - Bridge device 01:00.0 - 10b5:8518 - Bridge device PCIE1: Bus 00 - 0b PCIE2: connected as Root Complex 0d:00.0 - 1957:0040 - Processor PCIE2: Bus 0c - 0d Signed-off-by: Peter Tyser <ptyser@xes-inc.com> |
#
8295b944 |
|
05-Aug-2009 |
Kumar Gala <galak@kernel.crashing.org> |
pci/fsl_pci_init: Use PCIe capability to determine if controller is PCIe Change the code to use the PCIe capabilities register to determine if we are a PCIe controller or not. Additionally cleaned up some white space and formatting in the file. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
cc2a8c77 |
|
19-Feb-2009 |
Anton Vorontsov <avorontsov@ru.mvista.com> |
PCI: Add pci_last_busno() helper This is just a handy routine that reports last PCI busno: we walk down all the hoses and return last hose's last_busno. Will be used by PCI/PCIe initialization code. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com> |
#
6e61fae4 |
|
03-Feb-2009 |
Becky Bruce <beckyb@kernel.crashing.org> |
drivers/pci: Create pci_map_bar function It is no longer always true that the pci bus address can be used as the virtual address for pci accesses. pci_map_bar() is created to return the virtual address for a pci region. Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org> |
#
ff4e66e9 |
|
06-Feb-2009 |
Kumar Gala <galak@kernel.crashing.org> |
pci: Rename PCI_REGION_MEMORY to PCI_REGION_SYS_MEMORY for clarity The PCI_REGION_MEMORY and PCI_REGION_MEM are a bit to similar and can be confusing when reading the code. Rename PCI_REGION_MEMORY to PCI_REGION_SYS_MEMORY to clarify its used for system memory mapping purposes. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
fd6646c0 |
|
07-Jan-2009 |
Anton Vorontsov <avorontsov@ru.mvista.com> |
mpc83xx: Add support for MPC83xx PCI-E controllers This patch adds support for MPC83xx PCI-E controllers in Root Complex mode. The patch is based on Tony Li and Dave Liu work[1]. Though unlike the original patch, by default we don't register PCI-E buses for use in U-Boot, we only configure the controllers for future use in other OSes (Linux). This is done because we don't have enough of spare BATs to map all the PCI-E regions. To actually use PCI-E in U-Boot, users should explicitly define CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES symbol in the board file. And only then U-Boot will able to access PCI-E, but at the cost of disabled address translation. [1] http://lists.denx.de/pipermail/u-boot/2008-January/027630.html Signed-off-by: Tony Li <tony.li@freescale.com> Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Acked-by: Dave Liu <daveliu@freescale.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com> |
#
30e76d5e |
|
21-Oct-2008 |
Kumar Gala <galak@kernel.crashing.org> |
pci: Allow for PCI addresses to be 64-bit PCI bus is inherently 64-bit. While not all system require access to the full 64-bit PCI address range some do. This allows those systems to enable the full PCI address width via CONFIG_SYS_PCI_64BIT. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Andrew Fleming-AFLEMING <afleming@freescale.com> Acked-by: Wolfgang Denk <wd@denx.de> |
#
36f32675 |
|
07-May-2008 |
Becky Bruce <bgill@freescale.com> |
Update pci code to use phys_addr_t Physical addrs need to be represented by phys_addr_t, not unsigned long. Otherwise, systems that use CONFIG_PHYS_64BIT are going to fail mightily. Signed-off-by: Becky Bruce <becky.bruce@freescale.com> |
#
63cec581 |
|
02-Aug-2007 |
Ed Swarthout <Ed.Swarthout@freescale.com> |
Make MPC8641's PCI/PCI-E driver a common driver for many FSL parts. All of the PCI/PCI-Express driver and initialization code that was in the MPC8641HPCN port has now been moved into the common drivers/fsl_pci_init.c. In a subsequent patch, this will be utilized by the 85xx ports as well. Common PCI-E IMMAP register blocks for FSL 85xx/86xx are added. Also enable the second PCI-Express controller on 8641 by getting its BATS and CFG_ setup right. Fixed a u16 vendor compiler warning in AHCI driver too. Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com> Signed-off-by: Zhang Wei <wei.zhang@freescale.com> Signed-off-by: Jon Loeliger <jdl@freescale.com> |
#
13a7fcdf |
|
19-Oct-2006 |
Jon Loeliger <jdl@freescale.com> |
* Fix a bunch of compiler warnings for gcc 4.0 Signed-off-by: Matthew McClintock <msm@freescale.com> |
#
f0e6f57f |
|
28-Jun-2006 |
Matthew McClintock <msm@freescale.com> |
* Added PCI-X #defines for PCI-X initialization Patch by Andy Fleming on 17-Mar-2006 Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
7b230f61 |
|
12-Mar-2006 |
Wolfgang Denk <wd@denx.de> |
Merge with git://git.kernel.org/pub/scm/boot/u-boot/u-boot.git#pci
|
#
993a2275 |
|
12-Mar-2006 |
Wolfgang Denk <wd@denx.de> |
Fix bad declaration on pci_cfgfunc_nothing Patch by Sam Song, 19 Jun 2005 |
#
a179012e |
|
11-Jan-2006 |
Kumar Gala <galak@kernel.crashing.org> |
Added support for PCI prefetchable region and BARs If a host controller sets up a region as prefetchable and a device's BAR denotes it as prefetchable, allocate the BAR into the prefetch region. If a BAR is prefetchable and no prefetchable region has been setup by the controller we fall back to allocating the BAR into the normally memory region. Patch by Kumar Gala 11 Jan 2006 |
#
c157d8e2 |
|
01-Aug-2005 |
Stefan Roese <sr@denx.de> |
Add support for AMCC PPC440EP/GR eval boards Yosemite and Yellowstone. Patch by Steven Blakeslee, 27 Jul 2005 |
#
7a8e9bed |
|
31-May-2003 |
Wolfgang Denk <wd@denx.de> |
* Patch by Marc Singer, 29 May 2003: Fixed rarp boot method for IA32 and other little-endian CPUs. * Patch by Marc Singer, 28 May 2003: Added port I/O commands. * Patch by Matthew McClintock, 28 May 2003 - cpu/mpc824x/start.S: fix relocation code when booting from RAM - minor patches for utx8245 * Patch by Daniel Engstr�m, 28 May 2003: x86 update * Patch by Dave Ellis, 9 May 2003 + 27 May 2003: add nand flash support to SXNI855T configuration fix/extend nand flash support: - fix 'nand erase' command so does not erase bad blocks - fix 'nand write' command so does not write to bad blocks - fix nand_probe() so handles no flash detected properly - add doc/README.nand - add .jffs2 and .oob options to nand read/write - add 'nand bad' command to list bad blocks - add 'clean' option to 'nand erase' to write JFFS2 clean markers - make NAND read/write faster * Patch by Rune Torgersen, 23 May 2003: Update for MPC8266ADS board |
#
c7de829c |
|
19-Nov-2002 |
Wolfgang Denk <wd@denx.de> |
* Patch by Thomas Frieden, 13 Nov 2002: Add code for AmigaOne board (preliminary merge to U-Boot, still WIP) * Patch by Jon Diekema, 12 Nov 2002: - Adding URL for IEEE OUI lookup - Making the autoboot #defines dependent on CONFIG_AUTOBOOT_KEYED being defined. - In the CONFIG_EXTRA_ENV_SETTINGS #define, the root-on-initrd and root-on-nfs macros are designed to switch how the default boot method gets defined. |
#
c609719b |
|
02-Nov-2002 |
Wolfgang Denk <wd@denx.de> |
Initial revision |
#
d158fa1b |
|
18-Feb-2022 |
Pali Rohár <pali@kernel.org> |
pci: Remove duplicate PCI_CLASS_CODE_* and PCI_CLASS_SUB_CODE_* macros Macros PCI_CLASS_CODE_* and PCI_CLASS_SUB_CODE_* are unused and are duplication of PCI_CLASS_* macros defined in pci_ids.h header file. So remove them. Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Stefan Roese <sr@denx.de> |
#
819a43c9 |
|
10-Feb-2022 |
Pali Rohár <pali@kernel.org> |
arm: a37xx: pci: Use standard register macros from pci.h PCI config space of the aardvark PCIe Root Port is available only in internal aardvark memory space starting at offset 0x0. PCI Express registers (PCI_EXP_*) start at offset 0xc0. And Advanced Error Reporting registers (PCI_ERR_*) start at offset 0x100. Replace custom aardvark register macros by standard PCI macros from include/pci.h file with fixed offset. Some DEVCTL and AER macros are not defined in include/pci.h file, so define them in the same way as in linux uapi header file pci_regs.h. Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Stefan Roese <sr@denx.de> |
#
185f812c |
|
19-Jan-2022 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
doc: replace @return by Return: Sphinx expects Return: and not @return to indicate a return value. find . -name '*.c' -exec \ sed -i 's/^\(\s\)\*\(\s*\)@return\(\s\)/\1*\2Return:\3/' {} \; find . -name '*.h' -exec \ sed -i 's/^\(\s\)\*\(\s*\)@return\(\s\)/\1*\2Return:\3/' {} \; Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> |
#
a398a51c |
|
20-Nov-2021 |
Maciej W. Rozycki <macro@orcam.me.uk> |
pci: Work around PCIe link training failures Attempt to handle cases with a downstream port of a PCIe switch where link training never completes and the link continues switching between speeds indefinitely with the data link layer never reaching the active state. It has been observed with a downstream port of the ASMedia ASM2824 Gen 3 switch wired to the upstream port of the Pericom PI7C9X2G304 Gen 2 switch, using a Delock Riser Card PCI Express x1 > 2 x PCIe x1 device, P/N 41433, wired to a SiFive HiFive Unmatched board. In this setup the switches are supposed to negotiate the link speed of preferably 5.0GT/s, falling back to 2.5GT/s. However the link continues oscillating between the two speeds, at the rate of 34-35 times per second, with link training reported repeatedly active ~84% of the time, e.g.: 02:03.0 PCI bridge [0604]: ASMedia Technology Inc. ASM2824 PCIe Gen3 Packet Switch [1b21:2824] (rev 01) (prog-if 00 [Normal decode]) [...] Bus: primary=02, secondary=05, subordinate=05, sec-latency=0 [...] Capabilities: [80] Express (v2) Downstream Port (Slot+), MSI 00 [...] LnkSta: Speed 5GT/s (downgraded), Width x1 (ok) TrErr- Train+ SlotClk+ DLActive- BWMgmt+ ABWMgmt- [...] LnkCtl2: Target Link Speed: 8GT/s, EnterCompliance- SpeedDis+, Selectable De-emphasis: -3.5dB Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS- Compliance De-emphasis: -6dB [...] Forcibly limiting the target link speed to 2.5GT/s with the upstream ASM2824 device makes the two switches communicate correctly however: 02:03.0 PCI bridge [0604]: ASMedia Technology Inc. ASM2824 PCIe Gen3 Packet Switch [1b21:2824] (rev 01) (prog-if 00 [Normal decode]) [...] Bus: primary=02, secondary=05, subordinate=09, sec-latency=0 [...] Capabilities: [80] Express (v2) Downstream Port (Slot+), MSI 00 [...] LnkSta: Speed 2.5GT/s (downgraded), Width x1 (ok) TrErr- Train- SlotClk+ DLActive+ BWMgmt- ABWMgmt- [...] LnkCtl2: Target Link Speed: 2.5GT/s, EnterCompliance- SpeedDis+, Selectable De-emphasis: -3.5dB Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS- Compliance De-emphasis: -6dB [...] and then: 05:00.0 PCI bridge [0604]: Pericom Semiconductor PI7C9X2G304 EL/SL PCIe2 3-Port/4-Lane Packet Switch [12d8:2304] (rev 05) (prog-if 00 [Normal decode]) [...] Bus: primary=05, secondary=06, subordinate=09, sec-latency=0 [...] Capabilities: [c0] Express (v2) Upstream Port, MSI 00 [...] LnkSta: Speed 2.5GT/s (downgraded), Width x1 (downgraded) TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt- [...] LnkCtl2: Target Link Speed: 5GT/s, EnterCompliance- SpeedDis- Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS- Compliance De-emphasis: -6dB [...] Make use of this observation then and attempt to detect the inability to negotiate the link speed automatically, and then handle it by hand. Use the Data Link Layer Link Active status flag as the primary indicator of successful link speed negotiation, but given that the flag is optional by hardware to implement (the ASM2824 does have it though), resort to checking for the mandatory Link Bandwidth Management Status flag showing that the link speed or width has been changed in an attempt to correct unreliable link operation (the ASM2824 does set it too). If these checks indicate that link may not operate correctly, then poll the Data Link Layer Link Active status flag along with the Link Training flag for the duration of 200ms to see if the link has stabilised, that is either that the Data Link Layer Link Active status flag has been set or that Link Training has been inactive during at least the second half of the interval. If that has indicated failure, restrict the target speed to 2.5GT/s, request a link retrain and check again if the link has stabilised. If that does not work either, then restore the original speed setting and claim defeat, otherwise we are done. NB interestingly enough with the ASM2824 vs PI7C9X2G304 configuration referred above asking the ASM2824 to retrain with a higher target link speed once the 2.5GT/s speed has been negotiated makes the two devices successfully negotiate 5.0GT/s. Lifting the 2.5GT/s speed restriction would however prevent our workaround from working with an OS that issues a reset and that is unaware of the problem. This is because the devices would then try to negotiate a higher link speed from scratch and fail, while the sticky property of the Target Link Speed setting will keep the 2.5GT/s speed restriction across a reset. Keep the 2.5GT/s speed restriction then, conservatively, if functional once applied. Signed-off-by: Maciej W. Rozycki <macro@orcam.me.uk> Reviewed-by: Stefan Roese <sr@denx.de> |
#
2a8d4025 |
|
26-Nov-2021 |
Pali Rohár <pali@kernel.org> |
pci: Add standard PCI Config Address macros Lot of PCI and PCIe controllers are using standard Config Address for PCI Configuration Mechanism #1 or its extended version. So add PCI_CONF1_ADDRESS() and PCI_CONF1_EXT_ADDRESS() macros into U-Boot's pci.h header file which can be suitable for most PCI and PCIe controller drivers. Drivers do not have to invent their own macros and can use these new U-Boot macros. Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
a4bc38da |
|
02-Nov-2021 |
Pali Rohár <pali@kernel.org> |
pci: Add standard PCIe ECAM macros Lot of PCIe controllers are using ECAM addressing. So add common ECAM macros into U-Boot's pci.h header file which can be suitable for most PCI controller drivers. Replace custom ECAM address macros in every PCI controller driver by new ECAM macros from U-Boot's pci.h header file. Similar macros are defined also in Linux kernel. There is a small difference between Linux and these new U-Boot macros. U-Boot's PCIE_ECAM_OFFSET() takes device and function numbers in separate arguments. Linux's PCIE_ECAM_OFFSET() takes device and function numbers encoded in one argument. The reason is that U-Boot's PCI_DEVFN() macro is different than Linux's PCI_SLOT() macro. So having device and function numbers in separate arguments makes code more straightforward. Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Stefan Roese <sr@denx.de> |
#
1d7ad685 |
|
25-Sep-2021 |
Pali Rohár <pali@kernel.org> |
arm: a37xx: pci: Handle propagation of CRSSVE bit from PCIe Root Port Now that PCI Bridge (PCIe Root Port) for Aardvark is emulated in U-Boot, add support for handling and propagation of CRSSVE bit. When CRSSVE bit is unset (default), driver has to reissue config read/write request on CRS response. CRSSVE bit is supported only when CRSVIS bit is provided in read-only Root Capabilities register. So manually inject this CRSVIS bit into read response for that register. Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Stefan Roese <sr@denx.de> |
#
2649f69f |
|
17-Sep-2021 |
Vladimir Oltean <vladimir.oltean@nxp.com> |
pci: provide prototype for pci_skip_dev outside of #if defined(CONFIG_DM_PCI_COMPAT) The weak definition of pci_skip_dev from drivers/pci/pci_common.c is not under CONFIG_DM_PCI_COMPAT, and that definition needs a previous function prototype declaration to avoid W=1 build warnings. That prototype is not available due to it being under CONFIG_DM_PCI_COMPAT, so move it outside of that preprocessor block. Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
23cacd57 |
|
01-Aug-2021 |
Simon Glass <sjg@chromium.org> |
pci: Drop PCI_INDIRECT_BRIDGE This does not work with driver model so can be removed. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
26543cc6 |
|
01-Aug-2021 |
Simon Glass <sjg@chromium.org> |
pci: Drop old code from header file We don't need this code anymore since when PCI is enabled, driver model is always used. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
63814a69 |
|
01-Aug-2021 |
Simon Glass <sjg@chromium.org> |
pci: imx: Drop DM_PCI check from cpu driver We don't need this check anymore since when PCI is enabled, driver model is always used. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
e8c09d69 |
|
01-Aug-2021 |
Simon Glass <sjg@chromium.org> |
pci: Remove guard around compatibility functions This prevents use of IS_ENABLED() in other files. Functions should be visible in headers even if they are not available at link time. Fix it. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
f5cbb5c7 |
|
27-Jun-2021 |
Simon Glass <sjg@chromium.org> |
x86: pci: Allow binding of some devices before relocation At present only bridge devices are bound before relocation, to save space in pre-relocation memory. In some cases we do actually want to bind a device, e.g. because it provides the console UART. Add a devicetree binding to support this. Use the PCI_VENDEV() macro to encode the cell value. This is present in U-Boot but not used, so move it to the binding header-file. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
e58f3a7d |
|
27-Jun-2021 |
Simon Glass <sjg@chromium.org> |
pci: Use const for pci_find_device_id() etc. These functions don't modify the device-ID struct that is passed in, so mark the argument as const, so the data structure can be declared that way. This allows it to be placed in the rodata section. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
c7b36007 |
|
14-May-2021 |
Tom Rini <trini@konsulko.com> |
pci: Remove non-DM board_pci_fixup_dev() declaration With the ventana boards migrated to DM_PCI and DM_ETH, we can remove this prototype. Cc: Stefano Babic <sbabic@denx.de> Signed-off-by: Tom Rini <trini@konsulko.com> |
#
cecd013f |
|
16-Apr-2021 |
Tim Harvey <tharvey@gateworks.com> |
pci: pci-uclass: Add board_pci_fixup_dev for DM_PCI Add a board_pci_fixup_dev weak function to allow PCI device fixups during enumeration. Signed-off-by: Tim Harvey <tharvey@gateworks.com> |
#
8b85dfc6 |
|
16-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: Avoid accessing seq directly At present various drivers etc. access the device's 'seq' member directly. This makes it harder to change the meaning of that member. Change access to go through a function instead. The drivers/i2c/lpc32xx_i2c.c file is left unchanged for now. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
caa4daa2 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename 'platdata' variables to just 'plat' We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
284d062e |
|
09-Sep-2020 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
pci: add a few ARI related defines Add a few defines related to PCI ARI configuration. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
51eeae91 |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add VF BAR map support for Enhanced Allocation Makes dm_pci_map_bar API available to map BAR for Virtual function PCI devices which support Enhanced Allocation. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> |
#
b8852dcf |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add support for Single-Root I/O Virtualization SR-IOV - Single Root I/O Virtualization PF - Physical Function VF - Virtual Function If SR-IOV capability is present, use it to initialize Virtual Function PCI device instances. pci_sriov_init function will read SR-IOV registers to create VF devices under the PF PCI device and also bind driver if available. This function needs to be invoked from Physical function device driver which expects VF device support, creating minimal impact on existing framework. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> |
#
e0024741 |
|
23-Jul-2020 |
Stefan Roese <sr@denx.de> |
pci: pci-uclass: Dynamically allocate the PCI regions Instead of using a fixed length pre-allocated array of regions, this patch moves to dynamically allocating the regions based on the number of available regions plus the necessary regions for DRAM banks. Since MAX_PCI_REGIONS is not needed any more, its removed completely with this patch. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Thierry Reding <treding@nvidia.com> Cc: Marek Vasut <marek.vasut+renesas@gmail.com> |
#
143eb5b1 |
|
12-May-2020 |
Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
drivers: pci: add api to get dma regions Add api to get dma regions. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com> |
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com> |
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com> |
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
7d994067 |
|
23-Apr-2019 |
Tom Rini <trini@konsulko.com> |
Merge tag 'pull-24apr19' of git://git.denx.de/u-boot-dm Various minor sandbox iumprovements Fixes for tracing with sandbox Refactoring for boot_get_fdt()
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
a8c5f8d3 |
|
15-Oct-2018 |
Bin Meng <bmeng.cn@gmail.com> |
dm: pci: Add APIs to find next capability and extended capability This introduces two new APIs dm_pci_find_next_capability() and dm_pci_find_next_ext_capability() to get PCI capability address and PCI express extended capability address for a given PCI device starting from a given offset. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
dac01fd8 |
|
03-Aug-2018 |
Bin Meng <bmeng.cn@gmail.com> |
dm: pci: Add APIs to find capability and extended capability This introduces two new APIs dm_pci_find_capability() and dm_pci_find_ext_capability() to get PCI capability address and PCI express extended capability address for a given PCI device. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
5d544f96 |
|
03-Aug-2018 |
Bin Meng <bmeng.cn@gmail.com> |
pci: Add all known capability and extended capability ids Currently we don't have a complete list of capability and extended capability ids. This adds them. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
4345998a |
|
03-Aug-2018 |
Bin Meng <bmeng.cn@gmail.com> |
pci: sandbox: Support dynamically binding device driver At present all emulated sandbox pci devices must be present in the device tree in order to be used. The real world pci uclass driver supports pci device driver matching, and we should add such support on sandbox too. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
01259c93 |
|
03-Aug-2018 |
Bin Meng <bmeng.cn@gmail.com> |
pci: Remove 440ep-specific macros These macros should not be put in the generic pci.h header file. Since they are not referenced anywhere, remove them completely. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
5ce9aca8 |
|
14-May-2018 |
Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi> |
PCI: Document pciauto_region_allocate() Add a doc comment for pciauto_region_allocate(). Signed-off-by: Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
d71975ae |
|
14-May-2018 |
Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi> |
PCI: autoconfig: Don't allocate 64-bit addresses to 32-bit only resources Currently, if we happen to allocate an address requiring 64 bits to a device only supporting 32-bit BARs, the address eventually gets silently truncated to 32 bits. Avoid this by adding a new flag to pciauto_region_allocate() to bail out in such situations. Signed-off-by: Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
83d290c5 |
|
06-May-2018 |
Tom Rini <trini@konsulko.com> |
SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com> |
#
ed68ccbf |
|
13-Mar-2018 |
Stefan Roese <sr@denx.de> |
pci: Remove unused ppc4xx variable from struct pci_controller ppc4xx support was removed some time ago. Lets remove the now unused "pci_fb" variable from "struct pci_controller" as well. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Simon Glass <sjg@chromium.org> |
#
badb9922 |
|
19-Sep-2017 |
Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi> |
pci: Add helper for implementing memory-mapped config space accesses This sort of pattern for implementing memory-mapped PCI config space accesses appears in U-Boot twice already, and a third user is coming up. So add helper functions to avoid code duplication, similar to how Linux has pci_generic_config_write and pci_generic_config_read. Signed-off-by: Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
6ecbe137 |
|
12-May-2017 |
Tim Harvey <tharvey@gateworks.com> |
drivers: pci: imx: add imx_pcie_remove function There is no dedicated reset signal wired up for the MX6QDL thus if the bootloader enables the link we need some special handling to get the core back into a state where it is safe to touch it for configuration. While there has been some special handling in the Linux kernel to do this, it was removed in 4.11 thus we need to do it properly in the bootloader and therefore without this if you enable PCI in the bootloader you will hang while booting the 4.11 kernel. This puts the PCIe controller back into a safe state for the kernel driver before launching the kernel. Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com> Tested-by: Peter Senna Tschudin <peter.senna@collabora.com> |
#
eeb5b1ad |
|
10-Mar-2016 |
Stuart Yoder <stuart.yoder@nxp.com> |
pci: make pci_get_hose_head() available to external users Put pci_get_hose_head() prototype in header so it is available to external users, allowing them to find and iterate over all pci controllers. Signed-off-by: Stuart Yoder <stuart.yoder@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
4974a6ff |
|
06-Mar-2016 |
Simon Glass <sjg@chromium.org> |
pci: Correct a few comments and nits Two comments are missing a parameter and there is an extra blank line. Also two of the region access macros are misnamed. Correct these problems. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
319dba1f |
|
06-Mar-2016 |
Simon Glass <sjg@chromium.org> |
pci: Add functions to update PCI configuration registers It is common to read a config register value, clear and set some bits, then write back the updated value. Add functions to do this in one step, for convenience. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
308143ef |
|
02-Feb-2016 |
Bin Meng <bmeng.cn@gmail.com> |
dm: pci: Add missing forward declarations When CONFIG_DM_PCI_COMPAT is not on, there is only a forward declaration for pci_write_config32(). Add other missing ones. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
9d731c82 |
|
18-Jan-2016 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to write a BAR Add a driver-model version of the pci_write_bar32 function so that this is supported in the new API. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
7e78b9ef |
|
29-Nov-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Switch to DM API for PCI address mapping We should use the new address mapping functions unless we are in compatibility mode. Disable the old functions by default. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
21d1fe7e |
|
29-Nov-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add driver model API functions for address mapping At present the PCI address map functions use the old API. Add new functions for this so that drivers can be converted. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
bab17cf1 |
|
29-Nov-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR Add a driver-model function for reading the PCI BAR from a device. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
a0eb8356 |
|
29-Nov-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a driver-model version of pci_find_class() Add a function which scans the driver model device information rather than scanning the PCI bus again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> |
#
5c0bf647 |
|
29-Nov-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a driver-model version of pci_find_device() Add a function which scans the driver model device information rather than scanning the PCI bus again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> |
#
5e23b8b4 |
|
29-Nov-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Use driver model PCI API in auto-config At present we are using legacy functions even in the auto-configuration code used by driver model. Add a new pci_auto.c version which uses the correct API. Create a new pci_internal.h header to hold functions that are used within the PCI subsystem, but are not exported to other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> |
#
f3f1faef |
|
29-Nov-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a dm_ prefix to pci_bus_find_bdf() Most driver model PCI functions have a dm_ prefix. At some point, when the old code is converted to driver model and the old functions are removed, we will drop that prefix. For consistency, we should use the dm_ prefix for all driver model functions. Update pci_bus_find_bdf() accordingly. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
21ccce1b |
|
29-Nov-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a dm_ prefix to pci_get_bdf() Most driver model PCI functions have a dm_ prefix. At some point, when the old code is converted to driver model and the old functions are removed, we will drop that prefix. For consistency, we should use the dm_ prefix for all driver model functions. Update pci_get_bdf() accordingly. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
3ba5f74a |
|
26-Nov-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Disable PCI compatibility functions by default We eventually need to drop the compatibility functions for driver model. As a first step, create a configuration option to enable them and hide them when the option is disabled. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
54fe7b1c |
|
26-Nov-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a comment about how to find struct pci_controller With driver mode, struct pci_controller is stored as uclass-private data. Add a comment to that effect. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
f9260336 |
|
19-Nov-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to find the regions for a PCI bus This function looks up the controller and returns a pointer to each region type. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Stephen Warren <swarren@nvidia.com> Tested-by: Stephen Warren <swarren@nvidia.com> |
#
9f60fb0d |
|
19-Nov-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to get the controller for a bus A PCI bus may be a bridge device where the controller is the bridge's parent. Add a function to return the controller device, given a PCI device. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Stephen Warren <swarren@nvidia.com> Tested-by: Stephen Warren <swarren@nvidia.com> |
#
9289db6c |
|
19-Nov-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add functions to emulate 8- and 16-bit access Provide a few functions to support using 32-bit access to emulate 8- and 16-bit access. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Stephen Warren <swarren@nvidia.com> Tested-by: Stephen Warren <swarren@nvidia.com> |
#
bcbe3d15 |
|
28-Sep-2015 |
Simon Glass <sjg@chromium.org> |
dm: Rename dev_get_parentdata() to dev_get_parent_priv() The current name is inconsistent with other driver model data access functions. Rename it and fix up all users. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Joe Hershberger <joe.hershberger@ni.com> |
#
dc5740df |
|
22-Aug-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a comment to help find pci_hose_read_config_byte, etc. These functions are defined by macros so do not show up with grep. Add a comment to help. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
76c3fbcd |
|
10-Aug-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a way to iterate through all PCI devices These functions allow iteration through all PCI devices including bridges. The children of each PCI bus are returned in turn. This can be useful for configuring, checking or enumerating all the devices. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
66afb4ed |
|
10-Aug-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Provide friendly config access functions At present there are no PCI functions which allow access to PCI configuration using a struct udevice. This is a sad situation for driver model as it makes use of PCI harder. Add these functions. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
5f48d798 |
|
27-Jul-2015 |
Simon Glass <sjg@chromium.org> |
pci: Add a constant for an invalid interrupt Rather than using 0xff in the code, add a constant. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
ed5b580b |
|
09-Jul-2015 |
Minghuan Lian <Minghuan.Lian@freescale.com> |
drivers/pci: Add function to find an extended capability PCIe extends device's configuration space to 4k and provides extended capability. The patch adds function to find them. The code is ported from Linux PCIe driver. Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
4b515e4f |
|
06-Jul-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to get the BDF for a device It is useful to be able to find the full PCI address (bus, device and function) for a PCI device. Add a function to provide this. Adjust the existing code to use this. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
aba92962 |
|
06-Jul-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add support for PCI driver matching At present all PCI devices must be present in the device tree in order to be used. Many or most PCI devices don't require any configuration other than that which is done automatically by U-Boot. It is inefficent to add a node with nothing but a compatible string in order to get a device working. Add a mechanism whereby PCI drivers can be declared along with the device parameters they support (vendor/device/class). When no suitable driver is found in the device tree the list of such devices is consulted to determine the correct driver. If this also fails, then a generic driver is used as before. The mechanism used is very similar to that provided by Linux and the header file defintions are copied from Linux 4.1. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Joe Hershberger <joe.hershberger@ni.com> |
#
6c89663c |
|
07-Jul-2015 |
Bin Meng <bmeng.cn@gmail.com> |
pci: Configure expansion ROM during auto config process Currently PCI expansion ROM address is assigned by a call to pciauto_setup_rom() outside of the pci auto config process. This does not work when expansion ROM is on a device behind PCI bridge where bridge's memory limit register was already programmed to a value that does not cover the newly assigned expansion ROM address. To fix this, we should configure the ROM address during the auto config process. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Acked-by: Simon Glass <sjg@chromium.org> |
#
aec241df |
|
07-Jun-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Use the correct hose when configuring devices Only the PCI controller has access to the PCI region information. Make sure to use the controller (rather than any attached bridges) when configuring devices. This corrects a failure to scan and configure devices when driver model is enabled for PCI. Also add a comment to explain the problem. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
36d0d3b4 |
|
05-Mar-2015 |
Simon Glass <sjg@chromium.org> |
dm: sandbox: pci: Add a PCI emulation uclass Since sandbox does not have real devices (unless it borrows those from the host) it must use emulations. Provide a uclass which permits PCI operations to be passed through to an emulation device. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
ff3e077b |
|
05-Mar-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a uclass for PCI Add a uclass for PCI controllers and a generic one for PCI devices. Adjust the 'pci' command and the existing PCI support to work with this new uclass. Keep most of the compatibility code in a separate file so that it can be removed one day. TODO: Add more header file comments to the new parts of pci.h Signed-off-by: Simon Glass <sjg@chromium.org> |
#
aab6724c |
|
05-Mar-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move common PCI functions into their own file Driver model will share many functions with the existing PCI implementation. Move these into their own file to avoid duplication and confusion. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
250e039d |
|
27-Jan-2015 |
Simon Glass <sjg@chromium.org> |
pci: Add a function to find a device by class There is an existing function prototype in the header file but it is not implemented. Implement something similar. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
4a2708a0 |
|
14-Jan-2015 |
Simon Glass <sjg@chromium.org> |
x86: Access the VGA ROM when needed Add code to the generic pci_rom file to access the VGA ROM in PCI space when needed. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
d622ac39 |
|
15-Dec-2014 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
powerpc: mpc824x: remove MPC824X cpu support All the MPC824X boards are still non-generic boards: A3000, CPC45, CU824, eXalion, MVBLUE, MUSENKI, Sandpoint824x, utx8245 Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Josef Wagner <Wagner@Microsys.de> Cc: Torsten Demke <torsten.demke@fci.com> Cc: Jim Thompson <jim@musenki.com> Cc: Greg Allen <gallen@arlut.utexas.edu> |
#
e8a552eb |
|
14-Nov-2014 |
Simon Glass <sjg@chromium.org> |
pci: Add functions to read and write a BAR address Some PCI functions cannot be auto-configured. Add a function to set up a fixed BAR which can be used in these situations. Also add a function to read the current address of a BAR. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
4efe52bf |
|
12-Nov-2014 |
Thierry Reding <treding@nvidia.com> |
pci: Honour pci_skip_dev() When enumerating devices, honour the pci_skip_dev() function. This can be used by PCI controller drivers to restrict which devices will be probed. This is required by the NVIDIA Tegra PCIe controller driver, which will fail with a data abort exception if an access is attempted to a device number larger than 0 outside of bus 0. pci_skip_dev() is therefore implemented to prevent any such accesses. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Simon Glass <sjg@chromium.org> |
#
0991866c |
|
07-Aug-2014 |
Tim Harvey <tharvey@gateworks.com> |
pci: add support for board_pci_fixup_dev function Some board-level drivers may wish to have per-device fixup functions for PCI devices. Signed-off-by: Tim Harvey <tharvey@gateworks.com> |
#
fa5cec03 |
|
08-Nov-2013 |
Paul Burton <paul.burton@mips.com> |
pci.h: allow inclusion in assembly source This patch simply #ifdef's out the C-specific parts of pci.h when it is included by an assembly file. This will allow the macros it contains to be used from assembly source as will be done in a followup commit adding support for more modern MIPS Malta boards. Signed-off-by: Paul Burton <paul.burton@imgtec.com> |
#
287df01e |
|
11-Oct-2013 |
Zhao Qiang <B45475@freescale.com> |
PCIe:change the method to get the address of a requested capability in configuration space. Previously, the address of a requested capability is define like that "#define PCI_DCR 0x78" But, the addresses of capabilities is different with regard to PCIe revs. So this method is not flexible. Now a function to get the address of a requested capability is added and used. It can get the address dynamically by capability ID. The step of this function: 1. Read Status register in PCIe configuration space to confirm that Capabilities List is valid. 2. Find the address of Capabilities Pointer Register. 3. Find the address of requested capability from the first capability. Signed-off-by: Zhao Qiang <B45475@freescale.com> |
#
7b4e5844 |
|
03-Jul-2013 |
Zang Roy-R61911 <tie-fei.zang@freescale.com> |
powerpc/pcie: add PCIe version 3.x support T4240 PCIe IP is version 3.0 and has some update comparing previous QorIQ products. 1. Move Freescale specific register define to arch/powerpc/include/asm/fsl_pci.h and update the register offset define for T4240. 2. add the status/control register define use status/control register to judge the link status 3. The original code uses 'Programming Interface' field to judge if PCIE is EP or RC mode, however, T4240 does not support this functionality. According to PCIE specification, 'Header Type' offset 0x0e is used to indicate header type, so for PCIE controller, the patch changes code to use 'Header Type' field to identify if the PCIE is RC or EP mode. This patch fixes the PCIe card link up issue on T4240QDS. Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com> |
#
1a459660 |
|
08-Jul-2013 |
Wolfgang Denk <wd@denx.de> |
Add GPL-2.0+ SPDX-License-Identifier to source files Signed-off-by: Wolfgang Denk <wd@denx.de> [trini: Fixup common/cmd_io.c] Signed-off-by: Tom Rini <trini@ti.com> |
#
bc3442aa |
|
11-Jun-2013 |
Simon Glass <sjg@chromium.org> |
pci: Convert extern inline functions to static inline I am not sure of the meaning of extern inline, but this gives errors when building with function instrumenting enabled. Change these functions to static inline. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
842033e6 |
|
30-May-2013 |
Gabor Juhos <juhosg@openwrt.org> |
pci: introduce CONFIG_PCI_INDIRECT_BRIDGE option The pci_indirect.c file is always compiled when CONFIG_PCI is defined although the indirect PCI bridge support is not needed by every board. Introduce a new CONFIG_PCI_INDIRECT_BRIDGE config option and only compile indirect PCI bridge support if this options is enabled. Also add the new option into the configuration files of the boards which needs that. Compile tested for powerpc, x86, arm and nds32. MAKEALL results: powerpc: --------------------- SUMMARY ---------------------------- Boards compiled: 641 Boards with warnings but no errors: 2 ( ELPPC MPC8323ERDB ) ---------------------------------------------------------- Note: the warnings for ELPPC and MPC8323ERDB are present even without the actual patch. x86: --------------------- SUMMARY ---------------------------- Boards compiled: 1 ---------------------------------------------------------- arm: --------------------- SUMMARY ---------------------------- Boards compiled: 311 ---------------------------------------------------------- nds32: --------------------- SUMMARY ---------------------------- Boards compiled: 3 ---------------------------------------------------------- Cc: Tom Rini <trini@ti.com> Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com> Signed-off-by: Gabor Juhos <juhosg@openwrt.org> |
#
55ae10f8 |
|
20-Oct-2012 |
Bill Richardson <wfrichar@chromium.org> |
x86: gpio: Add GPIO driver for Intel ICH6 and later. Implement <asm-generic/gpio.h> functions for Intel ICH6 and later. Only GPIOs 0-31 are handled by this code. Signed-off-by: Bill Richardson <wfrichar@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org> |
#
a3a70725 |
|
24-Mar-2012 |
Linus Walleij <linus.walleij@linaro.org> |
pci: declare pciauto functions in header The FSL PCI driver uses local prototypes for pciauto_[pre|post]scan_setup_bridge(), this does not seem right, so move them to the <pci.h> file. Fixed a small extern declaration too, this is harmless but distracts the view since all other prototypes are explicitly external. Signed-off-by: Linus Walleij <linus.walleij@linaro.org> |
#
a1e47b66 |
|
03-Mar-2012 |
Linus Walleij <linus.walleij@linaro.org> |
pci: move pciauto_config_init() to pci.h Fixing build regressions for the Integrator I get find that a few boards try to work around the missing declaration of pciauto_config_init() by declaring it in the local scope. This does not make sense when the sibling functions are in <pci.h> so move the function to the header, ridding the build error in the Integrator and getting rid of the local declarations here and there. Reported-by: Wolfgang Denk <wd@denx.de> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> |
#
b03a466d |
|
01-Feb-2011 |
Prabhakar Kushwaha <prabhakar@freescale.com> |
powerpc/85xx: Handle PCIe initialization requires for P1021 class SoCs The P1011, P1012, P1015, P1016, P1020, P1021, P1024, & P1025 SoCs require that we initialize the SERDES registers if the lanes are configured for PCIe. Additionally these devices PCIe controller do not support ASPM and we have to explicitly disable it. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
10fa8d7c |
|
19-Jan-2011 |
Leo Liu <liucai.lfn@gmail.com> |
mpc83xx: fix pcie configuration space read/write This patch fix a problem for the pcie enumeration when the mpc83xx pcie controller is connected with switch or we use both of the two pcie controller. Signed-off-by: Leo Liu <liucai.lfn@gmail.com> fix codingstyle and compiler warning: 'pcie_priv' defined but not used Signed-off-by: Kim Phillips <kim.phillips@freescale.com> |
#
3a0e3c27 |
|
17-Dec-2010 |
Kumar Gala <galak@kernel.crashing.org> |
powerpc/fsl-pci: Determine pci_controller based on cfg addr for dts fixup Previously we passed in a specifically named struct pci_controller to determine if we had setup the particular PCI bus. Now we can search for the struct so we dont have to depend on the name or the struct being statically allocated. Introduced new find_hose_by_cfg_addr() to get back a pci_controller struct back by searching for it means we can do things like dynamically allocate them or not have to expose the static structures to all users. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Wolfgang Denk <wd@denx.de> |
#
983eb9d1 |
|
29-Oct-2010 |
Peter Tyser <ptyser@xes-inc.com> |
pci: Clean up PCI info when CONFIG_PCI_SCAN_SHOW This change does the following: - Removes the printing of the PCI interrupt line value. This is normally set to 0 by U-Boot on bootup and is rarely used during everyday operation. - Prints out the PCI function number of a device. Previously a device with multiple functions would be printed identically 2 times, which is generally confusing. For example, on an Intel 2 port gigabit Ethernet card the following was displayed: ... 04 01 8086 1010 0200 00 04 01 8086 1010 0200 00 ... - Prints a text description of each device's PCI class instead of the raw PCI class code. The textual description makes it much easier to determine what devices are installed on a PCI bus. - Changes the general formatting of the PCI device output. Previous output: PCIE1: connected as Root Complex 04 01 8086 1010 0200 00 04 01 8086 1010 0200 00 03 00 10b5 8112 0604 00 02 01 10b5 8518 0604 00 02 02 10b5 8518 0604 00 08 00 1957 0040 0b20 00 07 00 10b5 8518 0604 00 09 00 10b5 8112 0604 00 07 01 10b5 8518 0604 00 07 02 10b5 8518 0604 00 06 00 10b5 8518 0604 00 02 03 10b5 8518 0604 00 01 00 10b5 8518 0604 00 PCIE1: Bus 00 - 0b PCIE2: connected as Root Complex 0d 00 1957 0040 0b20 00 PCIE2: Bus 0c - 0d Updated output: PCIE1: connected as Root Complex 04:01.0 - 8086:1010 - Network controller 04:01.1 - 8086:1010 - Network controller 03:00.0 - 10b5:8112 - Bridge device 02:01.0 - 10b5:8518 - Bridge device 02:02.0 - 10b5:8518 - Bridge device 08:00.0 - 1957:0040 - Processor 07:00.0 - 10b5:8518 - Bridge device 09:00.0 - 10b5:8112 - Bridge device 07:01.0 - 10b5:8518 - Bridge device 07:02.0 - 10b5:8518 - Bridge device 06:00.0 - 10b5:8518 - Bridge device 02:03.0 - 10b5:8518 - Bridge device 01:00.0 - 10b5:8518 - Bridge device PCIE1: Bus 00 - 0b PCIE2: connected as Root Complex 0d:00.0 - 1957:0040 - Processor PCIE2: Bus 0c - 0d Signed-off-by: Peter Tyser <ptyser@xes-inc.com> |
#
8295b944 |
|
05-Aug-2009 |
Kumar Gala <galak@kernel.crashing.org> |
pci/fsl_pci_init: Use PCIe capability to determine if controller is PCIe Change the code to use the PCIe capabilities register to determine if we are a PCIe controller or not. Additionally cleaned up some white space and formatting in the file. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
cc2a8c77 |
|
19-Feb-2009 |
Anton Vorontsov <avorontsov@ru.mvista.com> |
PCI: Add pci_last_busno() helper This is just a handy routine that reports last PCI busno: we walk down all the hoses and return last hose's last_busno. Will be used by PCI/PCIe initialization code. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com> |
#
6e61fae4 |
|
03-Feb-2009 |
Becky Bruce <beckyb@kernel.crashing.org> |
drivers/pci: Create pci_map_bar function It is no longer always true that the pci bus address can be used as the virtual address for pci accesses. pci_map_bar() is created to return the virtual address for a pci region. Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org> |
#
ff4e66e9 |
|
06-Feb-2009 |
Kumar Gala <galak@kernel.crashing.org> |
pci: Rename PCI_REGION_MEMORY to PCI_REGION_SYS_MEMORY for clarity The PCI_REGION_MEMORY and PCI_REGION_MEM are a bit to similar and can be confusing when reading the code. Rename PCI_REGION_MEMORY to PCI_REGION_SYS_MEMORY to clarify its used for system memory mapping purposes. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
fd6646c0 |
|
07-Jan-2009 |
Anton Vorontsov <avorontsov@ru.mvista.com> |
mpc83xx: Add support for MPC83xx PCI-E controllers This patch adds support for MPC83xx PCI-E controllers in Root Complex mode. The patch is based on Tony Li and Dave Liu work[1]. Though unlike the original patch, by default we don't register PCI-E buses for use in U-Boot, we only configure the controllers for future use in other OSes (Linux). This is done because we don't have enough of spare BATs to map all the PCI-E regions. To actually use PCI-E in U-Boot, users should explicitly define CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES symbol in the board file. And only then U-Boot will able to access PCI-E, but at the cost of disabled address translation. [1] http://lists.denx.de/pipermail/u-boot/2008-January/027630.html Signed-off-by: Tony Li <tony.li@freescale.com> Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Acked-by: Dave Liu <daveliu@freescale.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com> |
#
30e76d5e |
|
21-Oct-2008 |
Kumar Gala <galak@kernel.crashing.org> |
pci: Allow for PCI addresses to be 64-bit PCI bus is inherently 64-bit. While not all system require access to the full 64-bit PCI address range some do. This allows those systems to enable the full PCI address width via CONFIG_SYS_PCI_64BIT. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Andrew Fleming-AFLEMING <afleming@freescale.com> Acked-by: Wolfgang Denk <wd@denx.de> |
#
36f32675 |
|
07-May-2008 |
Becky Bruce <bgill@freescale.com> |
Update pci code to use phys_addr_t Physical addrs need to be represented by phys_addr_t, not unsigned long. Otherwise, systems that use CONFIG_PHYS_64BIT are going to fail mightily. Signed-off-by: Becky Bruce <becky.bruce@freescale.com> |
#
63cec581 |
|
02-Aug-2007 |
Ed Swarthout <Ed.Swarthout@freescale.com> |
Make MPC8641's PCI/PCI-E driver a common driver for many FSL parts. All of the PCI/PCI-Express driver and initialization code that was in the MPC8641HPCN port has now been moved into the common drivers/fsl_pci_init.c. In a subsequent patch, this will be utilized by the 85xx ports as well. Common PCI-E IMMAP register blocks for FSL 85xx/86xx are added. Also enable the second PCI-Express controller on 8641 by getting its BATS and CFG_ setup right. Fixed a u16 vendor compiler warning in AHCI driver too. Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com> Signed-off-by: Zhang Wei <wei.zhang@freescale.com> Signed-off-by: Jon Loeliger <jdl@freescale.com> |
#
13a7fcdf |
|
19-Oct-2006 |
Jon Loeliger <jdl@freescale.com> |
* Fix a bunch of compiler warnings for gcc 4.0 Signed-off-by: Matthew McClintock <msm@freescale.com> |
#
f0e6f57f |
|
28-Jun-2006 |
Matthew McClintock <msm@freescale.com> |
* Added PCI-X #defines for PCI-X initialization Patch by Andy Fleming on 17-Mar-2006 Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
7b230f61 |
|
12-Mar-2006 |
Wolfgang Denk <wd@denx.de> |
Merge with git://git.kernel.org/pub/scm/boot/u-boot/u-boot.git#pci
|
#
993a2275 |
|
12-Mar-2006 |
Wolfgang Denk <wd@denx.de> |
Fix bad declaration on pci_cfgfunc_nothing Patch by Sam Song, 19 Jun 2005 |
#
a179012e |
|
11-Jan-2006 |
Kumar Gala <galak@kernel.crashing.org> |
Added support for PCI prefetchable region and BARs If a host controller sets up a region as prefetchable and a device's BAR denotes it as prefetchable, allocate the BAR into the prefetch region. If a BAR is prefetchable and no prefetchable region has been setup by the controller we fall back to allocating the BAR into the normally memory region. Patch by Kumar Gala 11 Jan 2006 |
#
c157d8e2 |
|
01-Aug-2005 |
Stefan Roese <sr@denx.de> |
Add support for AMCC PPC440EP/GR eval boards Yosemite and Yellowstone. Patch by Steven Blakeslee, 27 Jul 2005 |
#
7a8e9bed |
|
31-May-2003 |
Wolfgang Denk <wd@denx.de> |
* Patch by Marc Singer, 29 May 2003: Fixed rarp boot method for IA32 and other little-endian CPUs. * Patch by Marc Singer, 28 May 2003: Added port I/O commands. * Patch by Matthew McClintock, 28 May 2003 - cpu/mpc824x/start.S: fix relocation code when booting from RAM - minor patches for utx8245 * Patch by Daniel Engstr�m, 28 May 2003: x86 update * Patch by Dave Ellis, 9 May 2003 + 27 May 2003: add nand flash support to SXNI855T configuration fix/extend nand flash support: - fix 'nand erase' command so does not erase bad blocks - fix 'nand write' command so does not write to bad blocks - fix nand_probe() so handles no flash detected properly - add doc/README.nand - add .jffs2 and .oob options to nand read/write - add 'nand bad' command to list bad blocks - add 'clean' option to 'nand erase' to write JFFS2 clean markers - make NAND read/write faster * Patch by Rune Torgersen, 23 May 2003: Update for MPC8266ADS board |
#
c7de829c |
|
19-Nov-2002 |
Wolfgang Denk <wd@denx.de> |
* Patch by Thomas Frieden, 13 Nov 2002: Add code for AmigaOne board (preliminary merge to U-Boot, still WIP) * Patch by Jon Diekema, 12 Nov 2002: - Adding URL for IEEE OUI lookup - Making the autoboot #defines dependent on CONFIG_AUTOBOOT_KEYED being defined. - In the CONFIG_EXTRA_ENV_SETTINGS #define, the root-on-initrd and root-on-nfs macros are designed to switch how the default boot method gets defined. |
#
c609719b |
|
02-Nov-2002 |
Wolfgang Denk <wd@denx.de> |
Initial revision |
#
819a43c9 |
|
10-Feb-2022 |
Pali Rohár <pali@kernel.org> |
arm: a37xx: pci: Use standard register macros from pci.h PCI config space of the aardvark PCIe Root Port is available only in internal aardvark memory space starting at offset 0x0. PCI Express registers (PCI_EXP_*) start at offset 0xc0. And Advanced Error Reporting registers (PCI_ERR_*) start at offset 0x100. Replace custom aardvark register macros by standard PCI macros from include/pci.h file with fixed offset. Some DEVCTL and AER macros are not defined in include/pci.h file, so define them in the same way as in linux uapi header file pci_regs.h. Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Stefan Roese <sr@denx.de> |
#
185f812c |
|
19-Jan-2022 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
doc: replace @return by Return: Sphinx expects Return: and not @return to indicate a return value. find . -name '*.c' -exec \ sed -i 's/^\(\s\)\*\(\s*\)@return\(\s\)/\1*\2Return:\3/' {} \; find . -name '*.h' -exec \ sed -i 's/^\(\s\)\*\(\s*\)@return\(\s\)/\1*\2Return:\3/' {} \; Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> |
#
a398a51c |
|
20-Nov-2021 |
Maciej W. Rozycki <macro@orcam.me.uk> |
pci: Work around PCIe link training failures Attempt to handle cases with a downstream port of a PCIe switch where link training never completes and the link continues switching between speeds indefinitely with the data link layer never reaching the active state. It has been observed with a downstream port of the ASMedia ASM2824 Gen 3 switch wired to the upstream port of the Pericom PI7C9X2G304 Gen 2 switch, using a Delock Riser Card PCI Express x1 > 2 x PCIe x1 device, P/N 41433, wired to a SiFive HiFive Unmatched board. In this setup the switches are supposed to negotiate the link speed of preferably 5.0GT/s, falling back to 2.5GT/s. However the link continues oscillating between the two speeds, at the rate of 34-35 times per second, with link training reported repeatedly active ~84% of the time, e.g.: 02:03.0 PCI bridge [0604]: ASMedia Technology Inc. ASM2824 PCIe Gen3 Packet Switch [1b21:2824] (rev 01) (prog-if 00 [Normal decode]) [...] Bus: primary=02, secondary=05, subordinate=05, sec-latency=0 [...] Capabilities: [80] Express (v2) Downstream Port (Slot+), MSI 00 [...] LnkSta: Speed 5GT/s (downgraded), Width x1 (ok) TrErr- Train+ SlotClk+ DLActive- BWMgmt+ ABWMgmt- [...] LnkCtl2: Target Link Speed: 8GT/s, EnterCompliance- SpeedDis+, Selectable De-emphasis: -3.5dB Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS- Compliance De-emphasis: -6dB [...] Forcibly limiting the target link speed to 2.5GT/s with the upstream ASM2824 device makes the two switches communicate correctly however: 02:03.0 PCI bridge [0604]: ASMedia Technology Inc. ASM2824 PCIe Gen3 Packet Switch [1b21:2824] (rev 01) (prog-if 00 [Normal decode]) [...] Bus: primary=02, secondary=05, subordinate=09, sec-latency=0 [...] Capabilities: [80] Express (v2) Downstream Port (Slot+), MSI 00 [...] LnkSta: Speed 2.5GT/s (downgraded), Width x1 (ok) TrErr- Train- SlotClk+ DLActive+ BWMgmt- ABWMgmt- [...] LnkCtl2: Target Link Speed: 2.5GT/s, EnterCompliance- SpeedDis+, Selectable De-emphasis: -3.5dB Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS- Compliance De-emphasis: -6dB [...] and then: 05:00.0 PCI bridge [0604]: Pericom Semiconductor PI7C9X2G304 EL/SL PCIe2 3-Port/4-Lane Packet Switch [12d8:2304] (rev 05) (prog-if 00 [Normal decode]) [...] Bus: primary=05, secondary=06, subordinate=09, sec-latency=0 [...] Capabilities: [c0] Express (v2) Upstream Port, MSI 00 [...] LnkSta: Speed 2.5GT/s (downgraded), Width x1 (downgraded) TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt- [...] LnkCtl2: Target Link Speed: 5GT/s, EnterCompliance- SpeedDis- Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS- Compliance De-emphasis: -6dB [...] Make use of this observation then and attempt to detect the inability to negotiate the link speed automatically, and then handle it by hand. Use the Data Link Layer Link Active status flag as the primary indicator of successful link speed negotiation, but given that the flag is optional by hardware to implement (the ASM2824 does have it though), resort to checking for the mandatory Link Bandwidth Management Status flag showing that the link speed or width has been changed in an attempt to correct unreliable link operation (the ASM2824 does set it too). If these checks indicate that link may not operate correctly, then poll the Data Link Layer Link Active status flag along with the Link Training flag for the duration of 200ms to see if the link has stabilised, that is either that the Data Link Layer Link Active status flag has been set or that Link Training has been inactive during at least the second half of the interval. If that has indicated failure, restrict the target speed to 2.5GT/s, request a link retrain and check again if the link has stabilised. If that does not work either, then restore the original speed setting and claim defeat, otherwise we are done. NB interestingly enough with the ASM2824 vs PI7C9X2G304 configuration referred above asking the ASM2824 to retrain with a higher target link speed once the 2.5GT/s speed has been negotiated makes the two devices successfully negotiate 5.0GT/s. Lifting the 2.5GT/s speed restriction would however prevent our workaround from working with an OS that issues a reset and that is unaware of the problem. This is because the devices would then try to negotiate a higher link speed from scratch and fail, while the sticky property of the Target Link Speed setting will keep the 2.5GT/s speed restriction across a reset. Keep the 2.5GT/s speed restriction then, conservatively, if functional once applied. Signed-off-by: Maciej W. Rozycki <macro@orcam.me.uk> Reviewed-by: Stefan Roese <sr@denx.de> |
#
2a8d4025 |
|
26-Nov-2021 |
Pali Rohár <pali@kernel.org> |
pci: Add standard PCI Config Address macros Lot of PCI and PCIe controllers are using standard Config Address for PCI Configuration Mechanism #1 or its extended version. So add PCI_CONF1_ADDRESS() and PCI_CONF1_EXT_ADDRESS() macros into U-Boot's pci.h header file which can be suitable for most PCI and PCIe controller drivers. Drivers do not have to invent their own macros and can use these new U-Boot macros. Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
a4bc38da |
|
02-Nov-2021 |
Pali Rohár <pali@kernel.org> |
pci: Add standard PCIe ECAM macros Lot of PCIe controllers are using ECAM addressing. So add common ECAM macros into U-Boot's pci.h header file which can be suitable for most PCI controller drivers. Replace custom ECAM address macros in every PCI controller driver by new ECAM macros from U-Boot's pci.h header file. Similar macros are defined also in Linux kernel. There is a small difference between Linux and these new U-Boot macros. U-Boot's PCIE_ECAM_OFFSET() takes device and function numbers in separate arguments. Linux's PCIE_ECAM_OFFSET() takes device and function numbers encoded in one argument. The reason is that U-Boot's PCI_DEVFN() macro is different than Linux's PCI_SLOT() macro. So having device and function numbers in separate arguments makes code more straightforward. Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Stefan Roese <sr@denx.de> |
#
1d7ad685 |
|
25-Sep-2021 |
Pali Rohár <pali@kernel.org> |
arm: a37xx: pci: Handle propagation of CRSSVE bit from PCIe Root Port Now that PCI Bridge (PCIe Root Port) for Aardvark is emulated in U-Boot, add support for handling and propagation of CRSSVE bit. When CRSSVE bit is unset (default), driver has to reissue config read/write request on CRS response. CRSSVE bit is supported only when CRSVIS bit is provided in read-only Root Capabilities register. So manually inject this CRSVIS bit into read response for that register. Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Stefan Roese <sr@denx.de> |
#
2649f69f |
|
17-Sep-2021 |
Vladimir Oltean <vladimir.oltean@nxp.com> |
pci: provide prototype for pci_skip_dev outside of #if defined(CONFIG_DM_PCI_COMPAT) The weak definition of pci_skip_dev from drivers/pci/pci_common.c is not under CONFIG_DM_PCI_COMPAT, and that definition needs a previous function prototype declaration to avoid W=1 build warnings. That prototype is not available due to it being under CONFIG_DM_PCI_COMPAT, so move it outside of that preprocessor block. Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
23cacd57 |
|
01-Aug-2021 |
Simon Glass <sjg@chromium.org> |
pci: Drop PCI_INDIRECT_BRIDGE This does not work with driver model so can be removed. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
26543cc6 |
|
01-Aug-2021 |
Simon Glass <sjg@chromium.org> |
pci: Drop old code from header file We don't need this code anymore since when PCI is enabled, driver model is always used. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
63814a69 |
|
01-Aug-2021 |
Simon Glass <sjg@chromium.org> |
pci: imx: Drop DM_PCI check from cpu driver We don't need this check anymore since when PCI is enabled, driver model is always used. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
e8c09d69 |
|
01-Aug-2021 |
Simon Glass <sjg@chromium.org> |
pci: Remove guard around compatibility functions This prevents use of IS_ENABLED() in other files. Functions should be visible in headers even if they are not available at link time. Fix it. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
f5cbb5c7 |
|
27-Jun-2021 |
Simon Glass <sjg@chromium.org> |
x86: pci: Allow binding of some devices before relocation At present only bridge devices are bound before relocation, to save space in pre-relocation memory. In some cases we do actually want to bind a device, e.g. because it provides the console UART. Add a devicetree binding to support this. Use the PCI_VENDEV() macro to encode the cell value. This is present in U-Boot but not used, so move it to the binding header-file. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
e58f3a7d |
|
27-Jun-2021 |
Simon Glass <sjg@chromium.org> |
pci: Use const for pci_find_device_id() etc. These functions don't modify the device-ID struct that is passed in, so mark the argument as const, so the data structure can be declared that way. This allows it to be placed in the rodata section. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
c7b36007 |
|
14-May-2021 |
Tom Rini <trini@konsulko.com> |
pci: Remove non-DM board_pci_fixup_dev() declaration With the ventana boards migrated to DM_PCI and DM_ETH, we can remove this prototype. Cc: Stefano Babic <sbabic@denx.de> Signed-off-by: Tom Rini <trini@konsulko.com> |
#
cecd013f |
|
16-Apr-2021 |
Tim Harvey <tharvey@gateworks.com> |
pci: pci-uclass: Add board_pci_fixup_dev for DM_PCI Add a board_pci_fixup_dev weak function to allow PCI device fixups during enumeration. Signed-off-by: Tim Harvey <tharvey@gateworks.com> |
#
8b85dfc6 |
|
16-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: Avoid accessing seq directly At present various drivers etc. access the device's 'seq' member directly. This makes it harder to change the meaning of that member. Change access to go through a function instead. The drivers/i2c/lpc32xx_i2c.c file is left unchanged for now. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
caa4daa2 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename 'platdata' variables to just 'plat' We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
284d062e |
|
09-Sep-2020 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
pci: add a few ARI related defines Add a few defines related to PCI ARI configuration. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
51eeae91 |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add VF BAR map support for Enhanced Allocation Makes dm_pci_map_bar API available to map BAR for Virtual function PCI devices which support Enhanced Allocation. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> |
#
b8852dcf |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add support for Single-Root I/O Virtualization SR-IOV - Single Root I/O Virtualization PF - Physical Function VF - Virtual Function If SR-IOV capability is present, use it to initialize Virtual Function PCI device instances. pci_sriov_init function will read SR-IOV registers to create VF devices under the PF PCI device and also bind driver if available. This function needs to be invoked from Physical function device driver which expects VF device support, creating minimal impact on existing framework. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> |
#
e0024741 |
|
23-Jul-2020 |
Stefan Roese <sr@denx.de> |
pci: pci-uclass: Dynamically allocate the PCI regions Instead of using a fixed length pre-allocated array of regions, this patch moves to dynamically allocating the regions based on the number of available regions plus the necessary regions for DRAM banks. Since MAX_PCI_REGIONS is not needed any more, its removed completely with this patch. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Thierry Reding <treding@nvidia.com> Cc: Marek Vasut <marek.vasut+renesas@gmail.com> |
#
143eb5b1 |
|
12-May-2020 |
Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
drivers: pci: add api to get dma regions Add api to get dma regions. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com> |
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com> |
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com> |
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
7d994067 |
|
23-Apr-2019 |
Tom Rini <trini@konsulko.com> |
Merge tag 'pull-24apr19' of git://git.denx.de/u-boot-dm Various minor sandbox iumprovements Fixes for tracing with sandbox Refactoring for boot_get_fdt()
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
a8c5f8d3 |
|
15-Oct-2018 |
Bin Meng <bmeng.cn@gmail.com> |
dm: pci: Add APIs to find next capability and extended capability This introduces two new APIs dm_pci_find_next_capability() and dm_pci_find_next_ext_capability() to get PCI capability address and PCI express extended capability address for a given PCI device starting from a given offset. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
dac01fd8 |
|
03-Aug-2018 |
Bin Meng <bmeng.cn@gmail.com> |
dm: pci: Add APIs to find capability and extended capability This introduces two new APIs dm_pci_find_capability() and dm_pci_find_ext_capability() to get PCI capability address and PCI express extended capability address for a given PCI device. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
5d544f96 |
|
03-Aug-2018 |
Bin Meng <bmeng.cn@gmail.com> |
pci: Add all known capability and extended capability ids Currently we don't have a complete list of capability and extended capability ids. This adds them. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
4345998a |
|
03-Aug-2018 |
Bin Meng <bmeng.cn@gmail.com> |
pci: sandbox: Support dynamically binding device driver At present all emulated sandbox pci devices must be present in the device tree in order to be used. The real world pci uclass driver supports pci device driver matching, and we should add such support on sandbox too. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
01259c93 |
|
03-Aug-2018 |
Bin Meng <bmeng.cn@gmail.com> |
pci: Remove 440ep-specific macros These macros should not be put in the generic pci.h header file. Since they are not referenced anywhere, remove them completely. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
5ce9aca8 |
|
14-May-2018 |
Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi> |
PCI: Document pciauto_region_allocate() Add a doc comment for pciauto_region_allocate(). Signed-off-by: Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
d71975ae |
|
14-May-2018 |
Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi> |
PCI: autoconfig: Don't allocate 64-bit addresses to 32-bit only resources Currently, if we happen to allocate an address requiring 64 bits to a device only supporting 32-bit BARs, the address eventually gets silently truncated to 32 bits. Avoid this by adding a new flag to pciauto_region_allocate() to bail out in such situations. Signed-off-by: Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
83d290c5 |
|
06-May-2018 |
Tom Rini <trini@konsulko.com> |
SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com> |
#
ed68ccbf |
|
13-Mar-2018 |
Stefan Roese <sr@denx.de> |
pci: Remove unused ppc4xx variable from struct pci_controller ppc4xx support was removed some time ago. Lets remove the now unused "pci_fb" variable from "struct pci_controller" as well. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Simon Glass <sjg@chromium.org> |
#
badb9922 |
|
19-Sep-2017 |
Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi> |
pci: Add helper for implementing memory-mapped config space accesses This sort of pattern for implementing memory-mapped PCI config space accesses appears in U-Boot twice already, and a third user is coming up. So add helper functions to avoid code duplication, similar to how Linux has pci_generic_config_write and pci_generic_config_read. Signed-off-by: Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
6ecbe137 |
|
12-May-2017 |
Tim Harvey <tharvey@gateworks.com> |
drivers: pci: imx: add imx_pcie_remove function There is no dedicated reset signal wired up for the MX6QDL thus if the bootloader enables the link we need some special handling to get the core back into a state where it is safe to touch it for configuration. While there has been some special handling in the Linux kernel to do this, it was removed in 4.11 thus we need to do it properly in the bootloader and therefore without this if you enable PCI in the bootloader you will hang while booting the 4.11 kernel. This puts the PCIe controller back into a safe state for the kernel driver before launching the kernel. Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com> Tested-by: Peter Senna Tschudin <peter.senna@collabora.com> |
#
eeb5b1ad |
|
10-Mar-2016 |
Stuart Yoder <stuart.yoder@nxp.com> |
pci: make pci_get_hose_head() available to external users Put pci_get_hose_head() prototype in header so it is available to external users, allowing them to find and iterate over all pci controllers. Signed-off-by: Stuart Yoder <stuart.yoder@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
4974a6ff |
|
06-Mar-2016 |
Simon Glass <sjg@chromium.org> |
pci: Correct a few comments and nits Two comments are missing a parameter and there is an extra blank line. Also two of the region access macros are misnamed. Correct these problems. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
319dba1f |
|
06-Mar-2016 |
Simon Glass <sjg@chromium.org> |
pci: Add functions to update PCI configuration registers It is common to read a config register value, clear and set some bits, then write back the updated value. Add functions to do this in one step, for convenience. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
308143ef |
|
02-Feb-2016 |
Bin Meng <bmeng.cn@gmail.com> |
dm: pci: Add missing forward declarations When CONFIG_DM_PCI_COMPAT is not on, there is only a forward declaration for pci_write_config32(). Add other missing ones. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
9d731c82 |
|
18-Jan-2016 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to write a BAR Add a driver-model version of the pci_write_bar32 function so that this is supported in the new API. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
7e78b9ef |
|
29-Nov-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Switch to DM API for PCI address mapping We should use the new address mapping functions unless we are in compatibility mode. Disable the old functions by default. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
21d1fe7e |
|
29-Nov-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add driver model API functions for address mapping At present the PCI address map functions use the old API. Add new functions for this so that drivers can be converted. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
bab17cf1 |
|
29-Nov-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR Add a driver-model function for reading the PCI BAR from a device. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
a0eb8356 |
|
29-Nov-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a driver-model version of pci_find_class() Add a function which scans the driver model device information rather than scanning the PCI bus again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> |
#
5c0bf647 |
|
29-Nov-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a driver-model version of pci_find_device() Add a function which scans the driver model device information rather than scanning the PCI bus again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> |
#
5e23b8b4 |
|
29-Nov-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Use driver model PCI API in auto-config At present we are using legacy functions even in the auto-configuration code used by driver model. Add a new pci_auto.c version which uses the correct API. Create a new pci_internal.h header to hold functions that are used within the PCI subsystem, but are not exported to other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> |
#
f3f1faef |
|
29-Nov-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a dm_ prefix to pci_bus_find_bdf() Most driver model PCI functions have a dm_ prefix. At some point, when the old code is converted to driver model and the old functions are removed, we will drop that prefix. For consistency, we should use the dm_ prefix for all driver model functions. Update pci_bus_find_bdf() accordingly. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
21ccce1b |
|
29-Nov-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a dm_ prefix to pci_get_bdf() Most driver model PCI functions have a dm_ prefix. At some point, when the old code is converted to driver model and the old functions are removed, we will drop that prefix. For consistency, we should use the dm_ prefix for all driver model functions. Update pci_get_bdf() accordingly. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
3ba5f74a |
|
26-Nov-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Disable PCI compatibility functions by default We eventually need to drop the compatibility functions for driver model. As a first step, create a configuration option to enable them and hide them when the option is disabled. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
54fe7b1c |
|
26-Nov-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a comment about how to find struct pci_controller With driver mode, struct pci_controller is stored as uclass-private data. Add a comment to that effect. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
f9260336 |
|
19-Nov-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to find the regions for a PCI bus This function looks up the controller and returns a pointer to each region type. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Stephen Warren <swarren@nvidia.com> Tested-by: Stephen Warren <swarren@nvidia.com> |
#
9f60fb0d |
|
19-Nov-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to get the controller for a bus A PCI bus may be a bridge device where the controller is the bridge's parent. Add a function to return the controller device, given a PCI device. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Stephen Warren <swarren@nvidia.com> Tested-by: Stephen Warren <swarren@nvidia.com> |
#
9289db6c |
|
19-Nov-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add functions to emulate 8- and 16-bit access Provide a few functions to support using 32-bit access to emulate 8- and 16-bit access. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Stephen Warren <swarren@nvidia.com> Tested-by: Stephen Warren <swarren@nvidia.com> |
#
bcbe3d15 |
|
28-Sep-2015 |
Simon Glass <sjg@chromium.org> |
dm: Rename dev_get_parentdata() to dev_get_parent_priv() The current name is inconsistent with other driver model data access functions. Rename it and fix up all users. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Joe Hershberger <joe.hershberger@ni.com> |
#
dc5740df |
|
22-Aug-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a comment to help find pci_hose_read_config_byte, etc. These functions are defined by macros so do not show up with grep. Add a comment to help. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
76c3fbcd |
|
10-Aug-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a way to iterate through all PCI devices These functions allow iteration through all PCI devices including bridges. The children of each PCI bus are returned in turn. This can be useful for configuring, checking or enumerating all the devices. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
66afb4ed |
|
10-Aug-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Provide friendly config access functions At present there are no PCI functions which allow access to PCI configuration using a struct udevice. This is a sad situation for driver model as it makes use of PCI harder. Add these functions. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
5f48d798 |
|
27-Jul-2015 |
Simon Glass <sjg@chromium.org> |
pci: Add a constant for an invalid interrupt Rather than using 0xff in the code, add a constant. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
ed5b580b |
|
09-Jul-2015 |
Minghuan Lian <Minghuan.Lian@freescale.com> |
drivers/pci: Add function to find an extended capability PCIe extends device's configuration space to 4k and provides extended capability. The patch adds function to find them. The code is ported from Linux PCIe driver. Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
4b515e4f |
|
06-Jul-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to get the BDF for a device It is useful to be able to find the full PCI address (bus, device and function) for a PCI device. Add a function to provide this. Adjust the existing code to use this. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
aba92962 |
|
06-Jul-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add support for PCI driver matching At present all PCI devices must be present in the device tree in order to be used. Many or most PCI devices don't require any configuration other than that which is done automatically by U-Boot. It is inefficent to add a node with nothing but a compatible string in order to get a device working. Add a mechanism whereby PCI drivers can be declared along with the device parameters they support (vendor/device/class). When no suitable driver is found in the device tree the list of such devices is consulted to determine the correct driver. If this also fails, then a generic driver is used as before. The mechanism used is very similar to that provided by Linux and the header file defintions are copied from Linux 4.1. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Joe Hershberger <joe.hershberger@ni.com> |
#
6c89663c |
|
07-Jul-2015 |
Bin Meng <bmeng.cn@gmail.com> |
pci: Configure expansion ROM during auto config process Currently PCI expansion ROM address is assigned by a call to pciauto_setup_rom() outside of the pci auto config process. This does not work when expansion ROM is on a device behind PCI bridge where bridge's memory limit register was already programmed to a value that does not cover the newly assigned expansion ROM address. To fix this, we should configure the ROM address during the auto config process. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Acked-by: Simon Glass <sjg@chromium.org> |
#
aec241df |
|
07-Jun-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Use the correct hose when configuring devices Only the PCI controller has access to the PCI region information. Make sure to use the controller (rather than any attached bridges) when configuring devices. This corrects a failure to scan and configure devices when driver model is enabled for PCI. Also add a comment to explain the problem. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
36d0d3b4 |
|
05-Mar-2015 |
Simon Glass <sjg@chromium.org> |
dm: sandbox: pci: Add a PCI emulation uclass Since sandbox does not have real devices (unless it borrows those from the host) it must use emulations. Provide a uclass which permits PCI operations to be passed through to an emulation device. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
ff3e077b |
|
05-Mar-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a uclass for PCI Add a uclass for PCI controllers and a generic one for PCI devices. Adjust the 'pci' command and the existing PCI support to work with this new uclass. Keep most of the compatibility code in a separate file so that it can be removed one day. TODO: Add more header file comments to the new parts of pci.h Signed-off-by: Simon Glass <sjg@chromium.org> |
#
aab6724c |
|
05-Mar-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move common PCI functions into their own file Driver model will share many functions with the existing PCI implementation. Move these into their own file to avoid duplication and confusion. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
250e039d |
|
27-Jan-2015 |
Simon Glass <sjg@chromium.org> |
pci: Add a function to find a device by class There is an existing function prototype in the header file but it is not implemented. Implement something similar. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
4a2708a0 |
|
14-Jan-2015 |
Simon Glass <sjg@chromium.org> |
x86: Access the VGA ROM when needed Add code to the generic pci_rom file to access the VGA ROM in PCI space when needed. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
d622ac39 |
|
15-Dec-2014 |
Masahiro Yamada <yamada.m@jp.panasonic.com> |
powerpc: mpc824x: remove MPC824X cpu support All the MPC824X boards are still non-generic boards: A3000, CPC45, CU824, eXalion, MVBLUE, MUSENKI, Sandpoint824x, utx8245 Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Josef Wagner <Wagner@Microsys.de> Cc: Torsten Demke <torsten.demke@fci.com> Cc: Jim Thompson <jim@musenki.com> Cc: Greg Allen <gallen@arlut.utexas.edu> |
#
e8a552eb |
|
14-Nov-2014 |
Simon Glass <sjg@chromium.org> |
pci: Add functions to read and write a BAR address Some PCI functions cannot be auto-configured. Add a function to set up a fixed BAR which can be used in these situations. Also add a function to read the current address of a BAR. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
4efe52bf |
|
12-Nov-2014 |
Thierry Reding <treding@nvidia.com> |
pci: Honour pci_skip_dev() When enumerating devices, honour the pci_skip_dev() function. This can be used by PCI controller drivers to restrict which devices will be probed. This is required by the NVIDIA Tegra PCIe controller driver, which will fail with a data abort exception if an access is attempted to a device number larger than 0 outside of bus 0. pci_skip_dev() is therefore implemented to prevent any such accesses. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Simon Glass <sjg@chromium.org> |
#
0991866c |
|
07-Aug-2014 |
Tim Harvey <tharvey@gateworks.com> |
pci: add support for board_pci_fixup_dev function Some board-level drivers may wish to have per-device fixup functions for PCI devices. Signed-off-by: Tim Harvey <tharvey@gateworks.com> |
#
fa5cec03 |
|
08-Nov-2013 |
Paul Burton <paul.burton@mips.com> |
pci.h: allow inclusion in assembly source This patch simply #ifdef's out the C-specific parts of pci.h when it is included by an assembly file. This will allow the macros it contains to be used from assembly source as will be done in a followup commit adding support for more modern MIPS Malta boards. Signed-off-by: Paul Burton <paul.burton@imgtec.com> |
#
287df01e |
|
11-Oct-2013 |
Zhao Qiang <B45475@freescale.com> |
PCIe:change the method to get the address of a requested capability in configuration space. Previously, the address of a requested capability is define like that "#define PCI_DCR 0x78" But, the addresses of capabilities is different with regard to PCIe revs. So this method is not flexible. Now a function to get the address of a requested capability is added and used. It can get the address dynamically by capability ID. The step of this function: 1. Read Status register in PCIe configuration space to confirm that Capabilities List is valid. 2. Find the address of Capabilities Pointer Register. 3. Find the address of requested capability from the first capability. Signed-off-by: Zhao Qiang <B45475@freescale.com> |
#
7b4e5844 |
|
03-Jul-2013 |
Zang Roy-R61911 <tie-fei.zang@freescale.com> |
powerpc/pcie: add PCIe version 3.x support T4240 PCIe IP is version 3.0 and has some update comparing previous QorIQ products. 1. Move Freescale specific register define to arch/powerpc/include/asm/fsl_pci.h and update the register offset define for T4240. 2. add the status/control register define use status/control register to judge the link status 3. The original code uses 'Programming Interface' field to judge if PCIE is EP or RC mode, however, T4240 does not support this functionality. According to PCIE specification, 'Header Type' offset 0x0e is used to indicate header type, so for PCIE controller, the patch changes code to use 'Header Type' field to identify if the PCIE is RC or EP mode. This patch fixes the PCIe card link up issue on T4240QDS. Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com> |
#
1a459660 |
|
08-Jul-2013 |
Wolfgang Denk <wd@denx.de> |
Add GPL-2.0+ SPDX-License-Identifier to source files Signed-off-by: Wolfgang Denk <wd@denx.de> [trini: Fixup common/cmd_io.c] Signed-off-by: Tom Rini <trini@ti.com> |
#
bc3442aa |
|
11-Jun-2013 |
Simon Glass <sjg@chromium.org> |
pci: Convert extern inline functions to static inline I am not sure of the meaning of extern inline, but this gives errors when building with function instrumenting enabled. Change these functions to static inline. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
842033e6 |
|
30-May-2013 |
Gabor Juhos <juhosg@openwrt.org> |
pci: introduce CONFIG_PCI_INDIRECT_BRIDGE option The pci_indirect.c file is always compiled when CONFIG_PCI is defined although the indirect PCI bridge support is not needed by every board. Introduce a new CONFIG_PCI_INDIRECT_BRIDGE config option and only compile indirect PCI bridge support if this options is enabled. Also add the new option into the configuration files of the boards which needs that. Compile tested for powerpc, x86, arm and nds32. MAKEALL results: powerpc: --------------------- SUMMARY ---------------------------- Boards compiled: 641 Boards with warnings but no errors: 2 ( ELPPC MPC8323ERDB ) ---------------------------------------------------------- Note: the warnings for ELPPC and MPC8323ERDB are present even without the actual patch. x86: --------------------- SUMMARY ---------------------------- Boards compiled: 1 ---------------------------------------------------------- arm: --------------------- SUMMARY ---------------------------- Boards compiled: 311 ---------------------------------------------------------- nds32: --------------------- SUMMARY ---------------------------- Boards compiled: 3 ---------------------------------------------------------- Cc: Tom Rini <trini@ti.com> Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com> Signed-off-by: Gabor Juhos <juhosg@openwrt.org> |
#
55ae10f8 |
|
20-Oct-2012 |
Bill Richardson <wfrichar@chromium.org> |
x86: gpio: Add GPIO driver for Intel ICH6 and later. Implement <asm-generic/gpio.h> functions for Intel ICH6 and later. Only GPIOs 0-31 are handled by this code. Signed-off-by: Bill Richardson <wfrichar@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org> |
#
a3a70725 |
|
24-Mar-2012 |
Linus Walleij <linus.walleij@linaro.org> |
pci: declare pciauto functions in header The FSL PCI driver uses local prototypes for pciauto_[pre|post]scan_setup_bridge(), this does not seem right, so move them to the <pci.h> file. Fixed a small extern declaration too, this is harmless but distracts the view since all other prototypes are explicitly external. Signed-off-by: Linus Walleij <linus.walleij@linaro.org> |
#
a1e47b66 |
|
03-Mar-2012 |
Linus Walleij <linus.walleij@linaro.org> |
pci: move pciauto_config_init() to pci.h Fixing build regressions for the Integrator I get find that a few boards try to work around the missing declaration of pciauto_config_init() by declaring it in the local scope. This does not make sense when the sibling functions are in <pci.h> so move the function to the header, ridding the build error in the Integrator and getting rid of the local declarations here and there. Reported-by: Wolfgang Denk <wd@denx.de> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> |
#
b03a466d |
|
01-Feb-2011 |
Prabhakar Kushwaha <prabhakar@freescale.com> |
powerpc/85xx: Handle PCIe initialization requires for P1021 class SoCs The P1011, P1012, P1015, P1016, P1020, P1021, P1024, & P1025 SoCs require that we initialize the SERDES registers if the lanes are configured for PCIe. Additionally these devices PCIe controller do not support ASPM and we have to explicitly disable it. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
10fa8d7c |
|
19-Jan-2011 |
Leo Liu <liucai.lfn@gmail.com> |
mpc83xx: fix pcie configuration space read/write This patch fix a problem for the pcie enumeration when the mpc83xx pcie controller is connected with switch or we use both of the two pcie controller. Signed-off-by: Leo Liu <liucai.lfn@gmail.com> fix codingstyle and compiler warning: 'pcie_priv' defined but not used Signed-off-by: Kim Phillips <kim.phillips@freescale.com> |
#
3a0e3c27 |
|
17-Dec-2010 |
Kumar Gala <galak@kernel.crashing.org> |
powerpc/fsl-pci: Determine pci_controller based on cfg addr for dts fixup Previously we passed in a specifically named struct pci_controller to determine if we had setup the particular PCI bus. Now we can search for the struct so we dont have to depend on the name or the struct being statically allocated. Introduced new find_hose_by_cfg_addr() to get back a pci_controller struct back by searching for it means we can do things like dynamically allocate them or not have to expose the static structures to all users. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Wolfgang Denk <wd@denx.de> |
#
983eb9d1 |
|
29-Oct-2010 |
Peter Tyser <ptyser@xes-inc.com> |
pci: Clean up PCI info when CONFIG_PCI_SCAN_SHOW This change does the following: - Removes the printing of the PCI interrupt line value. This is normally set to 0 by U-Boot on bootup and is rarely used during everyday operation. - Prints out the PCI function number of a device. Previously a device with multiple functions would be printed identically 2 times, which is generally confusing. For example, on an Intel 2 port gigabit Ethernet card the following was displayed: ... 04 01 8086 1010 0200 00 04 01 8086 1010 0200 00 ... - Prints a text description of each device's PCI class instead of the raw PCI class code. The textual description makes it much easier to determine what devices are installed on a PCI bus. - Changes the general formatting of the PCI device output. Previous output: PCIE1: connected as Root Complex 04 01 8086 1010 0200 00 04 01 8086 1010 0200 00 03 00 10b5 8112 0604 00 02 01 10b5 8518 0604 00 02 02 10b5 8518 0604 00 08 00 1957 0040 0b20 00 07 00 10b5 8518 0604 00 09 00 10b5 8112 0604 00 07 01 10b5 8518 0604 00 07 02 10b5 8518 0604 00 06 00 10b5 8518 0604 00 02 03 10b5 8518 0604 00 01 00 10b5 8518 0604 00 PCIE1: Bus 00 - 0b PCIE2: connected as Root Complex 0d 00 1957 0040 0b20 00 PCIE2: Bus 0c - 0d Updated output: PCIE1: connected as Root Complex 04:01.0 - 8086:1010 - Network controller 04:01.1 - 8086:1010 - Network controller 03:00.0 - 10b5:8112 - Bridge device 02:01.0 - 10b5:8518 - Bridge device 02:02.0 - 10b5:8518 - Bridge device 08:00.0 - 1957:0040 - Processor 07:00.0 - 10b5:8518 - Bridge device 09:00.0 - 10b5:8112 - Bridge device 07:01.0 - 10b5:8518 - Bridge device 07:02.0 - 10b5:8518 - Bridge device 06:00.0 - 10b5:8518 - Bridge device 02:03.0 - 10b5:8518 - Bridge device 01:00.0 - 10b5:8518 - Bridge device PCIE1: Bus 00 - 0b PCIE2: connected as Root Complex 0d:00.0 - 1957:0040 - Processor PCIE2: Bus 0c - 0d Signed-off-by: Peter Tyser <ptyser@xes-inc.com> |
#
8295b944 |
|
05-Aug-2009 |
Kumar Gala <galak@kernel.crashing.org> |
pci/fsl_pci_init: Use PCIe capability to determine if controller is PCIe Change the code to use the PCIe capabilities register to determine if we are a PCIe controller or not. Additionally cleaned up some white space and formatting in the file. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
cc2a8c77 |
|
19-Feb-2009 |
Anton Vorontsov <avorontsov@ru.mvista.com> |
PCI: Add pci_last_busno() helper This is just a handy routine that reports last PCI busno: we walk down all the hoses and return last hose's last_busno. Will be used by PCI/PCIe initialization code. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com> |
#
6e61fae4 |
|
03-Feb-2009 |
Becky Bruce <beckyb@kernel.crashing.org> |
drivers/pci: Create pci_map_bar function It is no longer always true that the pci bus address can be used as the virtual address for pci accesses. pci_map_bar() is created to return the virtual address for a pci region. Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org> |
#
ff4e66e9 |
|
06-Feb-2009 |
Kumar Gala <galak@kernel.crashing.org> |
pci: Rename PCI_REGION_MEMORY to PCI_REGION_SYS_MEMORY for clarity The PCI_REGION_MEMORY and PCI_REGION_MEM are a bit to similar and can be confusing when reading the code. Rename PCI_REGION_MEMORY to PCI_REGION_SYS_MEMORY to clarify its used for system memory mapping purposes. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
fd6646c0 |
|
07-Jan-2009 |
Anton Vorontsov <avorontsov@ru.mvista.com> |
mpc83xx: Add support for MPC83xx PCI-E controllers This patch adds support for MPC83xx PCI-E controllers in Root Complex mode. The patch is based on Tony Li and Dave Liu work[1]. Though unlike the original patch, by default we don't register PCI-E buses for use in U-Boot, we only configure the controllers for future use in other OSes (Linux). This is done because we don't have enough of spare BATs to map all the PCI-E regions. To actually use PCI-E in U-Boot, users should explicitly define CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES symbol in the board file. And only then U-Boot will able to access PCI-E, but at the cost of disabled address translation. [1] http://lists.denx.de/pipermail/u-boot/2008-January/027630.html Signed-off-by: Tony Li <tony.li@freescale.com> Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Acked-by: Dave Liu <daveliu@freescale.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com> |
#
30e76d5e |
|
21-Oct-2008 |
Kumar Gala <galak@kernel.crashing.org> |
pci: Allow for PCI addresses to be 64-bit PCI bus is inherently 64-bit. While not all system require access to the full 64-bit PCI address range some do. This allows those systems to enable the full PCI address width via CONFIG_SYS_PCI_64BIT. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Andrew Fleming-AFLEMING <afleming@freescale.com> Acked-by: Wolfgang Denk <wd@denx.de> |
#
36f32675 |
|
07-May-2008 |
Becky Bruce <bgill@freescale.com> |
Update pci code to use phys_addr_t Physical addrs need to be represented by phys_addr_t, not unsigned long. Otherwise, systems that use CONFIG_PHYS_64BIT are going to fail mightily. Signed-off-by: Becky Bruce <becky.bruce@freescale.com> |
#
63cec581 |
|
02-Aug-2007 |
Ed Swarthout <Ed.Swarthout@freescale.com> |
Make MPC8641's PCI/PCI-E driver a common driver for many FSL parts. All of the PCI/PCI-Express driver and initialization code that was in the MPC8641HPCN port has now been moved into the common drivers/fsl_pci_init.c. In a subsequent patch, this will be utilized by the 85xx ports as well. Common PCI-E IMMAP register blocks for FSL 85xx/86xx are added. Also enable the second PCI-Express controller on 8641 by getting its BATS and CFG_ setup right. Fixed a u16 vendor compiler warning in AHCI driver too. Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com> Signed-off-by: Zhang Wei <wei.zhang@freescale.com> Signed-off-by: Jon Loeliger <jdl@freescale.com> |
#
13a7fcdf |
|
19-Oct-2006 |
Jon Loeliger <jdl@freescale.com> |
* Fix a bunch of compiler warnings for gcc 4.0 Signed-off-by: Matthew McClintock <msm@freescale.com> |
#
f0e6f57f |
|
28-Jun-2006 |
Matthew McClintock <msm@freescale.com> |
* Added PCI-X #defines for PCI-X initialization Patch by Andy Fleming on 17-Mar-2006 Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
7b230f61 |
|
12-Mar-2006 |
Wolfgang Denk <wd@pollux.denx.de> |
Merge with git://git.kernel.org/pub/scm/boot/u-boot/u-boot.git#pci
|
#
993a2275 |
|
12-Mar-2006 |
Wolfgang Denk <wd@pollux.denx.de> |
Fix bad declaration on pci_cfgfunc_nothing Patch by Sam Song, 19 Jun 2005 |
#
a179012e |
|
11-Jan-2006 |
Kumar Gala <galak@kernel.crashing.org> |
Added support for PCI prefetchable region and BARs If a host controller sets up a region as prefetchable and a device's BAR denotes it as prefetchable, allocate the BAR into the prefetch region. If a BAR is prefetchable and no prefetchable region has been setup by the controller we fall back to allocating the BAR into the normally memory region. Patch by Kumar Gala 11 Jan 2006 |
#
c157d8e2 |
|
01-Aug-2005 |
Stefan Roese <sr@denx.de> |
Add support for AMCC PPC440EP/GR eval boards Yosemite and Yellowstone. Patch by Steven Blakeslee, 27 Jul 2005 |
#
7a8e9bed |
|
31-May-2003 |
Wolfgang Denk <wdenk> |
* Patch by Marc Singer, 29 May 2003: Fixed rarp boot method for IA32 and other little-endian CPUs. * Patch by Marc Singer, 28 May 2003: Added port I/O commands. * Patch by Matthew McClintock, 28 May 2003 - cpu/mpc824x/start.S: fix relocation code when booting from RAM - minor patches for utx8245 * Patch by Daniel Engstr�m, 28 May 2003: x86 update * Patch by Dave Ellis, 9 May 2003 + 27 May 2003: add nand flash support to SXNI855T configuration fix/extend nand flash support: - fix 'nand erase' command so does not erase bad blocks - fix 'nand write' command so does not write to bad blocks - fix nand_probe() so handles no flash detected properly - add doc/README.nand - add .jffs2 and .oob options to nand read/write - add 'nand bad' command to list bad blocks - add 'clean' option to 'nand erase' to write JFFS2 clean markers - make NAND read/write faster * Patch by Rune Torgersen, 23 May 2003: Update for MPC8266ADS board |
#
c7de829c |
|
19-Nov-2002 |
Wolfgang Denk <wdenk> |
* Patch by Thomas Frieden, 13 Nov 2002: Add code for AmigaOne board (preliminary merge to U-Boot, still WIP) * Patch by Jon Diekema, 12 Nov 2002: - Adding URL for IEEE OUI lookup - Making the autoboot #defines dependent on CONFIG_AUTOBOOT_KEYED being defined. - In the CONFIG_EXTRA_ENV_SETTINGS #define, the root-on-initrd and root-on-nfs macros are designed to switch how the default boot method gets defined. |
#
c609719b |
|
02-Nov-2002 |
Wolfgang Denk <wdenk> |
Initial revision |
#
185f812c |
|
19-Jan-2022 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
doc: replace @return by Return: Sphinx expects Return: and not @return to indicate a return value. find . -name '*.c' -exec \ sed -i 's/^\(\s\)\*\(\s*\)@return\(\s\)/\1*\2Return:\3/' {} \; find . -name '*.h' -exec \ sed -i 's/^\(\s\)\*\(\s*\)@return\(\s\)/\1*\2Return:\3/' {} \; Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> |
#
a398a51c |
|
20-Nov-2021 |
Maciej W. Rozycki <macro@orcam.me.uk> |
pci: Work around PCIe link training failures Attempt to handle cases with a downstream port of a PCIe switch where link training never completes and the link continues switching between speeds indefinitely with the data link layer never reaching the active state. It has been observed with a downstream port of the ASMedia ASM2824 Gen 3 switch wired to the upstream port of the Pericom PI7C9X2G304 Gen 2 switch, using a Delock Riser Card PCI Express x1 > 2 x PCIe x1 device, P/N 41433, wired to a SiFive HiFive Unmatched board. In this setup the switches are supposed to negotiate the link speed of preferably 5.0GT/s, falling back to 2.5GT/s. However the link continues oscillating between the two speeds, at the rate of 34-35 times per second, with link training reported repeatedly active ~84% of the time, e.g.: 02:03.0 PCI bridge [0604]: ASMedia Technology Inc. ASM2824 PCIe Gen3 Packet Switch [1b21:2824] (rev 01) (prog-if 00 [Normal decode]) [...] Bus: primary=02, secondary=05, subordinate=05, sec-latency=0 [...] Capabilities: [80] Express (v2) Downstream Port (Slot+), MSI 00 [...] LnkSta: Speed 5GT/s (downgraded), Width x1 (ok) TrErr- Train+ SlotClk+ DLActive- BWMgmt+ ABWMgmt- [...] LnkCtl2: Target Link Speed: 8GT/s, EnterCompliance- SpeedDis+, Selectable De-emphasis: -3.5dB Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS- Compliance De-emphasis: -6dB [...] Forcibly limiting the target link speed to 2.5GT/s with the upstream ASM2824 device makes the two switches communicate correctly however: 02:03.0 PCI bridge [0604]: ASMedia Technology Inc. ASM2824 PCIe Gen3 Packet Switch [1b21:2824] (rev 01) (prog-if 00 [Normal decode]) [...] Bus: primary=02, secondary=05, subordinate=09, sec-latency=0 [...] Capabilities: [80] Express (v2) Downstream Port (Slot+), MSI 00 [...] LnkSta: Speed 2.5GT/s (downgraded), Width x1 (ok) TrErr- Train- SlotClk+ DLActive+ BWMgmt- ABWMgmt- [...] LnkCtl2: Target Link Speed: 2.5GT/s, EnterCompliance- SpeedDis+, Selectable De-emphasis: -3.5dB Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS- Compliance De-emphasis: -6dB [...] and then: 05:00.0 PCI bridge [0604]: Pericom Semiconductor PI7C9X2G304 EL/SL PCIe2 3-Port/4-Lane Packet Switch [12d8:2304] (rev 05) (prog-if 00 [Normal decode]) [...] Bus: primary=05, secondary=06, subordinate=09, sec-latency=0 [...] Capabilities: [c0] Express (v2) Upstream Port, MSI 00 [...] LnkSta: Speed 2.5GT/s (downgraded), Width x1 (downgraded) TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt- [...] LnkCtl2: Target Link Speed: 5GT/s, EnterCompliance- SpeedDis- Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS- Compliance De-emphasis: -6dB [...] Make use of this observation then and attempt to detect the inability to negotiate the link speed automatically, and then handle it by hand. Use the Data Link Layer Link Active status flag as the primary indicator of successful link speed negotiation, but given that the flag is optional by hardware to implement (the ASM2824 does have it though), resort to checking for the mandatory Link Bandwidth Management Status flag showing that the link speed or width has been changed in an attempt to correct unreliable link operation (the ASM2824 does set it too). If these checks indicate that link may not operate correctly, then poll the Data Link Layer Link Active status flag along with the Link Training flag for the duration of 200ms to see if the link has stabilised, that is either that the Data Link Layer Link Active status flag has been set or that Link Training has been inactive during at least the second half of the interval. If that has indicated failure, restrict the target speed to 2.5GT/s, request a link retrain and check again if the link has stabilised. If that does not work either, then restore the original speed setting and claim defeat, otherwise we are done. NB interestingly enough with the ASM2824 vs PI7C9X2G304 configuration referred above asking the ASM2824 to retrain with a higher target link speed once the 2.5GT/s speed has been negotiated makes the two devices successfully negotiate 5.0GT/s. Lifting the 2.5GT/s speed restriction would however prevent our workaround from working with an OS that issues a reset and that is unaware of the problem. This is because the devices would then try to negotiate a higher link speed from scratch and fail, while the sticky property of the Target Link Speed setting will keep the 2.5GT/s speed restriction across a reset. Keep the 2.5GT/s speed restriction then, conservatively, if functional once applied. Signed-off-by: Maciej W. Rozycki <macro@orcam.me.uk> Reviewed-by: Stefan Roese <sr@denx.de> |
#
2a8d4025 |
|
26-Nov-2021 |
Pali Rohár <pali@kernel.org> |
pci: Add standard PCI Config Address macros Lot of PCI and PCIe controllers are using standard Config Address for PCI Configuration Mechanism #1 or its extended version. So add PCI_CONF1_ADDRESS() and PCI_CONF1_EXT_ADDRESS() macros into U-Boot's pci.h header file which can be suitable for most PCI and PCIe controller drivers. Drivers do not have to invent their own macros and can use these new U-Boot macros. Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
a4bc38da |
|
02-Nov-2021 |
Pali Rohár <pali@kernel.org> |
pci: Add standard PCIe ECAM macros Lot of PCIe controllers are using ECAM addressing. So add common ECAM macros into U-Boot's pci.h header file which can be suitable for most PCI controller drivers. Replace custom ECAM address macros in every PCI controller driver by new ECAM macros from U-Boot's pci.h header file. Similar macros are defined also in Linux kernel. There is a small difference between Linux and these new U-Boot macros. U-Boot's PCIE_ECAM_OFFSET() takes device and function numbers in separate arguments. Linux's PCIE_ECAM_OFFSET() takes device and function numbers encoded in one argument. The reason is that U-Boot's PCI_DEVFN() macro is different than Linux's PCI_SLOT() macro. So having device and function numbers in separate arguments makes code more straightforward. Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Stefan Roese <sr@denx.de> |
#
1d7ad685 |
|
25-Sep-2021 |
Pali Rohár <pali@kernel.org> |
arm: a37xx: pci: Handle propagation of CRSSVE bit from PCIe Root Port Now that PCI Bridge (PCIe Root Port) for Aardvark is emulated in U-Boot, add support for handling and propagation of CRSSVE bit. When CRSSVE bit is unset (default), driver has to reissue config read/write request on CRS response. CRSSVE bit is supported only when CRSVIS bit is provided in read-only Root Capabilities register. So manually inject this CRSVIS bit into read response for that register. Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Stefan Roese <sr@denx.de> |
#
2649f69f |
|
17-Sep-2021 |
Vladimir Oltean <vladimir.oltean@nxp.com> |
pci: provide prototype for pci_skip_dev outside of #if defined(CONFIG_DM_PCI_COMPAT) The weak definition of pci_skip_dev from drivers/pci/pci_common.c is not under CONFIG_DM_PCI_COMPAT, and that definition needs a previous function prototype declaration to avoid W=1 build warnings. That prototype is not available due to it being under CONFIG_DM_PCI_COMPAT, so move it outside of that preprocessor block. Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
23cacd57 |
|
01-Aug-2021 |
Simon Glass <sjg@chromium.org> |
pci: Drop PCI_INDIRECT_BRIDGE This does not work with driver model so can be removed. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
26543cc6 |
|
01-Aug-2021 |
Simon Glass <sjg@chromium.org> |
pci: Drop old code from header file We don't need this code anymore since when PCI is enabled, driver model is always used. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
63814a69 |
|
01-Aug-2021 |
Simon Glass <sjg@chromium.org> |
pci: imx: Drop DM_PCI check from cpu driver We don't need this check anymore since when PCI is enabled, driver model is always used. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
e8c09d69 |
|
01-Aug-2021 |
Simon Glass <sjg@chromium.org> |
pci: Remove guard around compatibility functions This prevents use of IS_ENABLED() in other files. Functions should be visible in headers even if they are not available at link time. Fix it. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
f5cbb5c7 |
|
27-Jun-2021 |
Simon Glass <sjg@chromium.org> |
x86: pci: Allow binding of some devices before relocation At present only bridge devices are bound before relocation, to save space in pre-relocation memory. In some cases we do actually want to bind a device, e.g. because it provides the console UART. Add a devicetree binding to support this. Use the PCI_VENDEV() macro to encode the cell value. This is present in U-Boot but not used, so move it to the binding header-file. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
e58f3a7d |
|
27-Jun-2021 |
Simon Glass <sjg@chromium.org> |
pci: Use const for pci_find_device_id() etc. These functions don't modify the device-ID struct that is passed in, so mark the argument as const, so the data structure can be declared that way. This allows it to be placed in the rodata section. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
c7b36007 |
|
14-May-2021 |
Tom Rini <trini@konsulko.com> |
pci: Remove non-DM board_pci_fixup_dev() declaration With the ventana boards migrated to DM_PCI and DM_ETH, we can remove this prototype. Cc: Stefano Babic <sbabic@denx.de> Signed-off-by: Tom Rini <trini@konsulko.com> |
#
cecd013f |
|
16-Apr-2021 |
Tim Harvey <tharvey@gateworks.com> |
pci: pci-uclass: Add board_pci_fixup_dev for DM_PCI Add a board_pci_fixup_dev weak function to allow PCI device fixups during enumeration. Signed-off-by: Tim Harvey <tharvey@gateworks.com> |
#
8b85dfc6 |
|
16-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: Avoid accessing seq directly At present various drivers etc. access the device's 'seq' member directly. This makes it harder to change the meaning of that member. Change access to go through a function instead. The drivers/i2c/lpc32xx_i2c.c file is left unchanged for now. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
caa4daa2 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename 'platdata' variables to just 'plat' We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
284d062e |
|
09-Sep-2020 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
pci: add a few ARI related defines Add a few defines related to PCI ARI configuration. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
51eeae91 |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add VF BAR map support for Enhanced Allocation Makes dm_pci_map_bar API available to map BAR for Virtual function PCI devices which support Enhanced Allocation. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> |
#
b8852dcf |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add support for Single-Root I/O Virtualization SR-IOV - Single Root I/O Virtualization PF - Physical Function VF - Virtual Function If SR-IOV capability is present, use it to initialize Virtual Function PCI device instances. pci_sriov_init function will read SR-IOV registers to create VF devices under the PF PCI device and also bind driver if available. This function needs to be invoked from Physical function device driver which expects VF device support, creating minimal impact on existing framework. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> |
#
e0024741 |
|
23-Jul-2020 |
Stefan Roese <sr@denx.de> |
pci: pci-uclass: Dynamically allocate the PCI regions Instead of using a fixed length pre-allocated array of regions, this patch moves to dynamically allocating the regions based on the number of available regions plus the necessary regions for DRAM banks. Since MAX_PCI_REGIONS is not needed any more, its removed completely with this patch. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Thierry Reding <treding@nvidia.com> Cc: Marek Vasut <marek.vasut+renesas@gmail.com> |
#
143eb5b1 |
|
12-May-2020 |
Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
drivers: pci: add api to get dma regions Add api to get dma regions. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com> |
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com> |
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com> |
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
7d994067 |
|
23-Apr-2019 |
Tom Rini <trini@konsulko.com> |
Merge tag 'pull-24apr19' of git://git.denx.de/u-boot-dm Various minor sandbox iumprovements Fixes for tracing with sandbox Refactoring for boot_get_fdt()
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
a8c5f8d3 |
|
15-Oct-2018 |
Bin Meng <bmeng.cn@gmail.com> |
dm: pci: Add APIs to find next capability and extended capability This introduces two new APIs dm_pci_find_next_capability() and dm_pci_find_next_ext_capability() to get PCI capability address and PCI express extended capability address for a given PCI device starting from a given offset. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
dac01fd8 |
|
03-Aug-2018 |
Bin Meng <bmeng.cn@gmail.com> |
dm: pci: Add APIs to find capability and extended capability This introduces two new APIs dm_pci_find_capability() and dm_pci_find_ext_capability() to get PCI capability address and PCI express extended capability address for a given PCI device. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
5d544f96 |
|
03-Aug-2018 |
Bin Meng <bmeng.cn@gmail.com> |
pci: Add all known capability and extended capability ids Currently we don't have a complete list of capability and extended capability ids. This adds them. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
4345998a |
|
03-Aug-2018 |
Bin Meng <bmeng.cn@gmail.com> |
pci: sandbox: Support dynamically binding device driver At present all emulated sandbox pci devices must be present in the device tree in order to be used. The real world pci uclass driver supports pci device driver matching, and we should add such support on sandbox too. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
01259c93 |
|
03-Aug-2018 |
Bin Meng <bmeng.cn@gmail.com> |
pci: Remove 440ep-specific macros These macros should not be put in the generic pci.h header file. Since they are not referenced anywhere, remove them completely. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
5ce9aca8 |
|
14-May-2018 |
Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi> |
PCI: Document pciauto_region_allocate() Add a doc comment for pciauto_region_allocate(). Signed-off-by: Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
d71975ae |
|
14-May-2018 |
Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi> |
PCI: autoconfig: Don't allocate 64-bit addresses to 32-bit only resources Currently, if we happen to allocate an address requiring 64 bits to a device only supporting 32-bit BARs, the address eventually gets silently truncated to 32 bits. Avoid this by adding a new flag to pciauto_region_allocate() to bail out in such situations. Signed-off-by: Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
83d290c5 |
|
06-May-2018 |
Tom Rini <trini@konsulko.com> |
SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com> |
#
ed68ccbf |
|
13-Mar-2018 |
Stefan Roese <sr@denx.de> |
pci: Remove unused ppc4xx variable from struct pci_controller ppc4xx support was removed some time ago. Lets remove the now unused "pci_fb" variable from "struct pci_controller" as well. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Simon Glass <sjg@chromium.org> |
#
badb9922 |
|
19-Sep-2017 |
Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi> |
pci: Add helper for implementing memory-mapped config space accesses This sort of pattern for implementing memory-mapped PCI config space accesses appears in U-Boot twice already, and a third user is coming up. So add helper functions to avoid code duplication, similar to how Linux has pci_generic_config_write and pci_generic_config_read. Signed-off-by: Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
6ecbe137 |
|
12-May-2017 |
Tim Harvey <tharvey@gateworks.com> |
drivers: pci: imx: add imx_pcie_remove function There is no dedicated reset signal wired up for the MX6QDL thus if the bootloader enables the link we need some special handling to get the core back into a state where it is safe to touch it for configuration. While there has been some special handling in the Linux kernel to do this, it was removed in 4.11 thus we need to do it properly in the bootloader and therefore without this if you enable PCI in the bootloader you will hang while booting the 4.11 kernel. This puts the PCIe controller back into a safe state for the kernel driver before launching the kernel. Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com> Tested-by: Peter Senna Tschudin <peter.senna@collabora.com> |
#
eeb5b1ad |
|
10-Mar-2016 |
Stuart Yoder <stuart.yoder@nxp.com> |
pci: make pci_get_hose_head() available to external users Put pci_get_hose_head() prototype in header so it is available to external users, allowing them to find and iterate over all pci controllers. Signed-off-by: Stuart Yoder <stuart.yoder@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
4974a6ff |
|
06-Mar-2016 |
Simon Glass <sjg@chromium.org> |
pci: Correct a few comments and nits Two comments are missing a parameter and there is an extra blank line. Also two of the region access macros are misnamed. Correct these problems. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
319dba1f |
|
06-Mar-2016 |
Simon Glass <sjg@chromium.org> |
pci: Add functions to update PCI configuration registers It is common to read a config register value, clear and set some bits, then write back the updated value. Add functions to do this in one step, for convenience. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
308143ef |
|
02-Feb-2016 |
Bin Meng <bmeng.cn@gmail.com> |
dm: pci: Add missing forward declarations When CONFIG_DM_PCI_COMPAT is not on, there is only a forward declaration for pci_write_config32(). Add other missing ones. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
9d731c82 |
|
18-Jan-2016 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to write a BAR Add a driver-model version of the pci_write_bar32 function so that this is supported in the new API. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
7e78b9ef |
|
29-Nov-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Switch to DM API for PCI address mapping We should use the new address mapping functions unless we are in compatibility mode. Disable the old functions by default. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
21d1fe7e |
|
29-Nov-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add driver model API functions for address mapping At present the PCI address map functions use the old API. Add new functions for this so that drivers can be converted. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
bab17cf1 |
|
29-Nov-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR Add a driver-model function for reading the PCI BAR from a device. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
a0eb8356 |
|
29-Nov-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a driver-model version of pci_find_class() Add a function which scans the driver model device information rather than scanning the PCI bus again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> |
#
5c0bf647 |
|
29-Nov-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a driver-model version of pci_find_device() Add a function which scans the driver model device information rather than scanning the PCI bus again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> |
#
5e23b8b4 |
|
29-Nov-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Use driver model PCI API in auto-config At present we are using legacy functions even in the auto-configuration code used by driver model. Add a new pci_auto.c version which uses the correct API. Create a new pci_internal.h header to hold functions that are used within the PCI subsystem, but are not exported to other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> |
#
f3f1faef |
|
29-Nov-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a dm_ prefix to pci_bus_find_bdf() Most driver model PCI functions have a dm_ prefix. At some point, when the old code is converted to driver model and the old functions are removed, we will drop that prefix. For consistency, we should use the dm_ prefix for all driver model functions. Update pci_bus_find_bdf() accordingly. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
21ccce1b |
|
29-Nov-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a dm_ prefix to pci_get_bdf() Most driver model PCI functions have a dm_ prefix. At some point, when the old code is converted to driver model and the old functions are removed, we will drop that prefix. For consistency, we should use the dm_ prefix for all driver model functions. Update pci_get_bdf() accordingly. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
3ba5f74a |
|
26-Nov-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Disable PCI compatibility functions by default We eventually need to drop the compatibility functions for driver model. As a first step, create a configuration option to enable them and hide them when the option is disabled. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
54fe7b1c |
|
26-Nov-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a comment about how to find struct pci_controller With driver mode, struct pci_controller is stored as uclass-private data. Add a comment to that effect. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
f9260336 |
|
19-Nov-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to find the regions for a PCI bus This function looks up the controller and returns a pointer to each region type. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Stephen Warren <swarren@nvidia.com> Tested-by: Stephen Warren <swarren@nvidia.com> |
#
9f60fb0d |
|
19-Nov-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to get the controller for a bus A PCI bus may be a bridge device where the controller is the bridge's parent. Add a function to return the controller device, given a PCI device. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Stephen Warren <swarren@nvidia.com> Tested-by: Stephen Warren <swarren@nvidia.com> |
#
9289db6c |
|
19-Nov-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add functions to emulate 8- and 16-bit access Provide a few functions to support using 32-bit access to emulate 8- and 16-bit access. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Stephen Warren <swarren@nvidia.com> Tested-by: Stephen Warren <swarren@nvidia.com> |
#
bcbe3d15 |
|
28-Sep-2015 |
Simon Glass <sjg@chromium.org> |
dm: Rename dev_get_parentdata() to dev_get_parent_priv() The current name is inconsistent with other driver model data access functions. Rename it and fix up all users. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Joe Hershberger <joe.hershberger@ni.com> |
#
dc5740df |
|
22-Aug-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a comment to help find pci_hose_read_config_byte, etc. These functions are defined by macros so do not show up with grep. Add a comment to help. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
76c3fbcd |
|
10-Aug-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a way to iterate through all PCI devices These functions allow iteration through all PCI devices including bridges. The children of each PCI bus are returned in turn. This can be useful for configuring, checking or enumerating all the devices. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
66afb4ed |
|
10-Aug-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Provide friendly config access functions At present there are no PCI functions which allow access to PCI configuration using a struct udevice. This is a sad situation for driver model as it makes use of PCI harder. Add these functions. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
5f48d798 |
|
27-Jul-2015 |
Simon Glass <sjg@chromium.org> |
pci: Add a constant for an invalid interrupt Rather than using 0xff in the code, add a constant. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
ed5b580b |
|
09-Jul-2015 |
Minghuan Lian <Minghuan.Lian@freescale.com> |
drivers/pci: Add function to find an extended capability PCIe extends device's configuration space to 4k and provides extended capability. The patch adds function to find them. The code is ported from Linux PCIe driver. Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
4b515e4f |
|
06-Jul-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to get the BDF for a device It is useful to be able to find the full PCI address (bus, device and function) for a PCI device. Add a function to provide this. Adjust the existing code to use this. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
aba92962 |
|
06-Jul-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add support for PCI driver matching At present all PCI devices must be present in the device tree in order to be used. Many or most PCI devices don't require any configuration other than that which is done automatically by U-Boot. It is inefficent to add a node with nothing but a compatible string in order to get a device working. Add a mechanism whereby PCI drivers can be declared along with the device parameters they support (vendor/device/class). When no suitable driver is found in the device tree the list of such devices is consulted to determine the correct driver. If this also fails, then a generic driver is used as before. The mechanism used is very similar to that provided by Linux and the header file defintions are copied from Linux 4.1. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Joe Hershberger <joe.hershberger@ni.com> |
#
6c89663c |
|
07-Jul-2015 |
Bin Meng <bmeng.cn@gmail.com> |
pci: Configure expansion ROM during auto config process Currently PCI expansion ROM address is assigned by a call to pciauto_setup_rom() outside of the pci auto config process. This does not work when expansion ROM is on a device behind PCI bridge where bridge's memory limit register was already programmed to a value that does not cover the newly assigned expansion ROM address. To fix this, we should configure the ROM address during the auto config process. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Acked-by: Simon Glass <sjg@chromium.org> |
#
aec241df |
|
07-Jun-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Use the correct hose when configuring devices Only the PCI controller has access to the PCI region information. Make sure to use the controller (rather than any attached bridges) when configuring devices. This corrects a failure to scan and configure devices when driver model is enabled for PCI. Also add a comment to explain the problem. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
36d0d3b4 |
|
05-Mar-2015 |
Simon Glass <sjg@chromium.org> |
dm: sandbox: pci: Add a PCI emulation uclass Since sandbox does not have real devices (unless it borrows those from the host) it must use emulations. Provide a uclass which permits PCI operations to be passed through to an emulation device. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
ff3e077b |
|
05-Mar-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a uclass for PCI Add a uclass for PCI controllers and a generic one for PCI devices. Adjust the 'pci' command and the existing PCI support to work with this new uclass. Keep most of the compatibility code in a separate file so that it can be removed one day. TODO: Add more header file comments to the new parts of pci.h Signed-off-by: Simon Glass <sjg@chromium.org> |
#
aab6724c |
|
05-Mar-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move common PCI functions into their own file Driver model will share many functions with the existing PCI implementation. Move these into their own file to avoid duplication and confusion. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
250e039d |
|
27-Jan-2015 |
Simon Glass <sjg@chromium.org> |
pci: Add a function to find a device by class There is an existing function prototype in the header file but it is not implemented. Implement something similar. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
4a2708a0 |
|
14-Jan-2015 |
Simon Glass <sjg@chromium.org> |
x86: Access the VGA ROM when needed Add code to the generic pci_rom file to access the VGA ROM in PCI space when needed. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
d622ac39 |
|
15-Dec-2014 |
Masahiro Yamada <yamada.m@jp.panasonic.com> |
powerpc: mpc824x: remove MPC824X cpu support All the MPC824X boards are still non-generic boards: A3000, CPC45, CU824, eXalion, MVBLUE, MUSENKI, Sandpoint824x, utx8245 Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Josef Wagner <Wagner@Microsys.de> Cc: Torsten Demke <torsten.demke@fci.com> Cc: Jim Thompson <jim@musenki.com> Cc: Greg Allen <gallen@arlut.utexas.edu> |
#
e8a552eb |
|
14-Nov-2014 |
Simon Glass <sjg@chromium.org> |
pci: Add functions to read and write a BAR address Some PCI functions cannot be auto-configured. Add a function to set up a fixed BAR which can be used in these situations. Also add a function to read the current address of a BAR. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
4efe52bf |
|
12-Nov-2014 |
Thierry Reding <treding@nvidia.com> |
pci: Honour pci_skip_dev() When enumerating devices, honour the pci_skip_dev() function. This can be used by PCI controller drivers to restrict which devices will be probed. This is required by the NVIDIA Tegra PCIe controller driver, which will fail with a data abort exception if an access is attempted to a device number larger than 0 outside of bus 0. pci_skip_dev() is therefore implemented to prevent any such accesses. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Simon Glass <sjg@chromium.org> |
#
0991866c |
|
07-Aug-2014 |
Tim Harvey <tharvey@gateworks.com> |
pci: add support for board_pci_fixup_dev function Some board-level drivers may wish to have per-device fixup functions for PCI devices. Signed-off-by: Tim Harvey <tharvey@gateworks.com> |
#
fa5cec03 |
|
08-Nov-2013 |
Paul Burton <paul.burton@mips.com> |
pci.h: allow inclusion in assembly source This patch simply #ifdef's out the C-specific parts of pci.h when it is included by an assembly file. This will allow the macros it contains to be used from assembly source as will be done in a followup commit adding support for more modern MIPS Malta boards. Signed-off-by: Paul Burton <paul.burton@imgtec.com> |
#
287df01e |
|
11-Oct-2013 |
Zhao Qiang <B45475@freescale.com> |
PCIe:change the method to get the address of a requested capability in configuration space. Previously, the address of a requested capability is define like that "#define PCI_DCR 0x78" But, the addresses of capabilities is different with regard to PCIe revs. So this method is not flexible. Now a function to get the address of a requested capability is added and used. It can get the address dynamically by capability ID. The step of this function: 1. Read Status register in PCIe configuration space to confirm that Capabilities List is valid. 2. Find the address of Capabilities Pointer Register. 3. Find the address of requested capability from the first capability. Signed-off-by: Zhao Qiang <B45475@freescale.com> |
#
7b4e5844 |
|
03-Jul-2013 |
Zang Roy-R61911 <tie-fei.zang@freescale.com> |
powerpc/pcie: add PCIe version 3.x support T4240 PCIe IP is version 3.0 and has some update comparing previous QorIQ products. 1. Move Freescale specific register define to arch/powerpc/include/asm/fsl_pci.h and update the register offset define for T4240. 2. add the status/control register define use status/control register to judge the link status 3. The original code uses 'Programming Interface' field to judge if PCIE is EP or RC mode, however, T4240 does not support this functionality. According to PCIE specification, 'Header Type' offset 0x0e is used to indicate header type, so for PCIE controller, the patch changes code to use 'Header Type' field to identify if the PCIE is RC or EP mode. This patch fixes the PCIe card link up issue on T4240QDS. Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com> |
#
1a459660 |
|
08-Jul-2013 |
Wolfgang Denk <wd@denx.de> |
Add GPL-2.0+ SPDX-License-Identifier to source files Signed-off-by: Wolfgang Denk <wd@denx.de> [trini: Fixup common/cmd_io.c] Signed-off-by: Tom Rini <trini@ti.com> |
#
bc3442aa |
|
11-Jun-2013 |
Simon Glass <sjg@chromium.org> |
pci: Convert extern inline functions to static inline I am not sure of the meaning of extern inline, but this gives errors when building with function instrumenting enabled. Change these functions to static inline. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
842033e6 |
|
30-May-2013 |
Gabor Juhos <juhosg@openwrt.org> |
pci: introduce CONFIG_PCI_INDIRECT_BRIDGE option The pci_indirect.c file is always compiled when CONFIG_PCI is defined although the indirect PCI bridge support is not needed by every board. Introduce a new CONFIG_PCI_INDIRECT_BRIDGE config option and only compile indirect PCI bridge support if this options is enabled. Also add the new option into the configuration files of the boards which needs that. Compile tested for powerpc, x86, arm and nds32. MAKEALL results: powerpc: --------------------- SUMMARY ---------------------------- Boards compiled: 641 Boards with warnings but no errors: 2 ( ELPPC MPC8323ERDB ) ---------------------------------------------------------- Note: the warnings for ELPPC and MPC8323ERDB are present even without the actual patch. x86: --------------------- SUMMARY ---------------------------- Boards compiled: 1 ---------------------------------------------------------- arm: --------------------- SUMMARY ---------------------------- Boards compiled: 311 ---------------------------------------------------------- nds32: --------------------- SUMMARY ---------------------------- Boards compiled: 3 ---------------------------------------------------------- Cc: Tom Rini <trini@ti.com> Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com> Signed-off-by: Gabor Juhos <juhosg@openwrt.org> |
#
55ae10f8 |
|
20-Oct-2012 |
Bill Richardson <wfrichar@chromium.org> |
x86: gpio: Add GPIO driver for Intel ICH6 and later. Implement <asm-generic/gpio.h> functions for Intel ICH6 and later. Only GPIOs 0-31 are handled by this code. Signed-off-by: Bill Richardson <wfrichar@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org> |
#
a3a70725 |
|
24-Mar-2012 |
Linus Walleij <linus.walleij@linaro.org> |
pci: declare pciauto functions in header The FSL PCI driver uses local prototypes for pciauto_[pre|post]scan_setup_bridge(), this does not seem right, so move them to the <pci.h> file. Fixed a small extern declaration too, this is harmless but distracts the view since all other prototypes are explicitly external. Signed-off-by: Linus Walleij <linus.walleij@linaro.org> |
#
a1e47b66 |
|
03-Mar-2012 |
Linus Walleij <linus.walleij@linaro.org> |
pci: move pciauto_config_init() to pci.h Fixing build regressions for the Integrator I get find that a few boards try to work around the missing declaration of pciauto_config_init() by declaring it in the local scope. This does not make sense when the sibling functions are in <pci.h> so move the function to the header, ridding the build error in the Integrator and getting rid of the local declarations here and there. Reported-by: Wolfgang Denk <wd@denx.de> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> |
#
b03a466d |
|
01-Feb-2011 |
Prabhakar Kushwaha <prabhakar@freescale.com> |
powerpc/85xx: Handle PCIe initialization requires for P1021 class SoCs The P1011, P1012, P1015, P1016, P1020, P1021, P1024, & P1025 SoCs require that we initialize the SERDES registers if the lanes are configured for PCIe. Additionally these devices PCIe controller do not support ASPM and we have to explicitly disable it. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
10fa8d7c |
|
19-Jan-2011 |
Leo Liu <liucai.lfn@gmail.com> |
mpc83xx: fix pcie configuration space read/write This patch fix a problem for the pcie enumeration when the mpc83xx pcie controller is connected with switch or we use both of the two pcie controller. Signed-off-by: Leo Liu <liucai.lfn@gmail.com> fix codingstyle and compiler warning: 'pcie_priv' defined but not used Signed-off-by: Kim Phillips <kim.phillips@freescale.com> |
#
3a0e3c27 |
|
17-Dec-2010 |
Kumar Gala <galak@kernel.crashing.org> |
powerpc/fsl-pci: Determine pci_controller based on cfg addr for dts fixup Previously we passed in a specifically named struct pci_controller to determine if we had setup the particular PCI bus. Now we can search for the struct so we dont have to depend on the name or the struct being statically allocated. Introduced new find_hose_by_cfg_addr() to get back a pci_controller struct back by searching for it means we can do things like dynamically allocate them or not have to expose the static structures to all users. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Wolfgang Denk <wd@denx.de> |
#
983eb9d1 |
|
29-Oct-2010 |
Peter Tyser <ptyser@xes-inc.com> |
pci: Clean up PCI info when CONFIG_PCI_SCAN_SHOW This change does the following: - Removes the printing of the PCI interrupt line value. This is normally set to 0 by U-Boot on bootup and is rarely used during everyday operation. - Prints out the PCI function number of a device. Previously a device with multiple functions would be printed identically 2 times, which is generally confusing. For example, on an Intel 2 port gigabit Ethernet card the following was displayed: ... 04 01 8086 1010 0200 00 04 01 8086 1010 0200 00 ... - Prints a text description of each device's PCI class instead of the raw PCI class code. The textual description makes it much easier to determine what devices are installed on a PCI bus. - Changes the general formatting of the PCI device output. Previous output: PCIE1: connected as Root Complex 04 01 8086 1010 0200 00 04 01 8086 1010 0200 00 03 00 10b5 8112 0604 00 02 01 10b5 8518 0604 00 02 02 10b5 8518 0604 00 08 00 1957 0040 0b20 00 07 00 10b5 8518 0604 00 09 00 10b5 8112 0604 00 07 01 10b5 8518 0604 00 07 02 10b5 8518 0604 00 06 00 10b5 8518 0604 00 02 03 10b5 8518 0604 00 01 00 10b5 8518 0604 00 PCIE1: Bus 00 - 0b PCIE2: connected as Root Complex 0d 00 1957 0040 0b20 00 PCIE2: Bus 0c - 0d Updated output: PCIE1: connected as Root Complex 04:01.0 - 8086:1010 - Network controller 04:01.1 - 8086:1010 - Network controller 03:00.0 - 10b5:8112 - Bridge device 02:01.0 - 10b5:8518 - Bridge device 02:02.0 - 10b5:8518 - Bridge device 08:00.0 - 1957:0040 - Processor 07:00.0 - 10b5:8518 - Bridge device 09:00.0 - 10b5:8112 - Bridge device 07:01.0 - 10b5:8518 - Bridge device 07:02.0 - 10b5:8518 - Bridge device 06:00.0 - 10b5:8518 - Bridge device 02:03.0 - 10b5:8518 - Bridge device 01:00.0 - 10b5:8518 - Bridge device PCIE1: Bus 00 - 0b PCIE2: connected as Root Complex 0d:00.0 - 1957:0040 - Processor PCIE2: Bus 0c - 0d Signed-off-by: Peter Tyser <ptyser@xes-inc.com> |
#
8295b944 |
|
05-Aug-2009 |
Kumar Gala <galak@kernel.crashing.org> |
pci/fsl_pci_init: Use PCIe capability to determine if controller is PCIe Change the code to use the PCIe capabilities register to determine if we are a PCIe controller or not. Additionally cleaned up some white space and formatting in the file. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
cc2a8c77 |
|
19-Feb-2009 |
Anton Vorontsov <avorontsov@ru.mvista.com> |
PCI: Add pci_last_busno() helper This is just a handy routine that reports last PCI busno: we walk down all the hoses and return last hose's last_busno. Will be used by PCI/PCIe initialization code. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com> |
#
6e61fae4 |
|
03-Feb-2009 |
Becky Bruce <beckyb@kernel.crashing.org> |
drivers/pci: Create pci_map_bar function It is no longer always true that the pci bus address can be used as the virtual address for pci accesses. pci_map_bar() is created to return the virtual address for a pci region. Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org> |
#
ff4e66e9 |
|
06-Feb-2009 |
Kumar Gala <galak@kernel.crashing.org> |
pci: Rename PCI_REGION_MEMORY to PCI_REGION_SYS_MEMORY for clarity The PCI_REGION_MEMORY and PCI_REGION_MEM are a bit to similar and can be confusing when reading the code. Rename PCI_REGION_MEMORY to PCI_REGION_SYS_MEMORY to clarify its used for system memory mapping purposes. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
fd6646c0 |
|
07-Jan-2009 |
Anton Vorontsov <avorontsov@ru.mvista.com> |
mpc83xx: Add support for MPC83xx PCI-E controllers This patch adds support for MPC83xx PCI-E controllers in Root Complex mode. The patch is based on Tony Li and Dave Liu work[1]. Though unlike the original patch, by default we don't register PCI-E buses for use in U-Boot, we only configure the controllers for future use in other OSes (Linux). This is done because we don't have enough of spare BATs to map all the PCI-E regions. To actually use PCI-E in U-Boot, users should explicitly define CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES symbol in the board file. And only then U-Boot will able to access PCI-E, but at the cost of disabled address translation. [1] http://lists.denx.de/pipermail/u-boot/2008-January/027630.html Signed-off-by: Tony Li <tony.li@freescale.com> Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Acked-by: Dave Liu <daveliu@freescale.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com> |
#
30e76d5e |
|
21-Oct-2008 |
Kumar Gala <galak@kernel.crashing.org> |
pci: Allow for PCI addresses to be 64-bit PCI bus is inherently 64-bit. While not all system require access to the full 64-bit PCI address range some do. This allows those systems to enable the full PCI address width via CONFIG_SYS_PCI_64BIT. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Andrew Fleming-AFLEMING <afleming@freescale.com> Acked-by: Wolfgang Denk <wd@denx.de> |
#
36f32675 |
|
07-May-2008 |
Becky Bruce <bgill@freescale.com> |
Update pci code to use phys_addr_t Physical addrs need to be represented by phys_addr_t, not unsigned long. Otherwise, systems that use CONFIG_PHYS_64BIT are going to fail mightily. Signed-off-by: Becky Bruce <becky.bruce@freescale.com> |
#
63cec581 |
|
02-Aug-2007 |
Ed Swarthout <Ed.Swarthout@freescale.com> |
Make MPC8641's PCI/PCI-E driver a common driver for many FSL parts. All of the PCI/PCI-Express driver and initialization code that was in the MPC8641HPCN port has now been moved into the common drivers/fsl_pci_init.c. In a subsequent patch, this will be utilized by the 85xx ports as well. Common PCI-E IMMAP register blocks for FSL 85xx/86xx are added. Also enable the second PCI-Express controller on 8641 by getting its BATS and CFG_ setup right. Fixed a u16 vendor compiler warning in AHCI driver too. Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com> Signed-off-by: Zhang Wei <wei.zhang@freescale.com> Signed-off-by: Jon Loeliger <jdl@freescale.com> |
#
13a7fcdf |
|
19-Oct-2006 |
Jon Loeliger <jdl@freescale.com> |
* Fix a bunch of compiler warnings for gcc 4.0 Signed-off-by: Matthew McClintock <msm@freescale.com> |
#
f0e6f57f |
|
28-Jun-2006 |
Matthew McClintock <msm@freescale.com> |
* Added PCI-X #defines for PCI-X initialization Patch by Andy Fleming on 17-Mar-2006 Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
7b230f61 |
|
12-Mar-2006 |
Wolfgang Denk <wd@pollux.denx.de> |
Merge with git://git.kernel.org/pub/scm/boot/u-boot/u-boot.git#pci
|
#
993a2275 |
|
12-Mar-2006 |
Wolfgang Denk <wd@pollux.denx.de> |
Fix bad declaration on pci_cfgfunc_nothing Patch by Sam Song, 19 Jun 2005 |
#
a179012e |
|
11-Jan-2006 |
Kumar Gala <galak@kernel.crashing.org> |
Added support for PCI prefetchable region and BARs If a host controller sets up a region as prefetchable and a device's BAR denotes it as prefetchable, allocate the BAR into the prefetch region. If a BAR is prefetchable and no prefetchable region has been setup by the controller we fall back to allocating the BAR into the normally memory region. Patch by Kumar Gala 11 Jan 2006 |
#
c157d8e2 |
|
01-Aug-2005 |
Stefan Roese <sr@denx.de> |
Add support for AMCC PPC440EP/GR eval boards Yosemite and Yellowstone. Patch by Steven Blakeslee, 27 Jul 2005 |
#
7a8e9bed |
|
31-May-2003 |
Wolfgang Denk <wdenk> |
* Patch by Marc Singer, 29 May 2003: Fixed rarp boot method for IA32 and other little-endian CPUs. * Patch by Marc Singer, 28 May 2003: Added port I/O commands. * Patch by Matthew McClintock, 28 May 2003 - cpu/mpc824x/start.S: fix relocation code when booting from RAM - minor patches for utx8245 * Patch by Daniel Engstr�m, 28 May 2003: x86 update * Patch by Dave Ellis, 9 May 2003 + 27 May 2003: add nand flash support to SXNI855T configuration fix/extend nand flash support: - fix 'nand erase' command so does not erase bad blocks - fix 'nand write' command so does not write to bad blocks - fix nand_probe() so handles no flash detected properly - add doc/README.nand - add .jffs2 and .oob options to nand read/write - add 'nand bad' command to list bad blocks - add 'clean' option to 'nand erase' to write JFFS2 clean markers - make NAND read/write faster * Patch by Rune Torgersen, 23 May 2003: Update for MPC8266ADS board |
#
c7de829c |
|
19-Nov-2002 |
Wolfgang Denk <wdenk> |
* Patch by Thomas Frieden, 13 Nov 2002: Add code for AmigaOne board (preliminary merge to U-Boot, still WIP) * Patch by Jon Diekema, 12 Nov 2002: - Adding URL for IEEE OUI lookup - Making the autoboot #defines dependent on CONFIG_AUTOBOOT_KEYED being defined. - In the CONFIG_EXTRA_ENV_SETTINGS #define, the root-on-initrd and root-on-nfs macros are designed to switch how the default boot method gets defined. |
#
c609719b |
|
02-Nov-2002 |
Wolfgang Denk <wdenk> |
Initial revision |
#
a398a51c |
|
20-Nov-2021 |
Maciej W. Rozycki <macro@orcam.me.uk> |
pci: Work around PCIe link training failures Attempt to handle cases with a downstream port of a PCIe switch where link training never completes and the link continues switching between speeds indefinitely with the data link layer never reaching the active state. It has been observed with a downstream port of the ASMedia ASM2824 Gen 3 switch wired to the upstream port of the Pericom PI7C9X2G304 Gen 2 switch, using a Delock Riser Card PCI Express x1 > 2 x PCIe x1 device, P/N 41433, wired to a SiFive HiFive Unmatched board. In this setup the switches are supposed to negotiate the link speed of preferably 5.0GT/s, falling back to 2.5GT/s. However the link continues oscillating between the two speeds, at the rate of 34-35 times per second, with link training reported repeatedly active ~84% of the time, e.g.: 02:03.0 PCI bridge [0604]: ASMedia Technology Inc. ASM2824 PCIe Gen3 Packet Switch [1b21:2824] (rev 01) (prog-if 00 [Normal decode]) [...] Bus: primary=02, secondary=05, subordinate=05, sec-latency=0 [...] Capabilities: [80] Express (v2) Downstream Port (Slot+), MSI 00 [...] LnkSta: Speed 5GT/s (downgraded), Width x1 (ok) TrErr- Train+ SlotClk+ DLActive- BWMgmt+ ABWMgmt- [...] LnkCtl2: Target Link Speed: 8GT/s, EnterCompliance- SpeedDis+, Selectable De-emphasis: -3.5dB Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS- Compliance De-emphasis: -6dB [...] Forcibly limiting the target link speed to 2.5GT/s with the upstream ASM2824 device makes the two switches communicate correctly however: 02:03.0 PCI bridge [0604]: ASMedia Technology Inc. ASM2824 PCIe Gen3 Packet Switch [1b21:2824] (rev 01) (prog-if 00 [Normal decode]) [...] Bus: primary=02, secondary=05, subordinate=09, sec-latency=0 [...] Capabilities: [80] Express (v2) Downstream Port (Slot+), MSI 00 [...] LnkSta: Speed 2.5GT/s (downgraded), Width x1 (ok) TrErr- Train- SlotClk+ DLActive+ BWMgmt- ABWMgmt- [...] LnkCtl2: Target Link Speed: 2.5GT/s, EnterCompliance- SpeedDis+, Selectable De-emphasis: -3.5dB Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS- Compliance De-emphasis: -6dB [...] and then: 05:00.0 PCI bridge [0604]: Pericom Semiconductor PI7C9X2G304 EL/SL PCIe2 3-Port/4-Lane Packet Switch [12d8:2304] (rev 05) (prog-if 00 [Normal decode]) [...] Bus: primary=05, secondary=06, subordinate=09, sec-latency=0 [...] Capabilities: [c0] Express (v2) Upstream Port, MSI 00 [...] LnkSta: Speed 2.5GT/s (downgraded), Width x1 (downgraded) TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt- [...] LnkCtl2: Target Link Speed: 5GT/s, EnterCompliance- SpeedDis- Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS- Compliance De-emphasis: -6dB [...] Make use of this observation then and attempt to detect the inability to negotiate the link speed automatically, and then handle it by hand. Use the Data Link Layer Link Active status flag as the primary indicator of successful link speed negotiation, but given that the flag is optional by hardware to implement (the ASM2824 does have it though), resort to checking for the mandatory Link Bandwidth Management Status flag showing that the link speed or width has been changed in an attempt to correct unreliable link operation (the ASM2824 does set it too). If these checks indicate that link may not operate correctly, then poll the Data Link Layer Link Active status flag along with the Link Training flag for the duration of 200ms to see if the link has stabilised, that is either that the Data Link Layer Link Active status flag has been set or that Link Training has been inactive during at least the second half of the interval. If that has indicated failure, restrict the target speed to 2.5GT/s, request a link retrain and check again if the link has stabilised. If that does not work either, then restore the original speed setting and claim defeat, otherwise we are done. NB interestingly enough with the ASM2824 vs PI7C9X2G304 configuration referred above asking the ASM2824 to retrain with a higher target link speed once the 2.5GT/s speed has been negotiated makes the two devices successfully negotiate 5.0GT/s. Lifting the 2.5GT/s speed restriction would however prevent our workaround from working with an OS that issues a reset and that is unaware of the problem. This is because the devices would then try to negotiate a higher link speed from scratch and fail, while the sticky property of the Target Link Speed setting will keep the 2.5GT/s speed restriction across a reset. Keep the 2.5GT/s speed restriction then, conservatively, if functional once applied. Signed-off-by: Maciej W. Rozycki <macro@orcam.me.uk> Reviewed-by: Stefan Roese <sr@denx.de> |
#
2a8d4025 |
|
26-Nov-2021 |
Pali Rohár <pali@kernel.org> |
pci: Add standard PCI Config Address macros Lot of PCI and PCIe controllers are using standard Config Address for PCI Configuration Mechanism #1 or its extended version. So add PCI_CONF1_ADDRESS() and PCI_CONF1_EXT_ADDRESS() macros into U-Boot's pci.h header file which can be suitable for most PCI and PCIe controller drivers. Drivers do not have to invent their own macros and can use these new U-Boot macros. Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
a4bc38da |
|
02-Nov-2021 |
Pali Rohár <pali@kernel.org> |
pci: Add standard PCIe ECAM macros Lot of PCIe controllers are using ECAM addressing. So add common ECAM macros into U-Boot's pci.h header file which can be suitable for most PCI controller drivers. Replace custom ECAM address macros in every PCI controller driver by new ECAM macros from U-Boot's pci.h header file. Similar macros are defined also in Linux kernel. There is a small difference between Linux and these new U-Boot macros. U-Boot's PCIE_ECAM_OFFSET() takes device and function numbers in separate arguments. Linux's PCIE_ECAM_OFFSET() takes device and function numbers encoded in one argument. The reason is that U-Boot's PCI_DEVFN() macro is different than Linux's PCI_SLOT() macro. So having device and function numbers in separate arguments makes code more straightforward. Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Stefan Roese <sr@denx.de> |
#
1d7ad685 |
|
25-Sep-2021 |
Pali Rohár <pali@kernel.org> |
arm: a37xx: pci: Handle propagation of CRSSVE bit from PCIe Root Port Now that PCI Bridge (PCIe Root Port) for Aardvark is emulated in U-Boot, add support for handling and propagation of CRSSVE bit. When CRSSVE bit is unset (default), driver has to reissue config read/write request on CRS response. CRSSVE bit is supported only when CRSVIS bit is provided in read-only Root Capabilities register. So manually inject this CRSVIS bit into read response for that register. Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Stefan Roese <sr@denx.de> |
#
2649f69f |
|
17-Sep-2021 |
Vladimir Oltean <vladimir.oltean@nxp.com> |
pci: provide prototype for pci_skip_dev outside of #if defined(CONFIG_DM_PCI_COMPAT) The weak definition of pci_skip_dev from drivers/pci/pci_common.c is not under CONFIG_DM_PCI_COMPAT, and that definition needs a previous function prototype declaration to avoid W=1 build warnings. That prototype is not available due to it being under CONFIG_DM_PCI_COMPAT, so move it outside of that preprocessor block. Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
23cacd57 |
|
01-Aug-2021 |
Simon Glass <sjg@chromium.org> |
pci: Drop PCI_INDIRECT_BRIDGE This does not work with driver model so can be removed. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
26543cc6 |
|
01-Aug-2021 |
Simon Glass <sjg@chromium.org> |
pci: Drop old code from header file We don't need this code anymore since when PCI is enabled, driver model is always used. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
63814a69 |
|
01-Aug-2021 |
Simon Glass <sjg@chromium.org> |
pci: imx: Drop DM_PCI check from cpu driver We don't need this check anymore since when PCI is enabled, driver model is always used. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
e8c09d69 |
|
01-Aug-2021 |
Simon Glass <sjg@chromium.org> |
pci: Remove guard around compatibility functions This prevents use of IS_ENABLED() in other files. Functions should be visible in headers even if they are not available at link time. Fix it. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
f5cbb5c7 |
|
27-Jun-2021 |
Simon Glass <sjg@chromium.org> |
x86: pci: Allow binding of some devices before relocation At present only bridge devices are bound before relocation, to save space in pre-relocation memory. In some cases we do actually want to bind a device, e.g. because it provides the console UART. Add a devicetree binding to support this. Use the PCI_VENDEV() macro to encode the cell value. This is present in U-Boot but not used, so move it to the binding header-file. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
e58f3a7d |
|
27-Jun-2021 |
Simon Glass <sjg@chromium.org> |
pci: Use const for pci_find_device_id() etc. These functions don't modify the device-ID struct that is passed in, so mark the argument as const, so the data structure can be declared that way. This allows it to be placed in the rodata section. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
c7b36007 |
|
14-May-2021 |
Tom Rini <trini@konsulko.com> |
pci: Remove non-DM board_pci_fixup_dev() declaration With the ventana boards migrated to DM_PCI and DM_ETH, we can remove this prototype. Cc: Stefano Babic <sbabic@denx.de> Signed-off-by: Tom Rini <trini@konsulko.com> |
#
cecd013f |
|
16-Apr-2021 |
Tim Harvey <tharvey@gateworks.com> |
pci: pci-uclass: Add board_pci_fixup_dev for DM_PCI Add a board_pci_fixup_dev weak function to allow PCI device fixups during enumeration. Signed-off-by: Tim Harvey <tharvey@gateworks.com> |
#
8b85dfc6 |
|
16-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: Avoid accessing seq directly At present various drivers etc. access the device's 'seq' member directly. This makes it harder to change the meaning of that member. Change access to go through a function instead. The drivers/i2c/lpc32xx_i2c.c file is left unchanged for now. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
caa4daa2 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename 'platdata' variables to just 'plat' We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
284d062e |
|
09-Sep-2020 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
pci: add a few ARI related defines Add a few defines related to PCI ARI configuration. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
51eeae91 |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add VF BAR map support for Enhanced Allocation Makes dm_pci_map_bar API available to map BAR for Virtual function PCI devices which support Enhanced Allocation. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> |
#
b8852dcf |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add support for Single-Root I/O Virtualization SR-IOV - Single Root I/O Virtualization PF - Physical Function VF - Virtual Function If SR-IOV capability is present, use it to initialize Virtual Function PCI device instances. pci_sriov_init function will read SR-IOV registers to create VF devices under the PF PCI device and also bind driver if available. This function needs to be invoked from Physical function device driver which expects VF device support, creating minimal impact on existing framework. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> |
#
e0024741 |
|
23-Jul-2020 |
Stefan Roese <sr@denx.de> |
pci: pci-uclass: Dynamically allocate the PCI regions Instead of using a fixed length pre-allocated array of regions, this patch moves to dynamically allocating the regions based on the number of available regions plus the necessary regions for DRAM banks. Since MAX_PCI_REGIONS is not needed any more, its removed completely with this patch. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Thierry Reding <treding@nvidia.com> Cc: Marek Vasut <marek.vasut+renesas@gmail.com> |
#
143eb5b1 |
|
12-May-2020 |
Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
drivers: pci: add api to get dma regions Add api to get dma regions. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com> |
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com> |
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com> |
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
7d994067 |
|
23-Apr-2019 |
Tom Rini <trini@konsulko.com> |
Merge tag 'pull-24apr19' of git://git.denx.de/u-boot-dm Various minor sandbox iumprovements Fixes for tracing with sandbox Refactoring for boot_get_fdt()
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
a8c5f8d3 |
|
15-Oct-2018 |
Bin Meng <bmeng.cn@gmail.com> |
dm: pci: Add APIs to find next capability and extended capability This introduces two new APIs dm_pci_find_next_capability() and dm_pci_find_next_ext_capability() to get PCI capability address and PCI express extended capability address for a given PCI device starting from a given offset. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
dac01fd8 |
|
03-Aug-2018 |
Bin Meng <bmeng.cn@gmail.com> |
dm: pci: Add APIs to find capability and extended capability This introduces two new APIs dm_pci_find_capability() and dm_pci_find_ext_capability() to get PCI capability address and PCI express extended capability address for a given PCI device. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
5d544f96 |
|
03-Aug-2018 |
Bin Meng <bmeng.cn@gmail.com> |
pci: Add all known capability and extended capability ids Currently we don't have a complete list of capability and extended capability ids. This adds them. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
4345998a |
|
03-Aug-2018 |
Bin Meng <bmeng.cn@gmail.com> |
pci: sandbox: Support dynamically binding device driver At present all emulated sandbox pci devices must be present in the device tree in order to be used. The real world pci uclass driver supports pci device driver matching, and we should add such support on sandbox too. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
01259c93 |
|
03-Aug-2018 |
Bin Meng <bmeng.cn@gmail.com> |
pci: Remove 440ep-specific macros These macros should not be put in the generic pci.h header file. Since they are not referenced anywhere, remove them completely. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
5ce9aca8 |
|
14-May-2018 |
Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi> |
PCI: Document pciauto_region_allocate() Add a doc comment for pciauto_region_allocate(). Signed-off-by: Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
d71975ae |
|
14-May-2018 |
Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi> |
PCI: autoconfig: Don't allocate 64-bit addresses to 32-bit only resources Currently, if we happen to allocate an address requiring 64 bits to a device only supporting 32-bit BARs, the address eventually gets silently truncated to 32 bits. Avoid this by adding a new flag to pciauto_region_allocate() to bail out in such situations. Signed-off-by: Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
83d290c5 |
|
06-May-2018 |
Tom Rini <trini@konsulko.com> |
SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com> |
#
ed68ccbf |
|
13-Mar-2018 |
Stefan Roese <sr@denx.de> |
pci: Remove unused ppc4xx variable from struct pci_controller ppc4xx support was removed some time ago. Lets remove the now unused "pci_fb" variable from "struct pci_controller" as well. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Simon Glass <sjg@chromium.org> |
#
badb9922 |
|
19-Sep-2017 |
Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi> |
pci: Add helper for implementing memory-mapped config space accesses This sort of pattern for implementing memory-mapped PCI config space accesses appears in U-Boot twice already, and a third user is coming up. So add helper functions to avoid code duplication, similar to how Linux has pci_generic_config_write and pci_generic_config_read. Signed-off-by: Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
6ecbe137 |
|
12-May-2017 |
Tim Harvey <tharvey@gateworks.com> |
drivers: pci: imx: add imx_pcie_remove function There is no dedicated reset signal wired up for the MX6QDL thus if the bootloader enables the link we need some special handling to get the core back into a state where it is safe to touch it for configuration. While there has been some special handling in the Linux kernel to do this, it was removed in 4.11 thus we need to do it properly in the bootloader and therefore without this if you enable PCI in the bootloader you will hang while booting the 4.11 kernel. This puts the PCIe controller back into a safe state for the kernel driver before launching the kernel. Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com> Tested-by: Peter Senna Tschudin <peter.senna@collabora.com> |
#
eeb5b1ad |
|
10-Mar-2016 |
Stuart Yoder <stuart.yoder@nxp.com> |
pci: make pci_get_hose_head() available to external users Put pci_get_hose_head() prototype in header so it is available to external users, allowing them to find and iterate over all pci controllers. Signed-off-by: Stuart Yoder <stuart.yoder@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
4974a6ff |
|
06-Mar-2016 |
Simon Glass <sjg@chromium.org> |
pci: Correct a few comments and nits Two comments are missing a parameter and there is an extra blank line. Also two of the region access macros are misnamed. Correct these problems. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
319dba1f |
|
06-Mar-2016 |
Simon Glass <sjg@chromium.org> |
pci: Add functions to update PCI configuration registers It is common to read a config register value, clear and set some bits, then write back the updated value. Add functions to do this in one step, for convenience. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
308143ef |
|
02-Feb-2016 |
Bin Meng <bmeng.cn@gmail.com> |
dm: pci: Add missing forward declarations When CONFIG_DM_PCI_COMPAT is not on, there is only a forward declaration for pci_write_config32(). Add other missing ones. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
9d731c82 |
|
18-Jan-2016 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to write a BAR Add a driver-model version of the pci_write_bar32 function so that this is supported in the new API. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
7e78b9ef |
|
29-Nov-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Switch to DM API for PCI address mapping We should use the new address mapping functions unless we are in compatibility mode. Disable the old functions by default. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
21d1fe7e |
|
29-Nov-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add driver model API functions for address mapping At present the PCI address map functions use the old API. Add new functions for this so that drivers can be converted. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
bab17cf1 |
|
29-Nov-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR Add a driver-model function for reading the PCI BAR from a device. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
a0eb8356 |
|
29-Nov-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a driver-model version of pci_find_class() Add a function which scans the driver model device information rather than scanning the PCI bus again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> |
#
5c0bf647 |
|
29-Nov-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a driver-model version of pci_find_device() Add a function which scans the driver model device information rather than scanning the PCI bus again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> |
#
5e23b8b4 |
|
29-Nov-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Use driver model PCI API in auto-config At present we are using legacy functions even in the auto-configuration code used by driver model. Add a new pci_auto.c version which uses the correct API. Create a new pci_internal.h header to hold functions that are used within the PCI subsystem, but are not exported to other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> |
#
f3f1faef |
|
29-Nov-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a dm_ prefix to pci_bus_find_bdf() Most driver model PCI functions have a dm_ prefix. At some point, when the old code is converted to driver model and the old functions are removed, we will drop that prefix. For consistency, we should use the dm_ prefix for all driver model functions. Update pci_bus_find_bdf() accordingly. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
21ccce1b |
|
29-Nov-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a dm_ prefix to pci_get_bdf() Most driver model PCI functions have a dm_ prefix. At some point, when the old code is converted to driver model and the old functions are removed, we will drop that prefix. For consistency, we should use the dm_ prefix for all driver model functions. Update pci_get_bdf() accordingly. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
3ba5f74a |
|
26-Nov-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Disable PCI compatibility functions by default We eventually need to drop the compatibility functions for driver model. As a first step, create a configuration option to enable them and hide them when the option is disabled. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
54fe7b1c |
|
26-Nov-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a comment about how to find struct pci_controller With driver mode, struct pci_controller is stored as uclass-private data. Add a comment to that effect. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
f9260336 |
|
19-Nov-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to find the regions for a PCI bus This function looks up the controller and returns a pointer to each region type. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Stephen Warren <swarren@nvidia.com> Tested-by: Stephen Warren <swarren@nvidia.com> |
#
9f60fb0d |
|
19-Nov-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to get the controller for a bus A PCI bus may be a bridge device where the controller is the bridge's parent. Add a function to return the controller device, given a PCI device. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Stephen Warren <swarren@nvidia.com> Tested-by: Stephen Warren <swarren@nvidia.com> |
#
9289db6c |
|
19-Nov-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add functions to emulate 8- and 16-bit access Provide a few functions to support using 32-bit access to emulate 8- and 16-bit access. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Stephen Warren <swarren@nvidia.com> Tested-by: Stephen Warren <swarren@nvidia.com> |
#
bcbe3d15 |
|
28-Sep-2015 |
Simon Glass <sjg@chromium.org> |
dm: Rename dev_get_parentdata() to dev_get_parent_priv() The current name is inconsistent with other driver model data access functions. Rename it and fix up all users. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Joe Hershberger <joe.hershberger@ni.com> |
#
dc5740df |
|
22-Aug-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a comment to help find pci_hose_read_config_byte, etc. These functions are defined by macros so do not show up with grep. Add a comment to help. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
76c3fbcd |
|
10-Aug-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a way to iterate through all PCI devices These functions allow iteration through all PCI devices including bridges. The children of each PCI bus are returned in turn. This can be useful for configuring, checking or enumerating all the devices. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
66afb4ed |
|
10-Aug-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Provide friendly config access functions At present there are no PCI functions which allow access to PCI configuration using a struct udevice. This is a sad situation for driver model as it makes use of PCI harder. Add these functions. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
5f48d798 |
|
27-Jul-2015 |
Simon Glass <sjg@chromium.org> |
pci: Add a constant for an invalid interrupt Rather than using 0xff in the code, add a constant. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
ed5b580b |
|
09-Jul-2015 |
Minghuan Lian <Minghuan.Lian@freescale.com> |
drivers/pci: Add function to find an extended capability PCIe extends device's configuration space to 4k and provides extended capability. The patch adds function to find them. The code is ported from Linux PCIe driver. Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
4b515e4f |
|
06-Jul-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to get the BDF for a device It is useful to be able to find the full PCI address (bus, device and function) for a PCI device. Add a function to provide this. Adjust the existing code to use this. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
aba92962 |
|
06-Jul-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add support for PCI driver matching At present all PCI devices must be present in the device tree in order to be used. Many or most PCI devices don't require any configuration other than that which is done automatically by U-Boot. It is inefficent to add a node with nothing but a compatible string in order to get a device working. Add a mechanism whereby PCI drivers can be declared along with the device parameters they support (vendor/device/class). When no suitable driver is found in the device tree the list of such devices is consulted to determine the correct driver. If this also fails, then a generic driver is used as before. The mechanism used is very similar to that provided by Linux and the header file defintions are copied from Linux 4.1. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Joe Hershberger <joe.hershberger@ni.com> |
#
6c89663c |
|
07-Jul-2015 |
Bin Meng <bmeng.cn@gmail.com> |
pci: Configure expansion ROM during auto config process Currently PCI expansion ROM address is assigned by a call to pciauto_setup_rom() outside of the pci auto config process. This does not work when expansion ROM is on a device behind PCI bridge where bridge's memory limit register was already programmed to a value that does not cover the newly assigned expansion ROM address. To fix this, we should configure the ROM address during the auto config process. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Acked-by: Simon Glass <sjg@chromium.org> |
#
aec241df |
|
07-Jun-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Use the correct hose when configuring devices Only the PCI controller has access to the PCI region information. Make sure to use the controller (rather than any attached bridges) when configuring devices. This corrects a failure to scan and configure devices when driver model is enabled for PCI. Also add a comment to explain the problem. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
36d0d3b4 |
|
05-Mar-2015 |
Simon Glass <sjg@chromium.org> |
dm: sandbox: pci: Add a PCI emulation uclass Since sandbox does not have real devices (unless it borrows those from the host) it must use emulations. Provide a uclass which permits PCI operations to be passed through to an emulation device. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
ff3e077b |
|
05-Mar-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a uclass for PCI Add a uclass for PCI controllers and a generic one for PCI devices. Adjust the 'pci' command and the existing PCI support to work with this new uclass. Keep most of the compatibility code in a separate file so that it can be removed one day. TODO: Add more header file comments to the new parts of pci.h Signed-off-by: Simon Glass <sjg@chromium.org> |
#
aab6724c |
|
05-Mar-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move common PCI functions into their own file Driver model will share many functions with the existing PCI implementation. Move these into their own file to avoid duplication and confusion. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
250e039d |
|
27-Jan-2015 |
Simon Glass <sjg@chromium.org> |
pci: Add a function to find a device by class There is an existing function prototype in the header file but it is not implemented. Implement something similar. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
4a2708a0 |
|
14-Jan-2015 |
Simon Glass <sjg@chromium.org> |
x86: Access the VGA ROM when needed Add code to the generic pci_rom file to access the VGA ROM in PCI space when needed. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
d622ac39 |
|
15-Dec-2014 |
Masahiro Yamada <yamada.m@jp.panasonic.com> |
powerpc: mpc824x: remove MPC824X cpu support All the MPC824X boards are still non-generic boards: A3000, CPC45, CU824, eXalion, MVBLUE, MUSENKI, Sandpoint824x, utx8245 Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Josef Wagner <Wagner@Microsys.de> Cc: Torsten Demke <torsten.demke@fci.com> Cc: Jim Thompson <jim@musenki.com> Cc: Greg Allen <gallen@arlut.utexas.edu> |
#
e8a552eb |
|
14-Nov-2014 |
Simon Glass <sjg@chromium.org> |
pci: Add functions to read and write a BAR address Some PCI functions cannot be auto-configured. Add a function to set up a fixed BAR which can be used in these situations. Also add a function to read the current address of a BAR. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
4efe52bf |
|
12-Nov-2014 |
Thierry Reding <treding@nvidia.com> |
pci: Honour pci_skip_dev() When enumerating devices, honour the pci_skip_dev() function. This can be used by PCI controller drivers to restrict which devices will be probed. This is required by the NVIDIA Tegra PCIe controller driver, which will fail with a data abort exception if an access is attempted to a device number larger than 0 outside of bus 0. pci_skip_dev() is therefore implemented to prevent any such accesses. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Simon Glass <sjg@chromium.org> |
#
0991866c |
|
07-Aug-2014 |
Tim Harvey <tharvey@gateworks.com> |
pci: add support for board_pci_fixup_dev function Some board-level drivers may wish to have per-device fixup functions for PCI devices. Signed-off-by: Tim Harvey <tharvey@gateworks.com> |
#
fa5cec03 |
|
08-Nov-2013 |
Paul Burton <paul.burton@mips.com> |
pci.h: allow inclusion in assembly source This patch simply #ifdef's out the C-specific parts of pci.h when it is included by an assembly file. This will allow the macros it contains to be used from assembly source as will be done in a followup commit adding support for more modern MIPS Malta boards. Signed-off-by: Paul Burton <paul.burton@imgtec.com> |
#
287df01e |
|
11-Oct-2013 |
Zhao Qiang <B45475@freescale.com> |
PCIe:change the method to get the address of a requested capability in configuration space. Previously, the address of a requested capability is define like that "#define PCI_DCR 0x78" But, the addresses of capabilities is different with regard to PCIe revs. So this method is not flexible. Now a function to get the address of a requested capability is added and used. It can get the address dynamically by capability ID. The step of this function: 1. Read Status register in PCIe configuration space to confirm that Capabilities List is valid. 2. Find the address of Capabilities Pointer Register. 3. Find the address of requested capability from the first capability. Signed-off-by: Zhao Qiang <B45475@freescale.com> |
#
7b4e5844 |
|
03-Jul-2013 |
Zang Roy-R61911 <tie-fei.zang@freescale.com> |
powerpc/pcie: add PCIe version 3.x support T4240 PCIe IP is version 3.0 and has some update comparing previous QorIQ products. 1. Move Freescale specific register define to arch/powerpc/include/asm/fsl_pci.h and update the register offset define for T4240. 2. add the status/control register define use status/control register to judge the link status 3. The original code uses 'Programming Interface' field to judge if PCIE is EP or RC mode, however, T4240 does not support this functionality. According to PCIE specification, 'Header Type' offset 0x0e is used to indicate header type, so for PCIE controller, the patch changes code to use 'Header Type' field to identify if the PCIE is RC or EP mode. This patch fixes the PCIe card link up issue on T4240QDS. Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com> |
#
1a459660 |
|
08-Jul-2013 |
Wolfgang Denk <wd@denx.de> |
Add GPL-2.0+ SPDX-License-Identifier to source files Signed-off-by: Wolfgang Denk <wd@denx.de> [trini: Fixup common/cmd_io.c] Signed-off-by: Tom Rini <trini@ti.com> |
#
bc3442aa |
|
11-Jun-2013 |
Simon Glass <sjg@chromium.org> |
pci: Convert extern inline functions to static inline I am not sure of the meaning of extern inline, but this gives errors when building with function instrumenting enabled. Change these functions to static inline. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
842033e6 |
|
30-May-2013 |
Gabor Juhos <juhosg@openwrt.org> |
pci: introduce CONFIG_PCI_INDIRECT_BRIDGE option The pci_indirect.c file is always compiled when CONFIG_PCI is defined although the indirect PCI bridge support is not needed by every board. Introduce a new CONFIG_PCI_INDIRECT_BRIDGE config option and only compile indirect PCI bridge support if this options is enabled. Also add the new option into the configuration files of the boards which needs that. Compile tested for powerpc, x86, arm and nds32. MAKEALL results: powerpc: --------------------- SUMMARY ---------------------------- Boards compiled: 641 Boards with warnings but no errors: 2 ( ELPPC MPC8323ERDB ) ---------------------------------------------------------- Note: the warnings for ELPPC and MPC8323ERDB are present even without the actual patch. x86: --------------------- SUMMARY ---------------------------- Boards compiled: 1 ---------------------------------------------------------- arm: --------------------- SUMMARY ---------------------------- Boards compiled: 311 ---------------------------------------------------------- nds32: --------------------- SUMMARY ---------------------------- Boards compiled: 3 ---------------------------------------------------------- Cc: Tom Rini <trini@ti.com> Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com> Signed-off-by: Gabor Juhos <juhosg@openwrt.org> |
#
55ae10f8 |
|
20-Oct-2012 |
Bill Richardson <wfrichar@chromium.org> |
x86: gpio: Add GPIO driver for Intel ICH6 and later. Implement <asm-generic/gpio.h> functions for Intel ICH6 and later. Only GPIOs 0-31 are handled by this code. Signed-off-by: Bill Richardson <wfrichar@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org> |
#
a3a70725 |
|
24-Mar-2012 |
Linus Walleij <linus.walleij@linaro.org> |
pci: declare pciauto functions in header The FSL PCI driver uses local prototypes for pciauto_[pre|post]scan_setup_bridge(), this does not seem right, so move them to the <pci.h> file. Fixed a small extern declaration too, this is harmless but distracts the view since all other prototypes are explicitly external. Signed-off-by: Linus Walleij <linus.walleij@linaro.org> |
#
a1e47b66 |
|
03-Mar-2012 |
Linus Walleij <linus.walleij@linaro.org> |
pci: move pciauto_config_init() to pci.h Fixing build regressions for the Integrator I get find that a few boards try to work around the missing declaration of pciauto_config_init() by declaring it in the local scope. This does not make sense when the sibling functions are in <pci.h> so move the function to the header, ridding the build error in the Integrator and getting rid of the local declarations here and there. Reported-by: Wolfgang Denk <wd@denx.de> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> |
#
b03a466d |
|
01-Feb-2011 |
Prabhakar Kushwaha <prabhakar@freescale.com> |
powerpc/85xx: Handle PCIe initialization requires for P1021 class SoCs The P1011, P1012, P1015, P1016, P1020, P1021, P1024, & P1025 SoCs require that we initialize the SERDES registers if the lanes are configured for PCIe. Additionally these devices PCIe controller do not support ASPM and we have to explicitly disable it. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
10fa8d7c |
|
19-Jan-2011 |
Leo Liu <liucai.lfn@gmail.com> |
mpc83xx: fix pcie configuration space read/write This patch fix a problem for the pcie enumeration when the mpc83xx pcie controller is connected with switch or we use both of the two pcie controller. Signed-off-by: Leo Liu <liucai.lfn@gmail.com> fix codingstyle and compiler warning: 'pcie_priv' defined but not used Signed-off-by: Kim Phillips <kim.phillips@freescale.com> |
#
3a0e3c27 |
|
17-Dec-2010 |
Kumar Gala <galak@kernel.crashing.org> |
powerpc/fsl-pci: Determine pci_controller based on cfg addr for dts fixup Previously we passed in a specifically named struct pci_controller to determine if we had setup the particular PCI bus. Now we can search for the struct so we dont have to depend on the name or the struct being statically allocated. Introduced new find_hose_by_cfg_addr() to get back a pci_controller struct back by searching for it means we can do things like dynamically allocate them or not have to expose the static structures to all users. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Wolfgang Denk <wd@denx.de> |
#
983eb9d1 |
|
29-Oct-2010 |
Peter Tyser <ptyser@xes-inc.com> |
pci: Clean up PCI info when CONFIG_PCI_SCAN_SHOW This change does the following: - Removes the printing of the PCI interrupt line value. This is normally set to 0 by U-Boot on bootup and is rarely used during everyday operation. - Prints out the PCI function number of a device. Previously a device with multiple functions would be printed identically 2 times, which is generally confusing. For example, on an Intel 2 port gigabit Ethernet card the following was displayed: ... 04 01 8086 1010 0200 00 04 01 8086 1010 0200 00 ... - Prints a text description of each device's PCI class instead of the raw PCI class code. The textual description makes it much easier to determine what devices are installed on a PCI bus. - Changes the general formatting of the PCI device output. Previous output: PCIE1: connected as Root Complex 04 01 8086 1010 0200 00 04 01 8086 1010 0200 00 03 00 10b5 8112 0604 00 02 01 10b5 8518 0604 00 02 02 10b5 8518 0604 00 08 00 1957 0040 0b20 00 07 00 10b5 8518 0604 00 09 00 10b5 8112 0604 00 07 01 10b5 8518 0604 00 07 02 10b5 8518 0604 00 06 00 10b5 8518 0604 00 02 03 10b5 8518 0604 00 01 00 10b5 8518 0604 00 PCIE1: Bus 00 - 0b PCIE2: connected as Root Complex 0d 00 1957 0040 0b20 00 PCIE2: Bus 0c - 0d Updated output: PCIE1: connected as Root Complex 04:01.0 - 8086:1010 - Network controller 04:01.1 - 8086:1010 - Network controller 03:00.0 - 10b5:8112 - Bridge device 02:01.0 - 10b5:8518 - Bridge device 02:02.0 - 10b5:8518 - Bridge device 08:00.0 - 1957:0040 - Processor 07:00.0 - 10b5:8518 - Bridge device 09:00.0 - 10b5:8112 - Bridge device 07:01.0 - 10b5:8518 - Bridge device 07:02.0 - 10b5:8518 - Bridge device 06:00.0 - 10b5:8518 - Bridge device 02:03.0 - 10b5:8518 - Bridge device 01:00.0 - 10b5:8518 - Bridge device PCIE1: Bus 00 - 0b PCIE2: connected as Root Complex 0d:00.0 - 1957:0040 - Processor PCIE2: Bus 0c - 0d Signed-off-by: Peter Tyser <ptyser@xes-inc.com> |
#
8295b944 |
|
05-Aug-2009 |
Kumar Gala <galak@kernel.crashing.org> |
pci/fsl_pci_init: Use PCIe capability to determine if controller is PCIe Change the code to use the PCIe capabilities register to determine if we are a PCIe controller or not. Additionally cleaned up some white space and formatting in the file. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
cc2a8c77 |
|
19-Feb-2009 |
Anton Vorontsov <avorontsov@ru.mvista.com> |
PCI: Add pci_last_busno() helper This is just a handy routine that reports last PCI busno: we walk down all the hoses and return last hose's last_busno. Will be used by PCI/PCIe initialization code. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com> |
#
6e61fae4 |
|
03-Feb-2009 |
Becky Bruce <beckyb@kernel.crashing.org> |
drivers/pci: Create pci_map_bar function It is no longer always true that the pci bus address can be used as the virtual address for pci accesses. pci_map_bar() is created to return the virtual address for a pci region. Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org> |
#
ff4e66e9 |
|
06-Feb-2009 |
Kumar Gala <galak@kernel.crashing.org> |
pci: Rename PCI_REGION_MEMORY to PCI_REGION_SYS_MEMORY for clarity The PCI_REGION_MEMORY and PCI_REGION_MEM are a bit to similar and can be confusing when reading the code. Rename PCI_REGION_MEMORY to PCI_REGION_SYS_MEMORY to clarify its used for system memory mapping purposes. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
fd6646c0 |
|
07-Jan-2009 |
Anton Vorontsov <avorontsov@ru.mvista.com> |
mpc83xx: Add support for MPC83xx PCI-E controllers This patch adds support for MPC83xx PCI-E controllers in Root Complex mode. The patch is based on Tony Li and Dave Liu work[1]. Though unlike the original patch, by default we don't register PCI-E buses for use in U-Boot, we only configure the controllers for future use in other OSes (Linux). This is done because we don't have enough of spare BATs to map all the PCI-E regions. To actually use PCI-E in U-Boot, users should explicitly define CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES symbol in the board file. And only then U-Boot will able to access PCI-E, but at the cost of disabled address translation. [1] http://lists.denx.de/pipermail/u-boot/2008-January/027630.html Signed-off-by: Tony Li <tony.li@freescale.com> Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Acked-by: Dave Liu <daveliu@freescale.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com> |
#
30e76d5e |
|
21-Oct-2008 |
Kumar Gala <galak@kernel.crashing.org> |
pci: Allow for PCI addresses to be 64-bit PCI bus is inherently 64-bit. While not all system require access to the full 64-bit PCI address range some do. This allows those systems to enable the full PCI address width via CONFIG_SYS_PCI_64BIT. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Andrew Fleming-AFLEMING <afleming@freescale.com> Acked-by: Wolfgang Denk <wd@denx.de> |
#
36f32675 |
|
07-May-2008 |
Becky Bruce <bgill@freescale.com> |
Update pci code to use phys_addr_t Physical addrs need to be represented by phys_addr_t, not unsigned long. Otherwise, systems that use CONFIG_PHYS_64BIT are going to fail mightily. Signed-off-by: Becky Bruce <becky.bruce@freescale.com> |
#
63cec581 |
|
02-Aug-2007 |
Ed Swarthout <Ed.Swarthout@freescale.com> |
Make MPC8641's PCI/PCI-E driver a common driver for many FSL parts. All of the PCI/PCI-Express driver and initialization code that was in the MPC8641HPCN port has now been moved into the common drivers/fsl_pci_init.c. In a subsequent patch, this will be utilized by the 85xx ports as well. Common PCI-E IMMAP register blocks for FSL 85xx/86xx are added. Also enable the second PCI-Express controller on 8641 by getting its BATS and CFG_ setup right. Fixed a u16 vendor compiler warning in AHCI driver too. Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com> Signed-off-by: Zhang Wei <wei.zhang@freescale.com> Signed-off-by: Jon Loeliger <jdl@freescale.com> |
#
13a7fcdf |
|
19-Oct-2006 |
Jon Loeliger <jdl@freescale.com> |
* Fix a bunch of compiler warnings for gcc 4.0 Signed-off-by: Matthew McClintock <msm@freescale.com> |
#
f0e6f57f |
|
28-Jun-2006 |
Matthew McClintock <msm@freescale.com> |
* Added PCI-X #defines for PCI-X initialization Patch by Andy Fleming on 17-Mar-2006 Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
7b230f61 |
|
12-Mar-2006 |
Wolfgang Denk <wd@pollux.denx.de> |
Merge with git://git.kernel.org/pub/scm/boot/u-boot/u-boot.git#pci
|
#
993a2275 |
|
12-Mar-2006 |
Wolfgang Denk <wd@pollux.denx.de> |
Fix bad declaration on pci_cfgfunc_nothing Patch by Sam Song, 19 Jun 2005 |
#
a179012e |
|
11-Jan-2006 |
Kumar Gala <galak@kernel.crashing.org> |
Added support for PCI prefetchable region and BARs If a host controller sets up a region as prefetchable and a device's BAR denotes it as prefetchable, allocate the BAR into the prefetch region. If a BAR is prefetchable and no prefetchable region has been setup by the controller we fall back to allocating the BAR into the normally memory region. Patch by Kumar Gala 11 Jan 2006 |
#
c157d8e2 |
|
01-Aug-2005 |
Stefan Roese <sr@denx.de> |
Add support for AMCC PPC440EP/GR eval boards Yosemite and Yellowstone. Patch by Steven Blakeslee, 27 Jul 2005 |
#
7a8e9bed |
|
31-May-2003 |
Wolfgang Denk <wdenk> |
* Patch by Marc Singer, 29 May 2003: Fixed rarp boot method for IA32 and other little-endian CPUs. * Patch by Marc Singer, 28 May 2003: Added port I/O commands. * Patch by Matthew McClintock, 28 May 2003 - cpu/mpc824x/start.S: fix relocation code when booting from RAM - minor patches for utx8245 * Patch by Daniel Engstr�m, 28 May 2003: x86 update * Patch by Dave Ellis, 9 May 2003 + 27 May 2003: add nand flash support to SXNI855T configuration fix/extend nand flash support: - fix 'nand erase' command so does not erase bad blocks - fix 'nand write' command so does not write to bad blocks - fix nand_probe() so handles no flash detected properly - add doc/README.nand - add .jffs2 and .oob options to nand read/write - add 'nand bad' command to list bad blocks - add 'clean' option to 'nand erase' to write JFFS2 clean markers - make NAND read/write faster * Patch by Rune Torgersen, 23 May 2003: Update for MPC8266ADS board |
#
c7de829c |
|
19-Nov-2002 |
Wolfgang Denk <wdenk> |
* Patch by Thomas Frieden, 13 Nov 2002: Add code for AmigaOne board (preliminary merge to U-Boot, still WIP) * Patch by Jon Diekema, 12 Nov 2002: - Adding URL for IEEE OUI lookup - Making the autoboot #defines dependent on CONFIG_AUTOBOOT_KEYED being defined. - In the CONFIG_EXTRA_ENV_SETTINGS #define, the root-on-initrd and root-on-nfs macros are designed to switch how the default boot method gets defined. |
#
c609719b |
|
02-Nov-2002 |
Wolfgang Denk <wdenk> |
Initial revision |
#
2a8d4025 |
|
26-Nov-2021 |
Pali Rohár <pali@kernel.org> |
pci: Add standard PCI Config Address macros Lot of PCI and PCIe controllers are using standard Config Address for PCI Configuration Mechanism #1 or its extended version. So add PCI_CONF1_ADDRESS() and PCI_CONF1_EXT_ADDRESS() macros into U-Boot's pci.h header file which can be suitable for most PCI and PCIe controller drivers. Drivers do not have to invent their own macros and can use these new U-Boot macros. Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
a4bc38da |
|
02-Nov-2021 |
Pali Rohár <pali@kernel.org> |
pci: Add standard PCIe ECAM macros Lot of PCIe controllers are using ECAM addressing. So add common ECAM macros into U-Boot's pci.h header file which can be suitable for most PCI controller drivers. Replace custom ECAM address macros in every PCI controller driver by new ECAM macros from U-Boot's pci.h header file. Similar macros are defined also in Linux kernel. There is a small difference between Linux and these new U-Boot macros. U-Boot's PCIE_ECAM_OFFSET() takes device and function numbers in separate arguments. Linux's PCIE_ECAM_OFFSET() takes device and function numbers encoded in one argument. The reason is that U-Boot's PCI_DEVFN() macro is different than Linux's PCI_SLOT() macro. So having device and function numbers in separate arguments makes code more straightforward. Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Stefan Roese <sr@denx.de> |
#
1d7ad685 |
|
25-Sep-2021 |
Pali Rohár <pali@kernel.org> |
arm: a37xx: pci: Handle propagation of CRSSVE bit from PCIe Root Port Now that PCI Bridge (PCIe Root Port) for Aardvark is emulated in U-Boot, add support for handling and propagation of CRSSVE bit. When CRSSVE bit is unset (default), driver has to reissue config read/write request on CRS response. CRSSVE bit is supported only when CRSVIS bit is provided in read-only Root Capabilities register. So manually inject this CRSVIS bit into read response for that register. Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Stefan Roese <sr@denx.de> |
#
2649f69f |
|
17-Sep-2021 |
Vladimir Oltean <vladimir.oltean@nxp.com> |
pci: provide prototype for pci_skip_dev outside of #if defined(CONFIG_DM_PCI_COMPAT) The weak definition of pci_skip_dev from drivers/pci/pci_common.c is not under CONFIG_DM_PCI_COMPAT, and that definition needs a previous function prototype declaration to avoid W=1 build warnings. That prototype is not available due to it being under CONFIG_DM_PCI_COMPAT, so move it outside of that preprocessor block. Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
23cacd57 |
|
01-Aug-2021 |
Simon Glass <sjg@chromium.org> |
pci: Drop PCI_INDIRECT_BRIDGE This does not work with driver model so can be removed. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
26543cc6 |
|
01-Aug-2021 |
Simon Glass <sjg@chromium.org> |
pci: Drop old code from header file We don't need this code anymore since when PCI is enabled, driver model is always used. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
63814a69 |
|
01-Aug-2021 |
Simon Glass <sjg@chromium.org> |
pci: imx: Drop DM_PCI check from cpu driver We don't need this check anymore since when PCI is enabled, driver model is always used. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
e8c09d69 |
|
01-Aug-2021 |
Simon Glass <sjg@chromium.org> |
pci: Remove guard around compatibility functions This prevents use of IS_ENABLED() in other files. Functions should be visible in headers even if they are not available at link time. Fix it. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
f5cbb5c7 |
|
27-Jun-2021 |
Simon Glass <sjg@chromium.org> |
x86: pci: Allow binding of some devices before relocation At present only bridge devices are bound before relocation, to save space in pre-relocation memory. In some cases we do actually want to bind a device, e.g. because it provides the console UART. Add a devicetree binding to support this. Use the PCI_VENDEV() macro to encode the cell value. This is present in U-Boot but not used, so move it to the binding header-file. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
e58f3a7d |
|
27-Jun-2021 |
Simon Glass <sjg@chromium.org> |
pci: Use const for pci_find_device_id() etc. These functions don't modify the device-ID struct that is passed in, so mark the argument as const, so the data structure can be declared that way. This allows it to be placed in the rodata section. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
c7b36007 |
|
14-May-2021 |
Tom Rini <trini@konsulko.com> |
pci: Remove non-DM board_pci_fixup_dev() declaration With the ventana boards migrated to DM_PCI and DM_ETH, we can remove this prototype. Cc: Stefano Babic <sbabic@denx.de> Signed-off-by: Tom Rini <trini@konsulko.com> |
#
cecd013f |
|
16-Apr-2021 |
Tim Harvey <tharvey@gateworks.com> |
pci: pci-uclass: Add board_pci_fixup_dev for DM_PCI Add a board_pci_fixup_dev weak function to allow PCI device fixups during enumeration. Signed-off-by: Tim Harvey <tharvey@gateworks.com> |
#
8b85dfc6 |
|
16-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: Avoid accessing seq directly At present various drivers etc. access the device's 'seq' member directly. This makes it harder to change the meaning of that member. Change access to go through a function instead. The drivers/i2c/lpc32xx_i2c.c file is left unchanged for now. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
caa4daa2 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename 'platdata' variables to just 'plat' We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
284d062e |
|
09-Sep-2020 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
pci: add a few ARI related defines Add a few defines related to PCI ARI configuration. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
51eeae91 |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add VF BAR map support for Enhanced Allocation Makes dm_pci_map_bar API available to map BAR for Virtual function PCI devices which support Enhanced Allocation. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> |
#
b8852dcf |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add support for Single-Root I/O Virtualization SR-IOV - Single Root I/O Virtualization PF - Physical Function VF - Virtual Function If SR-IOV capability is present, use it to initialize Virtual Function PCI device instances. pci_sriov_init function will read SR-IOV registers to create VF devices under the PF PCI device and also bind driver if available. This function needs to be invoked from Physical function device driver which expects VF device support, creating minimal impact on existing framework. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> |
#
e0024741 |
|
23-Jul-2020 |
Stefan Roese <sr@denx.de> |
pci: pci-uclass: Dynamically allocate the PCI regions Instead of using a fixed length pre-allocated array of regions, this patch moves to dynamically allocating the regions based on the number of available regions plus the necessary regions for DRAM banks. Since MAX_PCI_REGIONS is not needed any more, its removed completely with this patch. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Thierry Reding <treding@nvidia.com> Cc: Marek Vasut <marek.vasut+renesas@gmail.com> |
#
143eb5b1 |
|
12-May-2020 |
Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
drivers: pci: add api to get dma regions Add api to get dma regions. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com> |
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com> |
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com> |
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
7d994067 |
|
23-Apr-2019 |
Tom Rini <trini@konsulko.com> |
Merge tag 'pull-24apr19' of git://git.denx.de/u-boot-dm Various minor sandbox iumprovements Fixes for tracing with sandbox Refactoring for boot_get_fdt()
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
a8c5f8d3 |
|
15-Oct-2018 |
Bin Meng <bmeng.cn@gmail.com> |
dm: pci: Add APIs to find next capability and extended capability This introduces two new APIs dm_pci_find_next_capability() and dm_pci_find_next_ext_capability() to get PCI capability address and PCI express extended capability address for a given PCI device starting from a given offset. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
dac01fd8 |
|
03-Aug-2018 |
Bin Meng <bmeng.cn@gmail.com> |
dm: pci: Add APIs to find capability and extended capability This introduces two new APIs dm_pci_find_capability() and dm_pci_find_ext_capability() to get PCI capability address and PCI express extended capability address for a given PCI device. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
5d544f96 |
|
03-Aug-2018 |
Bin Meng <bmeng.cn@gmail.com> |
pci: Add all known capability and extended capability ids Currently we don't have a complete list of capability and extended capability ids. This adds them. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
4345998a |
|
03-Aug-2018 |
Bin Meng <bmeng.cn@gmail.com> |
pci: sandbox: Support dynamically binding device driver At present all emulated sandbox pci devices must be present in the device tree in order to be used. The real world pci uclass driver supports pci device driver matching, and we should add such support on sandbox too. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
01259c93 |
|
03-Aug-2018 |
Bin Meng <bmeng.cn@gmail.com> |
pci: Remove 440ep-specific macros These macros should not be put in the generic pci.h header file. Since they are not referenced anywhere, remove them completely. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
5ce9aca8 |
|
14-May-2018 |
Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi> |
PCI: Document pciauto_region_allocate() Add a doc comment for pciauto_region_allocate(). Signed-off-by: Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
d71975ae |
|
14-May-2018 |
Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi> |
PCI: autoconfig: Don't allocate 64-bit addresses to 32-bit only resources Currently, if we happen to allocate an address requiring 64 bits to a device only supporting 32-bit BARs, the address eventually gets silently truncated to 32 bits. Avoid this by adding a new flag to pciauto_region_allocate() to bail out in such situations. Signed-off-by: Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
83d290c5 |
|
06-May-2018 |
Tom Rini <trini@konsulko.com> |
SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com> |
#
ed68ccbf |
|
13-Mar-2018 |
Stefan Roese <sr@denx.de> |
pci: Remove unused ppc4xx variable from struct pci_controller ppc4xx support was removed some time ago. Lets remove the now unused "pci_fb" variable from "struct pci_controller" as well. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Simon Glass <sjg@chromium.org> |
#
badb9922 |
|
19-Sep-2017 |
Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi> |
pci: Add helper for implementing memory-mapped config space accesses This sort of pattern for implementing memory-mapped PCI config space accesses appears in U-Boot twice already, and a third user is coming up. So add helper functions to avoid code duplication, similar to how Linux has pci_generic_config_write and pci_generic_config_read. Signed-off-by: Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
6ecbe137 |
|
12-May-2017 |
Tim Harvey <tharvey@gateworks.com> |
drivers: pci: imx: add imx_pcie_remove function There is no dedicated reset signal wired up for the MX6QDL thus if the bootloader enables the link we need some special handling to get the core back into a state where it is safe to touch it for configuration. While there has been some special handling in the Linux kernel to do this, it was removed in 4.11 thus we need to do it properly in the bootloader and therefore without this if you enable PCI in the bootloader you will hang while booting the 4.11 kernel. This puts the PCIe controller back into a safe state for the kernel driver before launching the kernel. Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com> Tested-by: Peter Senna Tschudin <peter.senna@collabora.com> |
#
eeb5b1ad |
|
10-Mar-2016 |
Stuart Yoder <stuart.yoder@nxp.com> |
pci: make pci_get_hose_head() available to external users Put pci_get_hose_head() prototype in header so it is available to external users, allowing them to find and iterate over all pci controllers. Signed-off-by: Stuart Yoder <stuart.yoder@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
4974a6ff |
|
06-Mar-2016 |
Simon Glass <sjg@chromium.org> |
pci: Correct a few comments and nits Two comments are missing a parameter and there is an extra blank line. Also two of the region access macros are misnamed. Correct these problems. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
319dba1f |
|
06-Mar-2016 |
Simon Glass <sjg@chromium.org> |
pci: Add functions to update PCI configuration registers It is common to read a config register value, clear and set some bits, then write back the updated value. Add functions to do this in one step, for convenience. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
308143ef |
|
02-Feb-2016 |
Bin Meng <bmeng.cn@gmail.com> |
dm: pci: Add missing forward declarations When CONFIG_DM_PCI_COMPAT is not on, there is only a forward declaration for pci_write_config32(). Add other missing ones. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
9d731c82 |
|
18-Jan-2016 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to write a BAR Add a driver-model version of the pci_write_bar32 function so that this is supported in the new API. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
7e78b9ef |
|
29-Nov-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Switch to DM API for PCI address mapping We should use the new address mapping functions unless we are in compatibility mode. Disable the old functions by default. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
21d1fe7e |
|
29-Nov-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add driver model API functions for address mapping At present the PCI address map functions use the old API. Add new functions for this so that drivers can be converted. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
bab17cf1 |
|
29-Nov-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR Add a driver-model function for reading the PCI BAR from a device. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
a0eb8356 |
|
29-Nov-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a driver-model version of pci_find_class() Add a function which scans the driver model device information rather than scanning the PCI bus again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> |
#
5c0bf647 |
|
29-Nov-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a driver-model version of pci_find_device() Add a function which scans the driver model device information rather than scanning the PCI bus again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> |
#
5e23b8b4 |
|
29-Nov-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Use driver model PCI API in auto-config At present we are using legacy functions even in the auto-configuration code used by driver model. Add a new pci_auto.c version which uses the correct API. Create a new pci_internal.h header to hold functions that are used within the PCI subsystem, but are not exported to other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> |
#
f3f1faef |
|
29-Nov-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a dm_ prefix to pci_bus_find_bdf() Most driver model PCI functions have a dm_ prefix. At some point, when the old code is converted to driver model and the old functions are removed, we will drop that prefix. For consistency, we should use the dm_ prefix for all driver model functions. Update pci_bus_find_bdf() accordingly. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
21ccce1b |
|
29-Nov-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a dm_ prefix to pci_get_bdf() Most driver model PCI functions have a dm_ prefix. At some point, when the old code is converted to driver model and the old functions are removed, we will drop that prefix. For consistency, we should use the dm_ prefix for all driver model functions. Update pci_get_bdf() accordingly. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
3ba5f74a |
|
26-Nov-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Disable PCI compatibility functions by default We eventually need to drop the compatibility functions for driver model. As a first step, create a configuration option to enable them and hide them when the option is disabled. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
54fe7b1c |
|
26-Nov-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a comment about how to find struct pci_controller With driver mode, struct pci_controller is stored as uclass-private data. Add a comment to that effect. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
f9260336 |
|
19-Nov-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to find the regions for a PCI bus This function looks up the controller and returns a pointer to each region type. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Stephen Warren <swarren@nvidia.com> Tested-by: Stephen Warren <swarren@nvidia.com> |
#
9f60fb0d |
|
19-Nov-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to get the controller for a bus A PCI bus may be a bridge device where the controller is the bridge's parent. Add a function to return the controller device, given a PCI device. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Stephen Warren <swarren@nvidia.com> Tested-by: Stephen Warren <swarren@nvidia.com> |
#
9289db6c |
|
19-Nov-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add functions to emulate 8- and 16-bit access Provide a few functions to support using 32-bit access to emulate 8- and 16-bit access. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Stephen Warren <swarren@nvidia.com> Tested-by: Stephen Warren <swarren@nvidia.com> |
#
bcbe3d15 |
|
28-Sep-2015 |
Simon Glass <sjg@chromium.org> |
dm: Rename dev_get_parentdata() to dev_get_parent_priv() The current name is inconsistent with other driver model data access functions. Rename it and fix up all users. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Joe Hershberger <joe.hershberger@ni.com> |
#
dc5740df |
|
22-Aug-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a comment to help find pci_hose_read_config_byte, etc. These functions are defined by macros so do not show up with grep. Add a comment to help. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
76c3fbcd |
|
10-Aug-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a way to iterate through all PCI devices These functions allow iteration through all PCI devices including bridges. The children of each PCI bus are returned in turn. This can be useful for configuring, checking or enumerating all the devices. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
66afb4ed |
|
10-Aug-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Provide friendly config access functions At present there are no PCI functions which allow access to PCI configuration using a struct udevice. This is a sad situation for driver model as it makes use of PCI harder. Add these functions. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
5f48d798 |
|
27-Jul-2015 |
Simon Glass <sjg@chromium.org> |
pci: Add a constant for an invalid interrupt Rather than using 0xff in the code, add a constant. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
ed5b580b |
|
09-Jul-2015 |
Minghuan Lian <Minghuan.Lian@freescale.com> |
drivers/pci: Add function to find an extended capability PCIe extends device's configuration space to 4k and provides extended capability. The patch adds function to find them. The code is ported from Linux PCIe driver. Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
4b515e4f |
|
06-Jul-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to get the BDF for a device It is useful to be able to find the full PCI address (bus, device and function) for a PCI device. Add a function to provide this. Adjust the existing code to use this. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
aba92962 |
|
06-Jul-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add support for PCI driver matching At present all PCI devices must be present in the device tree in order to be used. Many or most PCI devices don't require any configuration other than that which is done automatically by U-Boot. It is inefficent to add a node with nothing but a compatible string in order to get a device working. Add a mechanism whereby PCI drivers can be declared along with the device parameters they support (vendor/device/class). When no suitable driver is found in the device tree the list of such devices is consulted to determine the correct driver. If this also fails, then a generic driver is used as before. The mechanism used is very similar to that provided by Linux and the header file defintions are copied from Linux 4.1. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Joe Hershberger <joe.hershberger@ni.com> |
#
6c89663c |
|
07-Jul-2015 |
Bin Meng <bmeng.cn@gmail.com> |
pci: Configure expansion ROM during auto config process Currently PCI expansion ROM address is assigned by a call to pciauto_setup_rom() outside of the pci auto config process. This does not work when expansion ROM is on a device behind PCI bridge where bridge's memory limit register was already programmed to a value that does not cover the newly assigned expansion ROM address. To fix this, we should configure the ROM address during the auto config process. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Acked-by: Simon Glass <sjg@chromium.org> |
#
aec241df |
|
07-Jun-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Use the correct hose when configuring devices Only the PCI controller has access to the PCI region information. Make sure to use the controller (rather than any attached bridges) when configuring devices. This corrects a failure to scan and configure devices when driver model is enabled for PCI. Also add a comment to explain the problem. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
36d0d3b4 |
|
05-Mar-2015 |
Simon Glass <sjg@chromium.org> |
dm: sandbox: pci: Add a PCI emulation uclass Since sandbox does not have real devices (unless it borrows those from the host) it must use emulations. Provide a uclass which permits PCI operations to be passed through to an emulation device. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
ff3e077b |
|
05-Mar-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a uclass for PCI Add a uclass for PCI controllers and a generic one for PCI devices. Adjust the 'pci' command and the existing PCI support to work with this new uclass. Keep most of the compatibility code in a separate file so that it can be removed one day. TODO: Add more header file comments to the new parts of pci.h Signed-off-by: Simon Glass <sjg@chromium.org> |
#
aab6724c |
|
05-Mar-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move common PCI functions into their own file Driver model will share many functions with the existing PCI implementation. Move these into their own file to avoid duplication and confusion. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
250e039d |
|
27-Jan-2015 |
Simon Glass <sjg@chromium.org> |
pci: Add a function to find a device by class There is an existing function prototype in the header file but it is not implemented. Implement something similar. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
4a2708a0 |
|
14-Jan-2015 |
Simon Glass <sjg@chromium.org> |
x86: Access the VGA ROM when needed Add code to the generic pci_rom file to access the VGA ROM in PCI space when needed. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
d622ac39 |
|
15-Dec-2014 |
Masahiro Yamada <yamada.m@jp.panasonic.com> |
powerpc: mpc824x: remove MPC824X cpu support All the MPC824X boards are still non-generic boards: A3000, CPC45, CU824, eXalion, MVBLUE, MUSENKI, Sandpoint824x, utx8245 Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Josef Wagner <Wagner@Microsys.de> Cc: Torsten Demke <torsten.demke@fci.com> Cc: Jim Thompson <jim@musenki.com> Cc: Greg Allen <gallen@arlut.utexas.edu> |
#
e8a552eb |
|
14-Nov-2014 |
Simon Glass <sjg@chromium.org> |
pci: Add functions to read and write a BAR address Some PCI functions cannot be auto-configured. Add a function to set up a fixed BAR which can be used in these situations. Also add a function to read the current address of a BAR. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
4efe52bf |
|
12-Nov-2014 |
Thierry Reding <treding@nvidia.com> |
pci: Honour pci_skip_dev() When enumerating devices, honour the pci_skip_dev() function. This can be used by PCI controller drivers to restrict which devices will be probed. This is required by the NVIDIA Tegra PCIe controller driver, which will fail with a data abort exception if an access is attempted to a device number larger than 0 outside of bus 0. pci_skip_dev() is therefore implemented to prevent any such accesses. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Simon Glass <sjg@chromium.org> |
#
0991866c |
|
07-Aug-2014 |
Tim Harvey <tharvey@gateworks.com> |
pci: add support for board_pci_fixup_dev function Some board-level drivers may wish to have per-device fixup functions for PCI devices. Signed-off-by: Tim Harvey <tharvey@gateworks.com> |
#
fa5cec03 |
|
08-Nov-2013 |
Paul Burton <paul.burton@mips.com> |
pci.h: allow inclusion in assembly source This patch simply #ifdef's out the C-specific parts of pci.h when it is included by an assembly file. This will allow the macros it contains to be used from assembly source as will be done in a followup commit adding support for more modern MIPS Malta boards. Signed-off-by: Paul Burton <paul.burton@imgtec.com> |
#
287df01e |
|
11-Oct-2013 |
Zhao Qiang <B45475@freescale.com> |
PCIe:change the method to get the address of a requested capability in configuration space. Previously, the address of a requested capability is define like that "#define PCI_DCR 0x78" But, the addresses of capabilities is different with regard to PCIe revs. So this method is not flexible. Now a function to get the address of a requested capability is added and used. It can get the address dynamically by capability ID. The step of this function: 1. Read Status register in PCIe configuration space to confirm that Capabilities List is valid. 2. Find the address of Capabilities Pointer Register. 3. Find the address of requested capability from the first capability. Signed-off-by: Zhao Qiang <B45475@freescale.com> |
#
7b4e5844 |
|
03-Jul-2013 |
Zang Roy-R61911 <tie-fei.zang@freescale.com> |
powerpc/pcie: add PCIe version 3.x support T4240 PCIe IP is version 3.0 and has some update comparing previous QorIQ products. 1. Move Freescale specific register define to arch/powerpc/include/asm/fsl_pci.h and update the register offset define for T4240. 2. add the status/control register define use status/control register to judge the link status 3. The original code uses 'Programming Interface' field to judge if PCIE is EP or RC mode, however, T4240 does not support this functionality. According to PCIE specification, 'Header Type' offset 0x0e is used to indicate header type, so for PCIE controller, the patch changes code to use 'Header Type' field to identify if the PCIE is RC or EP mode. This patch fixes the PCIe card link up issue on T4240QDS. Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com> |
#
1a459660 |
|
08-Jul-2013 |
Wolfgang Denk <wd@denx.de> |
Add GPL-2.0+ SPDX-License-Identifier to source files Signed-off-by: Wolfgang Denk <wd@denx.de> [trini: Fixup common/cmd_io.c] Signed-off-by: Tom Rini <trini@ti.com> |
#
bc3442aa |
|
11-Jun-2013 |
Simon Glass <sjg@chromium.org> |
pci: Convert extern inline functions to static inline I am not sure of the meaning of extern inline, but this gives errors when building with function instrumenting enabled. Change these functions to static inline. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
842033e6 |
|
30-May-2013 |
Gabor Juhos <juhosg@openwrt.org> |
pci: introduce CONFIG_PCI_INDIRECT_BRIDGE option The pci_indirect.c file is always compiled when CONFIG_PCI is defined although the indirect PCI bridge support is not needed by every board. Introduce a new CONFIG_PCI_INDIRECT_BRIDGE config option and only compile indirect PCI bridge support if this options is enabled. Also add the new option into the configuration files of the boards which needs that. Compile tested for powerpc, x86, arm and nds32. MAKEALL results: powerpc: --------------------- SUMMARY ---------------------------- Boards compiled: 641 Boards with warnings but no errors: 2 ( ELPPC MPC8323ERDB ) ---------------------------------------------------------- Note: the warnings for ELPPC and MPC8323ERDB are present even without the actual patch. x86: --------------------- SUMMARY ---------------------------- Boards compiled: 1 ---------------------------------------------------------- arm: --------------------- SUMMARY ---------------------------- Boards compiled: 311 ---------------------------------------------------------- nds32: --------------------- SUMMARY ---------------------------- Boards compiled: 3 ---------------------------------------------------------- Cc: Tom Rini <trini@ti.com> Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com> Signed-off-by: Gabor Juhos <juhosg@openwrt.org> |
#
55ae10f8 |
|
20-Oct-2012 |
Bill Richardson <wfrichar@chromium.org> |
x86: gpio: Add GPIO driver for Intel ICH6 and later. Implement <asm-generic/gpio.h> functions for Intel ICH6 and later. Only GPIOs 0-31 are handled by this code. Signed-off-by: Bill Richardson <wfrichar@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org> |
#
a3a70725 |
|
24-Mar-2012 |
Linus Walleij <linus.walleij@linaro.org> |
pci: declare pciauto functions in header The FSL PCI driver uses local prototypes for pciauto_[pre|post]scan_setup_bridge(), this does not seem right, so move them to the <pci.h> file. Fixed a small extern declaration too, this is harmless but distracts the view since all other prototypes are explicitly external. Signed-off-by: Linus Walleij <linus.walleij@linaro.org> |
#
a1e47b66 |
|
03-Mar-2012 |
Linus Walleij <linus.walleij@linaro.org> |
pci: move pciauto_config_init() to pci.h Fixing build regressions for the Integrator I get find that a few boards try to work around the missing declaration of pciauto_config_init() by declaring it in the local scope. This does not make sense when the sibling functions are in <pci.h> so move the function to the header, ridding the build error in the Integrator and getting rid of the local declarations here and there. Reported-by: Wolfgang Denk <wd@denx.de> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> |
#
b03a466d |
|
01-Feb-2011 |
Prabhakar Kushwaha <prabhakar@freescale.com> |
powerpc/85xx: Handle PCIe initialization requires for P1021 class SoCs The P1011, P1012, P1015, P1016, P1020, P1021, P1024, & P1025 SoCs require that we initialize the SERDES registers if the lanes are configured for PCIe. Additionally these devices PCIe controller do not support ASPM and we have to explicitly disable it. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
10fa8d7c |
|
19-Jan-2011 |
Leo Liu <liucai.lfn@gmail.com> |
mpc83xx: fix pcie configuration space read/write This patch fix a problem for the pcie enumeration when the mpc83xx pcie controller is connected with switch or we use both of the two pcie controller. Signed-off-by: Leo Liu <liucai.lfn@gmail.com> fix codingstyle and compiler warning: 'pcie_priv' defined but not used Signed-off-by: Kim Phillips <kim.phillips@freescale.com> |
#
3a0e3c27 |
|
17-Dec-2010 |
Kumar Gala <galak@kernel.crashing.org> |
powerpc/fsl-pci: Determine pci_controller based on cfg addr for dts fixup Previously we passed in a specifically named struct pci_controller to determine if we had setup the particular PCI bus. Now we can search for the struct so we dont have to depend on the name or the struct being statically allocated. Introduced new find_hose_by_cfg_addr() to get back a pci_controller struct back by searching for it means we can do things like dynamically allocate them or not have to expose the static structures to all users. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Wolfgang Denk <wd@denx.de> |
#
983eb9d1 |
|
29-Oct-2010 |
Peter Tyser <ptyser@xes-inc.com> |
pci: Clean up PCI info when CONFIG_PCI_SCAN_SHOW This change does the following: - Removes the printing of the PCI interrupt line value. This is normally set to 0 by U-Boot on bootup and is rarely used during everyday operation. - Prints out the PCI function number of a device. Previously a device with multiple functions would be printed identically 2 times, which is generally confusing. For example, on an Intel 2 port gigabit Ethernet card the following was displayed: ... 04 01 8086 1010 0200 00 04 01 8086 1010 0200 00 ... - Prints a text description of each device's PCI class instead of the raw PCI class code. The textual description makes it much easier to determine what devices are installed on a PCI bus. - Changes the general formatting of the PCI device output. Previous output: PCIE1: connected as Root Complex 04 01 8086 1010 0200 00 04 01 8086 1010 0200 00 03 00 10b5 8112 0604 00 02 01 10b5 8518 0604 00 02 02 10b5 8518 0604 00 08 00 1957 0040 0b20 00 07 00 10b5 8518 0604 00 09 00 10b5 8112 0604 00 07 01 10b5 8518 0604 00 07 02 10b5 8518 0604 00 06 00 10b5 8518 0604 00 02 03 10b5 8518 0604 00 01 00 10b5 8518 0604 00 PCIE1: Bus 00 - 0b PCIE2: connected as Root Complex 0d 00 1957 0040 0b20 00 PCIE2: Bus 0c - 0d Updated output: PCIE1: connected as Root Complex 04:01.0 - 8086:1010 - Network controller 04:01.1 - 8086:1010 - Network controller 03:00.0 - 10b5:8112 - Bridge device 02:01.0 - 10b5:8518 - Bridge device 02:02.0 - 10b5:8518 - Bridge device 08:00.0 - 1957:0040 - Processor 07:00.0 - 10b5:8518 - Bridge device 09:00.0 - 10b5:8112 - Bridge device 07:01.0 - 10b5:8518 - Bridge device 07:02.0 - 10b5:8518 - Bridge device 06:00.0 - 10b5:8518 - Bridge device 02:03.0 - 10b5:8518 - Bridge device 01:00.0 - 10b5:8518 - Bridge device PCIE1: Bus 00 - 0b PCIE2: connected as Root Complex 0d:00.0 - 1957:0040 - Processor PCIE2: Bus 0c - 0d Signed-off-by: Peter Tyser <ptyser@xes-inc.com> |
#
8295b944 |
|
05-Aug-2009 |
Kumar Gala <galak@kernel.crashing.org> |
pci/fsl_pci_init: Use PCIe capability to determine if controller is PCIe Change the code to use the PCIe capabilities register to determine if we are a PCIe controller or not. Additionally cleaned up some white space and formatting in the file. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
cc2a8c77 |
|
19-Feb-2009 |
Anton Vorontsov <avorontsov@ru.mvista.com> |
PCI: Add pci_last_busno() helper This is just a handy routine that reports last PCI busno: we walk down all the hoses and return last hose's last_busno. Will be used by PCI/PCIe initialization code. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com> |
#
6e61fae4 |
|
03-Feb-2009 |
Becky Bruce <beckyb@kernel.crashing.org> |
drivers/pci: Create pci_map_bar function It is no longer always true that the pci bus address can be used as the virtual address for pci accesses. pci_map_bar() is created to return the virtual address for a pci region. Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org> |
#
ff4e66e9 |
|
06-Feb-2009 |
Kumar Gala <galak@kernel.crashing.org> |
pci: Rename PCI_REGION_MEMORY to PCI_REGION_SYS_MEMORY for clarity The PCI_REGION_MEMORY and PCI_REGION_MEM are a bit to similar and can be confusing when reading the code. Rename PCI_REGION_MEMORY to PCI_REGION_SYS_MEMORY to clarify its used for system memory mapping purposes. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
fd6646c0 |
|
07-Jan-2009 |
Anton Vorontsov <avorontsov@ru.mvista.com> |
mpc83xx: Add support for MPC83xx PCI-E controllers This patch adds support for MPC83xx PCI-E controllers in Root Complex mode. The patch is based on Tony Li and Dave Liu work[1]. Though unlike the original patch, by default we don't register PCI-E buses for use in U-Boot, we only configure the controllers for future use in other OSes (Linux). This is done because we don't have enough of spare BATs to map all the PCI-E regions. To actually use PCI-E in U-Boot, users should explicitly define CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES symbol in the board file. And only then U-Boot will able to access PCI-E, but at the cost of disabled address translation. [1] http://lists.denx.de/pipermail/u-boot/2008-January/027630.html Signed-off-by: Tony Li <tony.li@freescale.com> Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Acked-by: Dave Liu <daveliu@freescale.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com> |
#
30e76d5e |
|
21-Oct-2008 |
Kumar Gala <galak@kernel.crashing.org> |
pci: Allow for PCI addresses to be 64-bit PCI bus is inherently 64-bit. While not all system require access to the full 64-bit PCI address range some do. This allows those systems to enable the full PCI address width via CONFIG_SYS_PCI_64BIT. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Andrew Fleming-AFLEMING <afleming@freescale.com> Acked-by: Wolfgang Denk <wd@denx.de> |
#
36f32675 |
|
07-May-2008 |
Becky Bruce <bgill@freescale.com> |
Update pci code to use phys_addr_t Physical addrs need to be represented by phys_addr_t, not unsigned long. Otherwise, systems that use CONFIG_PHYS_64BIT are going to fail mightily. Signed-off-by: Becky Bruce <becky.bruce@freescale.com> |
#
63cec581 |
|
02-Aug-2007 |
Ed Swarthout <Ed.Swarthout@freescale.com> |
Make MPC8641's PCI/PCI-E driver a common driver for many FSL parts. All of the PCI/PCI-Express driver and initialization code that was in the MPC8641HPCN port has now been moved into the common drivers/fsl_pci_init.c. In a subsequent patch, this will be utilized by the 85xx ports as well. Common PCI-E IMMAP register blocks for FSL 85xx/86xx are added. Also enable the second PCI-Express controller on 8641 by getting its BATS and CFG_ setup right. Fixed a u16 vendor compiler warning in AHCI driver too. Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com> Signed-off-by: Zhang Wei <wei.zhang@freescale.com> Signed-off-by: Jon Loeliger <jdl@freescale.com> |
#
13a7fcdf |
|
19-Oct-2006 |
Jon Loeliger <jdl@freescale.com> |
* Fix a bunch of compiler warnings for gcc 4.0 Signed-off-by: Matthew McClintock <msm@freescale.com> |
#
f0e6f57f |
|
28-Jun-2006 |
Matthew McClintock <msm@freescale.com> |
* Added PCI-X #defines for PCI-X initialization Patch by Andy Fleming on 17-Mar-2006 Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
7b230f61 |
|
12-Mar-2006 |
Wolfgang Denk <wd@pollux.denx.de> |
Merge with git://git.kernel.org/pub/scm/boot/u-boot/u-boot.git#pci
|
#
993a2275 |
|
12-Mar-2006 |
Wolfgang Denk <wd@pollux.denx.de> |
Fix bad declaration on pci_cfgfunc_nothing Patch by Sam Song, 19 Jun 2005 |
#
a179012e |
|
11-Jan-2006 |
Kumar Gala <galak@kernel.crashing.org> |
Added support for PCI prefetchable region and BARs If a host controller sets up a region as prefetchable and a device's BAR denotes it as prefetchable, allocate the BAR into the prefetch region. If a BAR is prefetchable and no prefetchable region has been setup by the controller we fall back to allocating the BAR into the normally memory region. Patch by Kumar Gala 11 Jan 2006 |
#
c157d8e2 |
|
01-Aug-2005 |
Stefan Roese <sr@denx.de> |
Add support for AMCC PPC440EP/GR eval boards Yosemite and Yellowstone. Patch by Steven Blakeslee, 27 Jul 2005 |
#
7a8e9bed |
|
31-May-2003 |
Wolfgang Denk <wdenk> |
* Patch by Marc Singer, 29 May 2003: Fixed rarp boot method for IA32 and other little-endian CPUs. * Patch by Marc Singer, 28 May 2003: Added port I/O commands. * Patch by Matthew McClintock, 28 May 2003 - cpu/mpc824x/start.S: fix relocation code when booting from RAM - minor patches for utx8245 * Patch by Daniel Engstr�m, 28 May 2003: x86 update * Patch by Dave Ellis, 9 May 2003 + 27 May 2003: add nand flash support to SXNI855T configuration fix/extend nand flash support: - fix 'nand erase' command so does not erase bad blocks - fix 'nand write' command so does not write to bad blocks - fix nand_probe() so handles no flash detected properly - add doc/README.nand - add .jffs2 and .oob options to nand read/write - add 'nand bad' command to list bad blocks - add 'clean' option to 'nand erase' to write JFFS2 clean markers - make NAND read/write faster * Patch by Rune Torgersen, 23 May 2003: Update for MPC8266ADS board |
#
c7de829c |
|
19-Nov-2002 |
Wolfgang Denk <wdenk> |
* Patch by Thomas Frieden, 13 Nov 2002: Add code for AmigaOne board (preliminary merge to U-Boot, still WIP) * Patch by Jon Diekema, 12 Nov 2002: - Adding URL for IEEE OUI lookup - Making the autoboot #defines dependent on CONFIG_AUTOBOOT_KEYED being defined. - In the CONFIG_EXTRA_ENV_SETTINGS #define, the root-on-initrd and root-on-nfs macros are designed to switch how the default boot method gets defined. |
#
c609719b |
|
02-Nov-2002 |
Wolfgang Denk <wdenk> |
Initial revision |
#
a4bc38da |
|
02-Nov-2021 |
Pali Rohár <pali@kernel.org> |
pci: Add standard PCIe ECAM macros Lot of PCIe controllers are using ECAM addressing. So add common ECAM macros into U-Boot's pci.h header file which can be suitable for most PCI controller drivers. Replace custom ECAM address macros in every PCI controller driver by new ECAM macros from U-Boot's pci.h header file. Similar macros are defined also in Linux kernel. There is a small difference between Linux and these new U-Boot macros. U-Boot's PCIE_ECAM_OFFSET() takes device and function numbers in separate arguments. Linux's PCIE_ECAM_OFFSET() takes device and function numbers encoded in one argument. The reason is that U-Boot's PCI_DEVFN() macro is different than Linux's PCI_SLOT() macro. So having device and function numbers in separate arguments makes code more straightforward. Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Stefan Roese <sr@denx.de> |
#
1d7ad685 |
|
25-Sep-2021 |
Pali Rohár <pali@kernel.org> |
arm: a37xx: pci: Handle propagation of CRSSVE bit from PCIe Root Port Now that PCI Bridge (PCIe Root Port) for Aardvark is emulated in U-Boot, add support for handling and propagation of CRSSVE bit. When CRSSVE bit is unset (default), driver has to reissue config read/write request on CRS response. CRSSVE bit is supported only when CRSVIS bit is provided in read-only Root Capabilities register. So manually inject this CRSVIS bit into read response for that register. Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Stefan Roese <sr@denx.de> |
#
2649f69f |
|
17-Sep-2021 |
Vladimir Oltean <vladimir.oltean@nxp.com> |
pci: provide prototype for pci_skip_dev outside of #if defined(CONFIG_DM_PCI_COMPAT) The weak definition of pci_skip_dev from drivers/pci/pci_common.c is not under CONFIG_DM_PCI_COMPAT, and that definition needs a previous function prototype declaration to avoid W=1 build warnings. That prototype is not available due to it being under CONFIG_DM_PCI_COMPAT, so move it outside of that preprocessor block. Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
23cacd57 |
|
01-Aug-2021 |
Simon Glass <sjg@chromium.org> |
pci: Drop PCI_INDIRECT_BRIDGE This does not work with driver model so can be removed. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
26543cc6 |
|
01-Aug-2021 |
Simon Glass <sjg@chromium.org> |
pci: Drop old code from header file We don't need this code anymore since when PCI is enabled, driver model is always used. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
63814a69 |
|
01-Aug-2021 |
Simon Glass <sjg@chromium.org> |
pci: imx: Drop DM_PCI check from cpu driver We don't need this check anymore since when PCI is enabled, driver model is always used. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
e8c09d69 |
|
01-Aug-2021 |
Simon Glass <sjg@chromium.org> |
pci: Remove guard around compatibility functions This prevents use of IS_ENABLED() in other files. Functions should be visible in headers even if they are not available at link time. Fix it. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
f5cbb5c7 |
|
27-Jun-2021 |
Simon Glass <sjg@chromium.org> |
x86: pci: Allow binding of some devices before relocation At present only bridge devices are bound before relocation, to save space in pre-relocation memory. In some cases we do actually want to bind a device, e.g. because it provides the console UART. Add a devicetree binding to support this. Use the PCI_VENDEV() macro to encode the cell value. This is present in U-Boot but not used, so move it to the binding header-file. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
e58f3a7d |
|
27-Jun-2021 |
Simon Glass <sjg@chromium.org> |
pci: Use const for pci_find_device_id() etc. These functions don't modify the device-ID struct that is passed in, so mark the argument as const, so the data structure can be declared that way. This allows it to be placed in the rodata section. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
c7b36007 |
|
14-May-2021 |
Tom Rini <trini@konsulko.com> |
pci: Remove non-DM board_pci_fixup_dev() declaration With the ventana boards migrated to DM_PCI and DM_ETH, we can remove this prototype. Cc: Stefano Babic <sbabic@denx.de> Signed-off-by: Tom Rini <trini@konsulko.com> |
#
cecd013f |
|
16-Apr-2021 |
Tim Harvey <tharvey@gateworks.com> |
pci: pci-uclass: Add board_pci_fixup_dev for DM_PCI Add a board_pci_fixup_dev weak function to allow PCI device fixups during enumeration. Signed-off-by: Tim Harvey <tharvey@gateworks.com> |
#
8b85dfc6 |
|
16-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: Avoid accessing seq directly At present various drivers etc. access the device's 'seq' member directly. This makes it harder to change the meaning of that member. Change access to go through a function instead. The drivers/i2c/lpc32xx_i2c.c file is left unchanged for now. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
caa4daa2 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename 'platdata' variables to just 'plat' We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
284d062e |
|
09-Sep-2020 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
pci: add a few ARI related defines Add a few defines related to PCI ARI configuration. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
51eeae91 |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add VF BAR map support for Enhanced Allocation Makes dm_pci_map_bar API available to map BAR for Virtual function PCI devices which support Enhanced Allocation. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> |
#
b8852dcf |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add support for Single-Root I/O Virtualization SR-IOV - Single Root I/O Virtualization PF - Physical Function VF - Virtual Function If SR-IOV capability is present, use it to initialize Virtual Function PCI device instances. pci_sriov_init function will read SR-IOV registers to create VF devices under the PF PCI device and also bind driver if available. This function needs to be invoked from Physical function device driver which expects VF device support, creating minimal impact on existing framework. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> |
#
e0024741 |
|
23-Jul-2020 |
Stefan Roese <sr@denx.de> |
pci: pci-uclass: Dynamically allocate the PCI regions Instead of using a fixed length pre-allocated array of regions, this patch moves to dynamically allocating the regions based on the number of available regions plus the necessary regions for DRAM banks. Since MAX_PCI_REGIONS is not needed any more, its removed completely with this patch. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Thierry Reding <treding@nvidia.com> Cc: Marek Vasut <marek.vasut+renesas@gmail.com> |
#
143eb5b1 |
|
12-May-2020 |
Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
drivers: pci: add api to get dma regions Add api to get dma regions. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com> |
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com> |
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com> |
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
7d994067 |
|
23-Apr-2019 |
Tom Rini <trini@konsulko.com> |
Merge tag 'pull-24apr19' of git://git.denx.de/u-boot-dm Various minor sandbox iumprovements Fixes for tracing with sandbox Refactoring for boot_get_fdt()
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
a8c5f8d3 |
|
15-Oct-2018 |
Bin Meng <bmeng.cn@gmail.com> |
dm: pci: Add APIs to find next capability and extended capability This introduces two new APIs dm_pci_find_next_capability() and dm_pci_find_next_ext_capability() to get PCI capability address and PCI express extended capability address for a given PCI device starting from a given offset. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
dac01fd8 |
|
03-Aug-2018 |
Bin Meng <bmeng.cn@gmail.com> |
dm: pci: Add APIs to find capability and extended capability This introduces two new APIs dm_pci_find_capability() and dm_pci_find_ext_capability() to get PCI capability address and PCI express extended capability address for a given PCI device. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
5d544f96 |
|
03-Aug-2018 |
Bin Meng <bmeng.cn@gmail.com> |
pci: Add all known capability and extended capability ids Currently we don't have a complete list of capability and extended capability ids. This adds them. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
4345998a |
|
03-Aug-2018 |
Bin Meng <bmeng.cn@gmail.com> |
pci: sandbox: Support dynamically binding device driver At present all emulated sandbox pci devices must be present in the device tree in order to be used. The real world pci uclass driver supports pci device driver matching, and we should add such support on sandbox too. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
01259c93 |
|
03-Aug-2018 |
Bin Meng <bmeng.cn@gmail.com> |
pci: Remove 440ep-specific macros These macros should not be put in the generic pci.h header file. Since they are not referenced anywhere, remove them completely. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
5ce9aca8 |
|
14-May-2018 |
Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi> |
PCI: Document pciauto_region_allocate() Add a doc comment for pciauto_region_allocate(). Signed-off-by: Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
d71975ae |
|
14-May-2018 |
Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi> |
PCI: autoconfig: Don't allocate 64-bit addresses to 32-bit only resources Currently, if we happen to allocate an address requiring 64 bits to a device only supporting 32-bit BARs, the address eventually gets silently truncated to 32 bits. Avoid this by adding a new flag to pciauto_region_allocate() to bail out in such situations. Signed-off-by: Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
83d290c5 |
|
06-May-2018 |
Tom Rini <trini@konsulko.com> |
SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com> |
#
ed68ccbf |
|
13-Mar-2018 |
Stefan Roese <sr@denx.de> |
pci: Remove unused ppc4xx variable from struct pci_controller ppc4xx support was removed some time ago. Lets remove the now unused "pci_fb" variable from "struct pci_controller" as well. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Simon Glass <sjg@chromium.org> |
#
badb9922 |
|
19-Sep-2017 |
Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi> |
pci: Add helper for implementing memory-mapped config space accesses This sort of pattern for implementing memory-mapped PCI config space accesses appears in U-Boot twice already, and a third user is coming up. So add helper functions to avoid code duplication, similar to how Linux has pci_generic_config_write and pci_generic_config_read. Signed-off-by: Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
6ecbe137 |
|
12-May-2017 |
Tim Harvey <tharvey@gateworks.com> |
drivers: pci: imx: add imx_pcie_remove function There is no dedicated reset signal wired up for the MX6QDL thus if the bootloader enables the link we need some special handling to get the core back into a state where it is safe to touch it for configuration. While there has been some special handling in the Linux kernel to do this, it was removed in 4.11 thus we need to do it properly in the bootloader and therefore without this if you enable PCI in the bootloader you will hang while booting the 4.11 kernel. This puts the PCIe controller back into a safe state for the kernel driver before launching the kernel. Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com> Tested-by: Peter Senna Tschudin <peter.senna@collabora.com> |
#
eeb5b1ad |
|
10-Mar-2016 |
Stuart Yoder <stuart.yoder@nxp.com> |
pci: make pci_get_hose_head() available to external users Put pci_get_hose_head() prototype in header so it is available to external users, allowing them to find and iterate over all pci controllers. Signed-off-by: Stuart Yoder <stuart.yoder@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
4974a6ff |
|
06-Mar-2016 |
Simon Glass <sjg@chromium.org> |
pci: Correct a few comments and nits Two comments are missing a parameter and there is an extra blank line. Also two of the region access macros are misnamed. Correct these problems. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
319dba1f |
|
06-Mar-2016 |
Simon Glass <sjg@chromium.org> |
pci: Add functions to update PCI configuration registers It is common to read a config register value, clear and set some bits, then write back the updated value. Add functions to do this in one step, for convenience. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
308143ef |
|
02-Feb-2016 |
Bin Meng <bmeng.cn@gmail.com> |
dm: pci: Add missing forward declarations When CONFIG_DM_PCI_COMPAT is not on, there is only a forward declaration for pci_write_config32(). Add other missing ones. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
9d731c82 |
|
18-Jan-2016 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to write a BAR Add a driver-model version of the pci_write_bar32 function so that this is supported in the new API. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
7e78b9ef |
|
29-Nov-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Switch to DM API for PCI address mapping We should use the new address mapping functions unless we are in compatibility mode. Disable the old functions by default. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
21d1fe7e |
|
29-Nov-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add driver model API functions for address mapping At present the PCI address map functions use the old API. Add new functions for this so that drivers can be converted. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
bab17cf1 |
|
29-Nov-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR Add a driver-model function for reading the PCI BAR from a device. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
a0eb8356 |
|
29-Nov-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a driver-model version of pci_find_class() Add a function which scans the driver model device information rather than scanning the PCI bus again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> |
#
5c0bf647 |
|
29-Nov-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a driver-model version of pci_find_device() Add a function which scans the driver model device information rather than scanning the PCI bus again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> |
#
5e23b8b4 |
|
29-Nov-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Use driver model PCI API in auto-config At present we are using legacy functions even in the auto-configuration code used by driver model. Add a new pci_auto.c version which uses the correct API. Create a new pci_internal.h header to hold functions that are used within the PCI subsystem, but are not exported to other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> |
#
f3f1faef |
|
29-Nov-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a dm_ prefix to pci_bus_find_bdf() Most driver model PCI functions have a dm_ prefix. At some point, when the old code is converted to driver model and the old functions are removed, we will drop that prefix. For consistency, we should use the dm_ prefix for all driver model functions. Update pci_bus_find_bdf() accordingly. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
21ccce1b |
|
29-Nov-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a dm_ prefix to pci_get_bdf() Most driver model PCI functions have a dm_ prefix. At some point, when the old code is converted to driver model and the old functions are removed, we will drop that prefix. For consistency, we should use the dm_ prefix for all driver model functions. Update pci_get_bdf() accordingly. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
3ba5f74a |
|
26-Nov-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Disable PCI compatibility functions by default We eventually need to drop the compatibility functions for driver model. As a first step, create a configuration option to enable them and hide them when the option is disabled. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
54fe7b1c |
|
26-Nov-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a comment about how to find struct pci_controller With driver mode, struct pci_controller is stored as uclass-private data. Add a comment to that effect. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
f9260336 |
|
19-Nov-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to find the regions for a PCI bus This function looks up the controller and returns a pointer to each region type. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Stephen Warren <swarren@nvidia.com> Tested-by: Stephen Warren <swarren@nvidia.com> |
#
9f60fb0d |
|
19-Nov-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to get the controller for a bus A PCI bus may be a bridge device where the controller is the bridge's parent. Add a function to return the controller device, given a PCI device. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Stephen Warren <swarren@nvidia.com> Tested-by: Stephen Warren <swarren@nvidia.com> |
#
9289db6c |
|
19-Nov-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add functions to emulate 8- and 16-bit access Provide a few functions to support using 32-bit access to emulate 8- and 16-bit access. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Stephen Warren <swarren@nvidia.com> Tested-by: Stephen Warren <swarren@nvidia.com> |
#
bcbe3d15 |
|
28-Sep-2015 |
Simon Glass <sjg@chromium.org> |
dm: Rename dev_get_parentdata() to dev_get_parent_priv() The current name is inconsistent with other driver model data access functions. Rename it and fix up all users. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Joe Hershberger <joe.hershberger@ni.com> |
#
dc5740df |
|
22-Aug-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a comment to help find pci_hose_read_config_byte, etc. These functions are defined by macros so do not show up with grep. Add a comment to help. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
76c3fbcd |
|
10-Aug-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a way to iterate through all PCI devices These functions allow iteration through all PCI devices including bridges. The children of each PCI bus are returned in turn. This can be useful for configuring, checking or enumerating all the devices. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
66afb4ed |
|
10-Aug-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Provide friendly config access functions At present there are no PCI functions which allow access to PCI configuration using a struct udevice. This is a sad situation for driver model as it makes use of PCI harder. Add these functions. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
5f48d798 |
|
27-Jul-2015 |
Simon Glass <sjg@chromium.org> |
pci: Add a constant for an invalid interrupt Rather than using 0xff in the code, add a constant. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
ed5b580b |
|
09-Jul-2015 |
Minghuan Lian <Minghuan.Lian@freescale.com> |
drivers/pci: Add function to find an extended capability PCIe extends device's configuration space to 4k and provides extended capability. The patch adds function to find them. The code is ported from Linux PCIe driver. Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
4b515e4f |
|
06-Jul-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to get the BDF for a device It is useful to be able to find the full PCI address (bus, device and function) for a PCI device. Add a function to provide this. Adjust the existing code to use this. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
aba92962 |
|
06-Jul-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add support for PCI driver matching At present all PCI devices must be present in the device tree in order to be used. Many or most PCI devices don't require any configuration other than that which is done automatically by U-Boot. It is inefficent to add a node with nothing but a compatible string in order to get a device working. Add a mechanism whereby PCI drivers can be declared along with the device parameters they support (vendor/device/class). When no suitable driver is found in the device tree the list of such devices is consulted to determine the correct driver. If this also fails, then a generic driver is used as before. The mechanism used is very similar to that provided by Linux and the header file defintions are copied from Linux 4.1. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Joe Hershberger <joe.hershberger@ni.com> |
#
6c89663c |
|
07-Jul-2015 |
Bin Meng <bmeng.cn@gmail.com> |
pci: Configure expansion ROM during auto config process Currently PCI expansion ROM address is assigned by a call to pciauto_setup_rom() outside of the pci auto config process. This does not work when expansion ROM is on a device behind PCI bridge where bridge's memory limit register was already programmed to a value that does not cover the newly assigned expansion ROM address. To fix this, we should configure the ROM address during the auto config process. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Acked-by: Simon Glass <sjg@chromium.org> |
#
aec241df |
|
07-Jun-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Use the correct hose when configuring devices Only the PCI controller has access to the PCI region information. Make sure to use the controller (rather than any attached bridges) when configuring devices. This corrects a failure to scan and configure devices when driver model is enabled for PCI. Also add a comment to explain the problem. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
36d0d3b4 |
|
05-Mar-2015 |
Simon Glass <sjg@chromium.org> |
dm: sandbox: pci: Add a PCI emulation uclass Since sandbox does not have real devices (unless it borrows those from the host) it must use emulations. Provide a uclass which permits PCI operations to be passed through to an emulation device. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
ff3e077b |
|
05-Mar-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a uclass for PCI Add a uclass for PCI controllers and a generic one for PCI devices. Adjust the 'pci' command and the existing PCI support to work with this new uclass. Keep most of the compatibility code in a separate file so that it can be removed one day. TODO: Add more header file comments to the new parts of pci.h Signed-off-by: Simon Glass <sjg@chromium.org> |
#
aab6724c |
|
05-Mar-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move common PCI functions into their own file Driver model will share many functions with the existing PCI implementation. Move these into their own file to avoid duplication and confusion. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
250e039d |
|
27-Jan-2015 |
Simon Glass <sjg@chromium.org> |
pci: Add a function to find a device by class There is an existing function prototype in the header file but it is not implemented. Implement something similar. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
4a2708a0 |
|
14-Jan-2015 |
Simon Glass <sjg@chromium.org> |
x86: Access the VGA ROM when needed Add code to the generic pci_rom file to access the VGA ROM in PCI space when needed. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
d622ac39 |
|
15-Dec-2014 |
Masahiro Yamada <yamada.m@jp.panasonic.com> |
powerpc: mpc824x: remove MPC824X cpu support All the MPC824X boards are still non-generic boards: A3000, CPC45, CU824, eXalion, MVBLUE, MUSENKI, Sandpoint824x, utx8245 Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Josef Wagner <Wagner@Microsys.de> Cc: Torsten Demke <torsten.demke@fci.com> Cc: Jim Thompson <jim@musenki.com> Cc: Greg Allen <gallen@arlut.utexas.edu> |
#
e8a552eb |
|
14-Nov-2014 |
Simon Glass <sjg@chromium.org> |
pci: Add functions to read and write a BAR address Some PCI functions cannot be auto-configured. Add a function to set up a fixed BAR which can be used in these situations. Also add a function to read the current address of a BAR. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
4efe52bf |
|
12-Nov-2014 |
Thierry Reding <treding@nvidia.com> |
pci: Honour pci_skip_dev() When enumerating devices, honour the pci_skip_dev() function. This can be used by PCI controller drivers to restrict which devices will be probed. This is required by the NVIDIA Tegra PCIe controller driver, which will fail with a data abort exception if an access is attempted to a device number larger than 0 outside of bus 0. pci_skip_dev() is therefore implemented to prevent any such accesses. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Simon Glass <sjg@chromium.org> |
#
0991866c |
|
07-Aug-2014 |
Tim Harvey <tharvey@gateworks.com> |
pci: add support for board_pci_fixup_dev function Some board-level drivers may wish to have per-device fixup functions for PCI devices. Signed-off-by: Tim Harvey <tharvey@gateworks.com> |
#
fa5cec03 |
|
08-Nov-2013 |
Paul Burton <paul.burton@mips.com> |
pci.h: allow inclusion in assembly source This patch simply #ifdef's out the C-specific parts of pci.h when it is included by an assembly file. This will allow the macros it contains to be used from assembly source as will be done in a followup commit adding support for more modern MIPS Malta boards. Signed-off-by: Paul Burton <paul.burton@imgtec.com> |
#
287df01e |
|
11-Oct-2013 |
Zhao Qiang <B45475@freescale.com> |
PCIe:change the method to get the address of a requested capability in configuration space. Previously, the address of a requested capability is define like that "#define PCI_DCR 0x78" But, the addresses of capabilities is different with regard to PCIe revs. So this method is not flexible. Now a function to get the address of a requested capability is added and used. It can get the address dynamically by capability ID. The step of this function: 1. Read Status register in PCIe configuration space to confirm that Capabilities List is valid. 2. Find the address of Capabilities Pointer Register. 3. Find the address of requested capability from the first capability. Signed-off-by: Zhao Qiang <B45475@freescale.com> |
#
7b4e5844 |
|
03-Jul-2013 |
Zang Roy-R61911 <tie-fei.zang@freescale.com> |
powerpc/pcie: add PCIe version 3.x support T4240 PCIe IP is version 3.0 and has some update comparing previous QorIQ products. 1. Move Freescale specific register define to arch/powerpc/include/asm/fsl_pci.h and update the register offset define for T4240. 2. add the status/control register define use status/control register to judge the link status 3. The original code uses 'Programming Interface' field to judge if PCIE is EP or RC mode, however, T4240 does not support this functionality. According to PCIE specification, 'Header Type' offset 0x0e is used to indicate header type, so for PCIE controller, the patch changes code to use 'Header Type' field to identify if the PCIE is RC or EP mode. This patch fixes the PCIe card link up issue on T4240QDS. Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com> |
#
1a459660 |
|
08-Jul-2013 |
Wolfgang Denk <wd@denx.de> |
Add GPL-2.0+ SPDX-License-Identifier to source files Signed-off-by: Wolfgang Denk <wd@denx.de> [trini: Fixup common/cmd_io.c] Signed-off-by: Tom Rini <trini@ti.com> |
#
bc3442aa |
|
11-Jun-2013 |
Simon Glass <sjg@chromium.org> |
pci: Convert extern inline functions to static inline I am not sure of the meaning of extern inline, but this gives errors when building with function instrumenting enabled. Change these functions to static inline. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
842033e6 |
|
30-May-2013 |
Gabor Juhos <juhosg@openwrt.org> |
pci: introduce CONFIG_PCI_INDIRECT_BRIDGE option The pci_indirect.c file is always compiled when CONFIG_PCI is defined although the indirect PCI bridge support is not needed by every board. Introduce a new CONFIG_PCI_INDIRECT_BRIDGE config option and only compile indirect PCI bridge support if this options is enabled. Also add the new option into the configuration files of the boards which needs that. Compile tested for powerpc, x86, arm and nds32. MAKEALL results: powerpc: --------------------- SUMMARY ---------------------------- Boards compiled: 641 Boards with warnings but no errors: 2 ( ELPPC MPC8323ERDB ) ---------------------------------------------------------- Note: the warnings for ELPPC and MPC8323ERDB are present even without the actual patch. x86: --------------------- SUMMARY ---------------------------- Boards compiled: 1 ---------------------------------------------------------- arm: --------------------- SUMMARY ---------------------------- Boards compiled: 311 ---------------------------------------------------------- nds32: --------------------- SUMMARY ---------------------------- Boards compiled: 3 ---------------------------------------------------------- Cc: Tom Rini <trini@ti.com> Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com> Signed-off-by: Gabor Juhos <juhosg@openwrt.org> |
#
55ae10f8 |
|
20-Oct-2012 |
Bill Richardson <wfrichar@chromium.org> |
x86: gpio: Add GPIO driver for Intel ICH6 and later. Implement <asm-generic/gpio.h> functions for Intel ICH6 and later. Only GPIOs 0-31 are handled by this code. Signed-off-by: Bill Richardson <wfrichar@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org> |
#
a3a70725 |
|
24-Mar-2012 |
Linus Walleij <linus.walleij@linaro.org> |
pci: declare pciauto functions in header The FSL PCI driver uses local prototypes for pciauto_[pre|post]scan_setup_bridge(), this does not seem right, so move them to the <pci.h> file. Fixed a small extern declaration too, this is harmless but distracts the view since all other prototypes are explicitly external. Signed-off-by: Linus Walleij <linus.walleij@linaro.org> |
#
a1e47b66 |
|
03-Mar-2012 |
Linus Walleij <linus.walleij@linaro.org> |
pci: move pciauto_config_init() to pci.h Fixing build regressions for the Integrator I get find that a few boards try to work around the missing declaration of pciauto_config_init() by declaring it in the local scope. This does not make sense when the sibling functions are in <pci.h> so move the function to the header, ridding the build error in the Integrator and getting rid of the local declarations here and there. Reported-by: Wolfgang Denk <wd@denx.de> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> |
#
b03a466d |
|
01-Feb-2011 |
Prabhakar Kushwaha <prabhakar@freescale.com> |
powerpc/85xx: Handle PCIe initialization requires for P1021 class SoCs The P1011, P1012, P1015, P1016, P1020, P1021, P1024, & P1025 SoCs require that we initialize the SERDES registers if the lanes are configured for PCIe. Additionally these devices PCIe controller do not support ASPM and we have to explicitly disable it. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
10fa8d7c |
|
19-Jan-2011 |
Leo Liu <liucai.lfn@gmail.com> |
mpc83xx: fix pcie configuration space read/write This patch fix a problem for the pcie enumeration when the mpc83xx pcie controller is connected with switch or we use both of the two pcie controller. Signed-off-by: Leo Liu <liucai.lfn@gmail.com> fix codingstyle and compiler warning: 'pcie_priv' defined but not used Signed-off-by: Kim Phillips <kim.phillips@freescale.com> |
#
3a0e3c27 |
|
17-Dec-2010 |
Kumar Gala <galak@kernel.crashing.org> |
powerpc/fsl-pci: Determine pci_controller based on cfg addr for dts fixup Previously we passed in a specifically named struct pci_controller to determine if we had setup the particular PCI bus. Now we can search for the struct so we dont have to depend on the name or the struct being statically allocated. Introduced new find_hose_by_cfg_addr() to get back a pci_controller struct back by searching for it means we can do things like dynamically allocate them or not have to expose the static structures to all users. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Wolfgang Denk <wd@denx.de> |
#
983eb9d1 |
|
29-Oct-2010 |
Peter Tyser <ptyser@xes-inc.com> |
pci: Clean up PCI info when CONFIG_PCI_SCAN_SHOW This change does the following: - Removes the printing of the PCI interrupt line value. This is normally set to 0 by U-Boot on bootup and is rarely used during everyday operation. - Prints out the PCI function number of a device. Previously a device with multiple functions would be printed identically 2 times, which is generally confusing. For example, on an Intel 2 port gigabit Ethernet card the following was displayed: ... 04 01 8086 1010 0200 00 04 01 8086 1010 0200 00 ... - Prints a text description of each device's PCI class instead of the raw PCI class code. The textual description makes it much easier to determine what devices are installed on a PCI bus. - Changes the general formatting of the PCI device output. Previous output: PCIE1: connected as Root Complex 04 01 8086 1010 0200 00 04 01 8086 1010 0200 00 03 00 10b5 8112 0604 00 02 01 10b5 8518 0604 00 02 02 10b5 8518 0604 00 08 00 1957 0040 0b20 00 07 00 10b5 8518 0604 00 09 00 10b5 8112 0604 00 07 01 10b5 8518 0604 00 07 02 10b5 8518 0604 00 06 00 10b5 8518 0604 00 02 03 10b5 8518 0604 00 01 00 10b5 8518 0604 00 PCIE1: Bus 00 - 0b PCIE2: connected as Root Complex 0d 00 1957 0040 0b20 00 PCIE2: Bus 0c - 0d Updated output: PCIE1: connected as Root Complex 04:01.0 - 8086:1010 - Network controller 04:01.1 - 8086:1010 - Network controller 03:00.0 - 10b5:8112 - Bridge device 02:01.0 - 10b5:8518 - Bridge device 02:02.0 - 10b5:8518 - Bridge device 08:00.0 - 1957:0040 - Processor 07:00.0 - 10b5:8518 - Bridge device 09:00.0 - 10b5:8112 - Bridge device 07:01.0 - 10b5:8518 - Bridge device 07:02.0 - 10b5:8518 - Bridge device 06:00.0 - 10b5:8518 - Bridge device 02:03.0 - 10b5:8518 - Bridge device 01:00.0 - 10b5:8518 - Bridge device PCIE1: Bus 00 - 0b PCIE2: connected as Root Complex 0d:00.0 - 1957:0040 - Processor PCIE2: Bus 0c - 0d Signed-off-by: Peter Tyser <ptyser@xes-inc.com> |
#
8295b944 |
|
05-Aug-2009 |
Kumar Gala <galak@kernel.crashing.org> |
pci/fsl_pci_init: Use PCIe capability to determine if controller is PCIe Change the code to use the PCIe capabilities register to determine if we are a PCIe controller or not. Additionally cleaned up some white space and formatting in the file. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
cc2a8c77 |
|
19-Feb-2009 |
Anton Vorontsov <avorontsov@ru.mvista.com> |
PCI: Add pci_last_busno() helper This is just a handy routine that reports last PCI busno: we walk down all the hoses and return last hose's last_busno. Will be used by PCI/PCIe initialization code. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com> |
#
6e61fae4 |
|
03-Feb-2009 |
Becky Bruce <beckyb@kernel.crashing.org> |
drivers/pci: Create pci_map_bar function It is no longer always true that the pci bus address can be used as the virtual address for pci accesses. pci_map_bar() is created to return the virtual address for a pci region. Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org> |
#
ff4e66e9 |
|
06-Feb-2009 |
Kumar Gala <galak@kernel.crashing.org> |
pci: Rename PCI_REGION_MEMORY to PCI_REGION_SYS_MEMORY for clarity The PCI_REGION_MEMORY and PCI_REGION_MEM are a bit to similar and can be confusing when reading the code. Rename PCI_REGION_MEMORY to PCI_REGION_SYS_MEMORY to clarify its used for system memory mapping purposes. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
fd6646c0 |
|
07-Jan-2009 |
Anton Vorontsov <avorontsov@ru.mvista.com> |
mpc83xx: Add support for MPC83xx PCI-E controllers This patch adds support for MPC83xx PCI-E controllers in Root Complex mode. The patch is based on Tony Li and Dave Liu work[1]. Though unlike the original patch, by default we don't register PCI-E buses for use in U-Boot, we only configure the controllers for future use in other OSes (Linux). This is done because we don't have enough of spare BATs to map all the PCI-E regions. To actually use PCI-E in U-Boot, users should explicitly define CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES symbol in the board file. And only then U-Boot will able to access PCI-E, but at the cost of disabled address translation. [1] http://lists.denx.de/pipermail/u-boot/2008-January/027630.html Signed-off-by: Tony Li <tony.li@freescale.com> Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Acked-by: Dave Liu <daveliu@freescale.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com> |
#
30e76d5e |
|
21-Oct-2008 |
Kumar Gala <galak@kernel.crashing.org> |
pci: Allow for PCI addresses to be 64-bit PCI bus is inherently 64-bit. While not all system require access to the full 64-bit PCI address range some do. This allows those systems to enable the full PCI address width via CONFIG_SYS_PCI_64BIT. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Andrew Fleming-AFLEMING <afleming@freescale.com> Acked-by: Wolfgang Denk <wd@denx.de> |
#
36f32675 |
|
07-May-2008 |
Becky Bruce <bgill@freescale.com> |
Update pci code to use phys_addr_t Physical addrs need to be represented by phys_addr_t, not unsigned long. Otherwise, systems that use CONFIG_PHYS_64BIT are going to fail mightily. Signed-off-by: Becky Bruce <becky.bruce@freescale.com> |
#
63cec581 |
|
02-Aug-2007 |
Ed Swarthout <Ed.Swarthout@freescale.com> |
Make MPC8641's PCI/PCI-E driver a common driver for many FSL parts. All of the PCI/PCI-Express driver and initialization code that was in the MPC8641HPCN port has now been moved into the common drivers/fsl_pci_init.c. In a subsequent patch, this will be utilized by the 85xx ports as well. Common PCI-E IMMAP register blocks for FSL 85xx/86xx are added. Also enable the second PCI-Express controller on 8641 by getting its BATS and CFG_ setup right. Fixed a u16 vendor compiler warning in AHCI driver too. Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com> Signed-off-by: Zhang Wei <wei.zhang@freescale.com> Signed-off-by: Jon Loeliger <jdl@freescale.com> |
#
13a7fcdf |
|
19-Oct-2006 |
Jon Loeliger <jdl@freescale.com> |
* Fix a bunch of compiler warnings for gcc 4.0 Signed-off-by: Matthew McClintock <msm@freescale.com> |
#
f0e6f57f |
|
28-Jun-2006 |
Matthew McClintock <msm@freescale.com> |
* Added PCI-X #defines for PCI-X initialization Patch by Andy Fleming on 17-Mar-2006 Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
7b230f61 |
|
12-Mar-2006 |
Wolfgang Denk <wd@pollux.denx.de> |
Merge with git://git.kernel.org/pub/scm/boot/u-boot/u-boot.git#pci
|
#
993a2275 |
|
12-Mar-2006 |
Wolfgang Denk <wd@pollux.denx.de> |
Fix bad declaration on pci_cfgfunc_nothing Patch by Sam Song, 19 Jun 2005 |
#
a179012e |
|
11-Jan-2006 |
Kumar Gala <galak@kernel.crashing.org> |
Added support for PCI prefetchable region and BARs If a host controller sets up a region as prefetchable and a device's BAR denotes it as prefetchable, allocate the BAR into the prefetch region. If a BAR is prefetchable and no prefetchable region has been setup by the controller we fall back to allocating the BAR into the normally memory region. Patch by Kumar Gala 11 Jan 2006 |
#
c157d8e2 |
|
01-Aug-2005 |
Stefan Roese <sr@denx.de> |
Add support for AMCC PPC440EP/GR eval boards Yosemite and Yellowstone. Patch by Steven Blakeslee, 27 Jul 2005 |
#
7a8e9bed |
|
31-May-2003 |
Wolfgang Denk <wdenk> |
* Patch by Marc Singer, 29 May 2003: Fixed rarp boot method for IA32 and other little-endian CPUs. * Patch by Marc Singer, 28 May 2003: Added port I/O commands. * Patch by Matthew McClintock, 28 May 2003 - cpu/mpc824x/start.S: fix relocation code when booting from RAM - minor patches for utx8245 * Patch by Daniel Engstr�m, 28 May 2003: x86 update * Patch by Dave Ellis, 9 May 2003 + 27 May 2003: add nand flash support to SXNI855T configuration fix/extend nand flash support: - fix 'nand erase' command so does not erase bad blocks - fix 'nand write' command so does not write to bad blocks - fix nand_probe() so handles no flash detected properly - add doc/README.nand - add .jffs2 and .oob options to nand read/write - add 'nand bad' command to list bad blocks - add 'clean' option to 'nand erase' to write JFFS2 clean markers - make NAND read/write faster * Patch by Rune Torgersen, 23 May 2003: Update for MPC8266ADS board |
#
c7de829c |
|
19-Nov-2002 |
Wolfgang Denk <wdenk> |
* Patch by Thomas Frieden, 13 Nov 2002: Add code for AmigaOne board (preliminary merge to U-Boot, still WIP) * Patch by Jon Diekema, 12 Nov 2002: - Adding URL for IEEE OUI lookup - Making the autoboot #defines dependent on CONFIG_AUTOBOOT_KEYED being defined. - In the CONFIG_EXTRA_ENV_SETTINGS #define, the root-on-initrd and root-on-nfs macros are designed to switch how the default boot method gets defined. |
#
c609719b |
|
02-Nov-2002 |
Wolfgang Denk <wdenk> |
Initial revision |
#
1d7ad685 |
|
25-Sep-2021 |
Pali Rohár <pali@kernel.org> |
arm: a37xx: pci: Handle propagation of CRSSVE bit from PCIe Root Port Now that PCI Bridge (PCIe Root Port) for Aardvark is emulated in U-Boot, add support for handling and propagation of CRSSVE bit. When CRSSVE bit is unset (default), driver has to reissue config read/write request on CRS response. CRSSVE bit is supported only when CRSVIS bit is provided in read-only Root Capabilities register. So manually inject this CRSVIS bit into read response for that register. Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Stefan Roese <sr@denx.de> |
#
2649f69f |
|
17-Sep-2021 |
Vladimir Oltean <vladimir.oltean@nxp.com> |
pci: provide prototype for pci_skip_dev outside of #if defined(CONFIG_DM_PCI_COMPAT) The weak definition of pci_skip_dev from drivers/pci/pci_common.c is not under CONFIG_DM_PCI_COMPAT, and that definition needs a previous function prototype declaration to avoid W=1 build warnings. That prototype is not available due to it being under CONFIG_DM_PCI_COMPAT, so move it outside of that preprocessor block. Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
23cacd57 |
|
01-Aug-2021 |
Simon Glass <sjg@chromium.org> |
pci: Drop PCI_INDIRECT_BRIDGE This does not work with driver model so can be removed. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
26543cc6 |
|
01-Aug-2021 |
Simon Glass <sjg@chromium.org> |
pci: Drop old code from header file We don't need this code anymore since when PCI is enabled, driver model is always used. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
63814a69 |
|
01-Aug-2021 |
Simon Glass <sjg@chromium.org> |
pci: imx: Drop DM_PCI check from cpu driver We don't need this check anymore since when PCI is enabled, driver model is always used. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
e8c09d69 |
|
01-Aug-2021 |
Simon Glass <sjg@chromium.org> |
pci: Remove guard around compatibility functions This prevents use of IS_ENABLED() in other files. Functions should be visible in headers even if they are not available at link time. Fix it. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
f5cbb5c7 |
|
27-Jun-2021 |
Simon Glass <sjg@chromium.org> |
x86: pci: Allow binding of some devices before relocation At present only bridge devices are bound before relocation, to save space in pre-relocation memory. In some cases we do actually want to bind a device, e.g. because it provides the console UART. Add a devicetree binding to support this. Use the PCI_VENDEV() macro to encode the cell value. This is present in U-Boot but not used, so move it to the binding header-file. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
e58f3a7d |
|
27-Jun-2021 |
Simon Glass <sjg@chromium.org> |
pci: Use const for pci_find_device_id() etc. These functions don't modify the device-ID struct that is passed in, so mark the argument as const, so the data structure can be declared that way. This allows it to be placed in the rodata section. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
c7b36007 |
|
14-May-2021 |
Tom Rini <trini@konsulko.com> |
pci: Remove non-DM board_pci_fixup_dev() declaration With the ventana boards migrated to DM_PCI and DM_ETH, we can remove this prototype. Cc: Stefano Babic <sbabic@denx.de> Signed-off-by: Tom Rini <trini@konsulko.com> |
#
cecd013f |
|
16-Apr-2021 |
Tim Harvey <tharvey@gateworks.com> |
pci: pci-uclass: Add board_pci_fixup_dev for DM_PCI Add a board_pci_fixup_dev weak function to allow PCI device fixups during enumeration. Signed-off-by: Tim Harvey <tharvey@gateworks.com> |
#
8b85dfc6 |
|
16-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: Avoid accessing seq directly At present various drivers etc. access the device's 'seq' member directly. This makes it harder to change the meaning of that member. Change access to go through a function instead. The drivers/i2c/lpc32xx_i2c.c file is left unchanged for now. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
caa4daa2 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename 'platdata' variables to just 'plat' We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
284d062e |
|
09-Sep-2020 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
pci: add a few ARI related defines Add a few defines related to PCI ARI configuration. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
51eeae91 |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add VF BAR map support for Enhanced Allocation Makes dm_pci_map_bar API available to map BAR for Virtual function PCI devices which support Enhanced Allocation. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> |
#
b8852dcf |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add support for Single-Root I/O Virtualization SR-IOV - Single Root I/O Virtualization PF - Physical Function VF - Virtual Function If SR-IOV capability is present, use it to initialize Virtual Function PCI device instances. pci_sriov_init function will read SR-IOV registers to create VF devices under the PF PCI device and also bind driver if available. This function needs to be invoked from Physical function device driver which expects VF device support, creating minimal impact on existing framework. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> |
#
e0024741 |
|
23-Jul-2020 |
Stefan Roese <sr@denx.de> |
pci: pci-uclass: Dynamically allocate the PCI regions Instead of using a fixed length pre-allocated array of regions, this patch moves to dynamically allocating the regions based on the number of available regions plus the necessary regions for DRAM banks. Since MAX_PCI_REGIONS is not needed any more, its removed completely with this patch. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Thierry Reding <treding@nvidia.com> Cc: Marek Vasut <marek.vasut+renesas@gmail.com> |
#
143eb5b1 |
|
12-May-2020 |
Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
drivers: pci: add api to get dma regions Add api to get dma regions. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com> |
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com> |
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com> |
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
7d994067 |
|
23-Apr-2019 |
Tom Rini <trini@konsulko.com> |
Merge tag 'pull-24apr19' of git://git.denx.de/u-boot-dm Various minor sandbox iumprovements Fixes for tracing with sandbox Refactoring for boot_get_fdt()
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
a8c5f8d3 |
|
15-Oct-2018 |
Bin Meng <bmeng.cn@gmail.com> |
dm: pci: Add APIs to find next capability and extended capability This introduces two new APIs dm_pci_find_next_capability() and dm_pci_find_next_ext_capability() to get PCI capability address and PCI express extended capability address for a given PCI device starting from a given offset. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
dac01fd8 |
|
03-Aug-2018 |
Bin Meng <bmeng.cn@gmail.com> |
dm: pci: Add APIs to find capability and extended capability This introduces two new APIs dm_pci_find_capability() and dm_pci_find_ext_capability() to get PCI capability address and PCI express extended capability address for a given PCI device. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
5d544f96 |
|
03-Aug-2018 |
Bin Meng <bmeng.cn@gmail.com> |
pci: Add all known capability and extended capability ids Currently we don't have a complete list of capability and extended capability ids. This adds them. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
4345998a |
|
03-Aug-2018 |
Bin Meng <bmeng.cn@gmail.com> |
pci: sandbox: Support dynamically binding device driver At present all emulated sandbox pci devices must be present in the device tree in order to be used. The real world pci uclass driver supports pci device driver matching, and we should add such support on sandbox too. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
01259c93 |
|
03-Aug-2018 |
Bin Meng <bmeng.cn@gmail.com> |
pci: Remove 440ep-specific macros These macros should not be put in the generic pci.h header file. Since they are not referenced anywhere, remove them completely. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
5ce9aca8 |
|
14-May-2018 |
Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi> |
PCI: Document pciauto_region_allocate() Add a doc comment for pciauto_region_allocate(). Signed-off-by: Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
d71975ae |
|
14-May-2018 |
Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi> |
PCI: autoconfig: Don't allocate 64-bit addresses to 32-bit only resources Currently, if we happen to allocate an address requiring 64 bits to a device only supporting 32-bit BARs, the address eventually gets silently truncated to 32 bits. Avoid this by adding a new flag to pciauto_region_allocate() to bail out in such situations. Signed-off-by: Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
83d290c5 |
|
06-May-2018 |
Tom Rini <trini@konsulko.com> |
SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com> |
#
ed68ccbf |
|
13-Mar-2018 |
Stefan Roese <sr@denx.de> |
pci: Remove unused ppc4xx variable from struct pci_controller ppc4xx support was removed some time ago. Lets remove the now unused "pci_fb" variable from "struct pci_controller" as well. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Simon Glass <sjg@chromium.org> |
#
badb9922 |
|
19-Sep-2017 |
Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi> |
pci: Add helper for implementing memory-mapped config space accesses This sort of pattern for implementing memory-mapped PCI config space accesses appears in U-Boot twice already, and a third user is coming up. So add helper functions to avoid code duplication, similar to how Linux has pci_generic_config_write and pci_generic_config_read. Signed-off-by: Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
6ecbe137 |
|
12-May-2017 |
Tim Harvey <tharvey@gateworks.com> |
drivers: pci: imx: add imx_pcie_remove function There is no dedicated reset signal wired up for the MX6QDL thus if the bootloader enables the link we need some special handling to get the core back into a state where it is safe to touch it for configuration. While there has been some special handling in the Linux kernel to do this, it was removed in 4.11 thus we need to do it properly in the bootloader and therefore without this if you enable PCI in the bootloader you will hang while booting the 4.11 kernel. This puts the PCIe controller back into a safe state for the kernel driver before launching the kernel. Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com> Tested-by: Peter Senna Tschudin <peter.senna@collabora.com> |
#
eeb5b1ad |
|
10-Mar-2016 |
Stuart Yoder <stuart.yoder@nxp.com> |
pci: make pci_get_hose_head() available to external users Put pci_get_hose_head() prototype in header so it is available to external users, allowing them to find and iterate over all pci controllers. Signed-off-by: Stuart Yoder <stuart.yoder@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
4974a6ff |
|
06-Mar-2016 |
Simon Glass <sjg@chromium.org> |
pci: Correct a few comments and nits Two comments are missing a parameter and there is an extra blank line. Also two of the region access macros are misnamed. Correct these problems. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
319dba1f |
|
06-Mar-2016 |
Simon Glass <sjg@chromium.org> |
pci: Add functions to update PCI configuration registers It is common to read a config register value, clear and set some bits, then write back the updated value. Add functions to do this in one step, for convenience. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
308143ef |
|
02-Feb-2016 |
Bin Meng <bmeng.cn@gmail.com> |
dm: pci: Add missing forward declarations When CONFIG_DM_PCI_COMPAT is not on, there is only a forward declaration for pci_write_config32(). Add other missing ones. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
9d731c82 |
|
18-Jan-2016 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to write a BAR Add a driver-model version of the pci_write_bar32 function so that this is supported in the new API. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
7e78b9ef |
|
29-Nov-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Switch to DM API for PCI address mapping We should use the new address mapping functions unless we are in compatibility mode. Disable the old functions by default. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
21d1fe7e |
|
29-Nov-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add driver model API functions for address mapping At present the PCI address map functions use the old API. Add new functions for this so that drivers can be converted. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
bab17cf1 |
|
29-Nov-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR Add a driver-model function for reading the PCI BAR from a device. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
a0eb8356 |
|
29-Nov-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a driver-model version of pci_find_class() Add a function which scans the driver model device information rather than scanning the PCI bus again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> |
#
5c0bf647 |
|
29-Nov-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a driver-model version of pci_find_device() Add a function which scans the driver model device information rather than scanning the PCI bus again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> |
#
5e23b8b4 |
|
29-Nov-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Use driver model PCI API in auto-config At present we are using legacy functions even in the auto-configuration code used by driver model. Add a new pci_auto.c version which uses the correct API. Create a new pci_internal.h header to hold functions that are used within the PCI subsystem, but are not exported to other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> |
#
f3f1faef |
|
29-Nov-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a dm_ prefix to pci_bus_find_bdf() Most driver model PCI functions have a dm_ prefix. At some point, when the old code is converted to driver model and the old functions are removed, we will drop that prefix. For consistency, we should use the dm_ prefix for all driver model functions. Update pci_bus_find_bdf() accordingly. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
21ccce1b |
|
29-Nov-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a dm_ prefix to pci_get_bdf() Most driver model PCI functions have a dm_ prefix. At some point, when the old code is converted to driver model and the old functions are removed, we will drop that prefix. For consistency, we should use the dm_ prefix for all driver model functions. Update pci_get_bdf() accordingly. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
3ba5f74a |
|
26-Nov-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Disable PCI compatibility functions by default We eventually need to drop the compatibility functions for driver model. As a first step, create a configuration option to enable them and hide them when the option is disabled. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
54fe7b1c |
|
26-Nov-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a comment about how to find struct pci_controller With driver mode, struct pci_controller is stored as uclass-private data. Add a comment to that effect. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
f9260336 |
|
19-Nov-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to find the regions for a PCI bus This function looks up the controller and returns a pointer to each region type. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Stephen Warren <swarren@nvidia.com> Tested-by: Stephen Warren <swarren@nvidia.com> |
#
9f60fb0d |
|
19-Nov-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to get the controller for a bus A PCI bus may be a bridge device where the controller is the bridge's parent. Add a function to return the controller device, given a PCI device. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Stephen Warren <swarren@nvidia.com> Tested-by: Stephen Warren <swarren@nvidia.com> |
#
9289db6c |
|
19-Nov-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add functions to emulate 8- and 16-bit access Provide a few functions to support using 32-bit access to emulate 8- and 16-bit access. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Stephen Warren <swarren@nvidia.com> Tested-by: Stephen Warren <swarren@nvidia.com> |
#
bcbe3d15 |
|
28-Sep-2015 |
Simon Glass <sjg@chromium.org> |
dm: Rename dev_get_parentdata() to dev_get_parent_priv() The current name is inconsistent with other driver model data access functions. Rename it and fix up all users. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Joe Hershberger <joe.hershberger@ni.com> |
#
dc5740df |
|
22-Aug-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a comment to help find pci_hose_read_config_byte, etc. These functions are defined by macros so do not show up with grep. Add a comment to help. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
76c3fbcd |
|
10-Aug-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a way to iterate through all PCI devices These functions allow iteration through all PCI devices including bridges. The children of each PCI bus are returned in turn. This can be useful for configuring, checking or enumerating all the devices. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
66afb4ed |
|
10-Aug-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Provide friendly config access functions At present there are no PCI functions which allow access to PCI configuration using a struct udevice. This is a sad situation for driver model as it makes use of PCI harder. Add these functions. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
5f48d798 |
|
27-Jul-2015 |
Simon Glass <sjg@chromium.org> |
pci: Add a constant for an invalid interrupt Rather than using 0xff in the code, add a constant. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
ed5b580b |
|
09-Jul-2015 |
Minghuan Lian <Minghuan.Lian@freescale.com> |
drivers/pci: Add function to find an extended capability PCIe extends device's configuration space to 4k and provides extended capability. The patch adds function to find them. The code is ported from Linux PCIe driver. Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
4b515e4f |
|
06-Jul-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to get the BDF for a device It is useful to be able to find the full PCI address (bus, device and function) for a PCI device. Add a function to provide this. Adjust the existing code to use this. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
aba92962 |
|
06-Jul-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add support for PCI driver matching At present all PCI devices must be present in the device tree in order to be used. Many or most PCI devices don't require any configuration other than that which is done automatically by U-Boot. It is inefficent to add a node with nothing but a compatible string in order to get a device working. Add a mechanism whereby PCI drivers can be declared along with the device parameters they support (vendor/device/class). When no suitable driver is found in the device tree the list of such devices is consulted to determine the correct driver. If this also fails, then a generic driver is used as before. The mechanism used is very similar to that provided by Linux and the header file defintions are copied from Linux 4.1. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Joe Hershberger <joe.hershberger@ni.com> |
#
6c89663c |
|
07-Jul-2015 |
Bin Meng <bmeng.cn@gmail.com> |
pci: Configure expansion ROM during auto config process Currently PCI expansion ROM address is assigned by a call to pciauto_setup_rom() outside of the pci auto config process. This does not work when expansion ROM is on a device behind PCI bridge where bridge's memory limit register was already programmed to a value that does not cover the newly assigned expansion ROM address. To fix this, we should configure the ROM address during the auto config process. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Acked-by: Simon Glass <sjg@chromium.org> |
#
aec241df |
|
07-Jun-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Use the correct hose when configuring devices Only the PCI controller has access to the PCI region information. Make sure to use the controller (rather than any attached bridges) when configuring devices. This corrects a failure to scan and configure devices when driver model is enabled for PCI. Also add a comment to explain the problem. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
36d0d3b4 |
|
05-Mar-2015 |
Simon Glass <sjg@chromium.org> |
dm: sandbox: pci: Add a PCI emulation uclass Since sandbox does not have real devices (unless it borrows those from the host) it must use emulations. Provide a uclass which permits PCI operations to be passed through to an emulation device. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
ff3e077b |
|
05-Mar-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a uclass for PCI Add a uclass for PCI controllers and a generic one for PCI devices. Adjust the 'pci' command and the existing PCI support to work with this new uclass. Keep most of the compatibility code in a separate file so that it can be removed one day. TODO: Add more header file comments to the new parts of pci.h Signed-off-by: Simon Glass <sjg@chromium.org> |
#
aab6724c |
|
05-Mar-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move common PCI functions into their own file Driver model will share many functions with the existing PCI implementation. Move these into their own file to avoid duplication and confusion. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
250e039d |
|
27-Jan-2015 |
Simon Glass <sjg@chromium.org> |
pci: Add a function to find a device by class There is an existing function prototype in the header file but it is not implemented. Implement something similar. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
4a2708a0 |
|
14-Jan-2015 |
Simon Glass <sjg@chromium.org> |
x86: Access the VGA ROM when needed Add code to the generic pci_rom file to access the VGA ROM in PCI space when needed. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
d622ac39 |
|
15-Dec-2014 |
Masahiro Yamada <yamada.m@jp.panasonic.com> |
powerpc: mpc824x: remove MPC824X cpu support All the MPC824X boards are still non-generic boards: A3000, CPC45, CU824, eXalion, MVBLUE, MUSENKI, Sandpoint824x, utx8245 Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Josef Wagner <Wagner@Microsys.de> Cc: Torsten Demke <torsten.demke@fci.com> Cc: Jim Thompson <jim@musenki.com> Cc: Greg Allen <gallen@arlut.utexas.edu> |
#
e8a552eb |
|
14-Nov-2014 |
Simon Glass <sjg@chromium.org> |
pci: Add functions to read and write a BAR address Some PCI functions cannot be auto-configured. Add a function to set up a fixed BAR which can be used in these situations. Also add a function to read the current address of a BAR. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
4efe52bf |
|
12-Nov-2014 |
Thierry Reding <treding@nvidia.com> |
pci: Honour pci_skip_dev() When enumerating devices, honour the pci_skip_dev() function. This can be used by PCI controller drivers to restrict which devices will be probed. This is required by the NVIDIA Tegra PCIe controller driver, which will fail with a data abort exception if an access is attempted to a device number larger than 0 outside of bus 0. pci_skip_dev() is therefore implemented to prevent any such accesses. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Simon Glass <sjg@chromium.org> |
#
0991866c |
|
07-Aug-2014 |
Tim Harvey <tharvey@gateworks.com> |
pci: add support for board_pci_fixup_dev function Some board-level drivers may wish to have per-device fixup functions for PCI devices. Signed-off-by: Tim Harvey <tharvey@gateworks.com> |
#
fa5cec03 |
|
08-Nov-2013 |
Paul Burton <paul.burton@mips.com> |
pci.h: allow inclusion in assembly source This patch simply #ifdef's out the C-specific parts of pci.h when it is included by an assembly file. This will allow the macros it contains to be used from assembly source as will be done in a followup commit adding support for more modern MIPS Malta boards. Signed-off-by: Paul Burton <paul.burton@imgtec.com> |
#
287df01e |
|
11-Oct-2013 |
Zhao Qiang <B45475@freescale.com> |
PCIe:change the method to get the address of a requested capability in configuration space. Previously, the address of a requested capability is define like that "#define PCI_DCR 0x78" But, the addresses of capabilities is different with regard to PCIe revs. So this method is not flexible. Now a function to get the address of a requested capability is added and used. It can get the address dynamically by capability ID. The step of this function: 1. Read Status register in PCIe configuration space to confirm that Capabilities List is valid. 2. Find the address of Capabilities Pointer Register. 3. Find the address of requested capability from the first capability. Signed-off-by: Zhao Qiang <B45475@freescale.com> |
#
7b4e5844 |
|
03-Jul-2013 |
Zang Roy-R61911 <tie-fei.zang@freescale.com> |
powerpc/pcie: add PCIe version 3.x support T4240 PCIe IP is version 3.0 and has some update comparing previous QorIQ products. 1. Move Freescale specific register define to arch/powerpc/include/asm/fsl_pci.h and update the register offset define for T4240. 2. add the status/control register define use status/control register to judge the link status 3. The original code uses 'Programming Interface' field to judge if PCIE is EP or RC mode, however, T4240 does not support this functionality. According to PCIE specification, 'Header Type' offset 0x0e is used to indicate header type, so for PCIE controller, the patch changes code to use 'Header Type' field to identify if the PCIE is RC or EP mode. This patch fixes the PCIe card link up issue on T4240QDS. Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com> |
#
1a459660 |
|
08-Jul-2013 |
Wolfgang Denk <wd@denx.de> |
Add GPL-2.0+ SPDX-License-Identifier to source files Signed-off-by: Wolfgang Denk <wd@denx.de> [trini: Fixup common/cmd_io.c] Signed-off-by: Tom Rini <trini@ti.com> |
#
bc3442aa |
|
11-Jun-2013 |
Simon Glass <sjg@chromium.org> |
pci: Convert extern inline functions to static inline I am not sure of the meaning of extern inline, but this gives errors when building with function instrumenting enabled. Change these functions to static inline. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
842033e6 |
|
30-May-2013 |
Gabor Juhos <juhosg@openwrt.org> |
pci: introduce CONFIG_PCI_INDIRECT_BRIDGE option The pci_indirect.c file is always compiled when CONFIG_PCI is defined although the indirect PCI bridge support is not needed by every board. Introduce a new CONFIG_PCI_INDIRECT_BRIDGE config option and only compile indirect PCI bridge support if this options is enabled. Also add the new option into the configuration files of the boards which needs that. Compile tested for powerpc, x86, arm and nds32. MAKEALL results: powerpc: --------------------- SUMMARY ---------------------------- Boards compiled: 641 Boards with warnings but no errors: 2 ( ELPPC MPC8323ERDB ) ---------------------------------------------------------- Note: the warnings for ELPPC and MPC8323ERDB are present even without the actual patch. x86: --------------------- SUMMARY ---------------------------- Boards compiled: 1 ---------------------------------------------------------- arm: --------------------- SUMMARY ---------------------------- Boards compiled: 311 ---------------------------------------------------------- nds32: --------------------- SUMMARY ---------------------------- Boards compiled: 3 ---------------------------------------------------------- Cc: Tom Rini <trini@ti.com> Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com> Signed-off-by: Gabor Juhos <juhosg@openwrt.org> |
#
55ae10f8 |
|
20-Oct-2012 |
Bill Richardson <wfrichar@chromium.org> |
x86: gpio: Add GPIO driver for Intel ICH6 and later. Implement <asm-generic/gpio.h> functions for Intel ICH6 and later. Only GPIOs 0-31 are handled by this code. Signed-off-by: Bill Richardson <wfrichar@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org> |
#
a3a70725 |
|
24-Mar-2012 |
Linus Walleij <linus.walleij@linaro.org> |
pci: declare pciauto functions in header The FSL PCI driver uses local prototypes for pciauto_[pre|post]scan_setup_bridge(), this does not seem right, so move them to the <pci.h> file. Fixed a small extern declaration too, this is harmless but distracts the view since all other prototypes are explicitly external. Signed-off-by: Linus Walleij <linus.walleij@linaro.org> |
#
a1e47b66 |
|
03-Mar-2012 |
Linus Walleij <linus.walleij@linaro.org> |
pci: move pciauto_config_init() to pci.h Fixing build regressions for the Integrator I get find that a few boards try to work around the missing declaration of pciauto_config_init() by declaring it in the local scope. This does not make sense when the sibling functions are in <pci.h> so move the function to the header, ridding the build error in the Integrator and getting rid of the local declarations here and there. Reported-by: Wolfgang Denk <wd@denx.de> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> |
#
b03a466d |
|
01-Feb-2011 |
Prabhakar Kushwaha <prabhakar@freescale.com> |
powerpc/85xx: Handle PCIe initialization requires for P1021 class SoCs The P1011, P1012, P1015, P1016, P1020, P1021, P1024, & P1025 SoCs require that we initialize the SERDES registers if the lanes are configured for PCIe. Additionally these devices PCIe controller do not support ASPM and we have to explicitly disable it. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
10fa8d7c |
|
19-Jan-2011 |
Leo Liu <liucai.lfn@gmail.com> |
mpc83xx: fix pcie configuration space read/write This patch fix a problem for the pcie enumeration when the mpc83xx pcie controller is connected with switch or we use both of the two pcie controller. Signed-off-by: Leo Liu <liucai.lfn@gmail.com> fix codingstyle and compiler warning: 'pcie_priv' defined but not used Signed-off-by: Kim Phillips <kim.phillips@freescale.com> |
#
3a0e3c27 |
|
17-Dec-2010 |
Kumar Gala <galak@kernel.crashing.org> |
powerpc/fsl-pci: Determine pci_controller based on cfg addr for dts fixup Previously we passed in a specifically named struct pci_controller to determine if we had setup the particular PCI bus. Now we can search for the struct so we dont have to depend on the name or the struct being statically allocated. Introduced new find_hose_by_cfg_addr() to get back a pci_controller struct back by searching for it means we can do things like dynamically allocate them or not have to expose the static structures to all users. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Wolfgang Denk <wd@denx.de> |
#
983eb9d1 |
|
29-Oct-2010 |
Peter Tyser <ptyser@xes-inc.com> |
pci: Clean up PCI info when CONFIG_PCI_SCAN_SHOW This change does the following: - Removes the printing of the PCI interrupt line value. This is normally set to 0 by U-Boot on bootup and is rarely used during everyday operation. - Prints out the PCI function number of a device. Previously a device with multiple functions would be printed identically 2 times, which is generally confusing. For example, on an Intel 2 port gigabit Ethernet card the following was displayed: ... 04 01 8086 1010 0200 00 04 01 8086 1010 0200 00 ... - Prints a text description of each device's PCI class instead of the raw PCI class code. The textual description makes it much easier to determine what devices are installed on a PCI bus. - Changes the general formatting of the PCI device output. Previous output: PCIE1: connected as Root Complex 04 01 8086 1010 0200 00 04 01 8086 1010 0200 00 03 00 10b5 8112 0604 00 02 01 10b5 8518 0604 00 02 02 10b5 8518 0604 00 08 00 1957 0040 0b20 00 07 00 10b5 8518 0604 00 09 00 10b5 8112 0604 00 07 01 10b5 8518 0604 00 07 02 10b5 8518 0604 00 06 00 10b5 8518 0604 00 02 03 10b5 8518 0604 00 01 00 10b5 8518 0604 00 PCIE1: Bus 00 - 0b PCIE2: connected as Root Complex 0d 00 1957 0040 0b20 00 PCIE2: Bus 0c - 0d Updated output: PCIE1: connected as Root Complex 04:01.0 - 8086:1010 - Network controller 04:01.1 - 8086:1010 - Network controller 03:00.0 - 10b5:8112 - Bridge device 02:01.0 - 10b5:8518 - Bridge device 02:02.0 - 10b5:8518 - Bridge device 08:00.0 - 1957:0040 - Processor 07:00.0 - 10b5:8518 - Bridge device 09:00.0 - 10b5:8112 - Bridge device 07:01.0 - 10b5:8518 - Bridge device 07:02.0 - 10b5:8518 - Bridge device 06:00.0 - 10b5:8518 - Bridge device 02:03.0 - 10b5:8518 - Bridge device 01:00.0 - 10b5:8518 - Bridge device PCIE1: Bus 00 - 0b PCIE2: connected as Root Complex 0d:00.0 - 1957:0040 - Processor PCIE2: Bus 0c - 0d Signed-off-by: Peter Tyser <ptyser@xes-inc.com> |
#
8295b944 |
|
05-Aug-2009 |
Kumar Gala <galak@kernel.crashing.org> |
pci/fsl_pci_init: Use PCIe capability to determine if controller is PCIe Change the code to use the PCIe capabilities register to determine if we are a PCIe controller or not. Additionally cleaned up some white space and formatting in the file. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
cc2a8c77 |
|
19-Feb-2009 |
Anton Vorontsov <avorontsov@ru.mvista.com> |
PCI: Add pci_last_busno() helper This is just a handy routine that reports last PCI busno: we walk down all the hoses and return last hose's last_busno. Will be used by PCI/PCIe initialization code. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com> |
#
6e61fae4 |
|
03-Feb-2009 |
Becky Bruce <beckyb@kernel.crashing.org> |
drivers/pci: Create pci_map_bar function It is no longer always true that the pci bus address can be used as the virtual address for pci accesses. pci_map_bar() is created to return the virtual address for a pci region. Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org> |
#
ff4e66e9 |
|
06-Feb-2009 |
Kumar Gala <galak@kernel.crashing.org> |
pci: Rename PCI_REGION_MEMORY to PCI_REGION_SYS_MEMORY for clarity The PCI_REGION_MEMORY and PCI_REGION_MEM are a bit to similar and can be confusing when reading the code. Rename PCI_REGION_MEMORY to PCI_REGION_SYS_MEMORY to clarify its used for system memory mapping purposes. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
fd6646c0 |
|
07-Jan-2009 |
Anton Vorontsov <avorontsov@ru.mvista.com> |
mpc83xx: Add support for MPC83xx PCI-E controllers This patch adds support for MPC83xx PCI-E controllers in Root Complex mode. The patch is based on Tony Li and Dave Liu work[1]. Though unlike the original patch, by default we don't register PCI-E buses for use in U-Boot, we only configure the controllers for future use in other OSes (Linux). This is done because we don't have enough of spare BATs to map all the PCI-E regions. To actually use PCI-E in U-Boot, users should explicitly define CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES symbol in the board file. And only then U-Boot will able to access PCI-E, but at the cost of disabled address translation. [1] http://lists.denx.de/pipermail/u-boot/2008-January/027630.html Signed-off-by: Tony Li <tony.li@freescale.com> Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Acked-by: Dave Liu <daveliu@freescale.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com> |
#
30e76d5e |
|
21-Oct-2008 |
Kumar Gala <galak@kernel.crashing.org> |
pci: Allow for PCI addresses to be 64-bit PCI bus is inherently 64-bit. While not all system require access to the full 64-bit PCI address range some do. This allows those systems to enable the full PCI address width via CONFIG_SYS_PCI_64BIT. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Andrew Fleming-AFLEMING <afleming@freescale.com> Acked-by: Wolfgang Denk <wd@denx.de> |
#
36f32675 |
|
07-May-2008 |
Becky Bruce <bgill@freescale.com> |
Update pci code to use phys_addr_t Physical addrs need to be represented by phys_addr_t, not unsigned long. Otherwise, systems that use CONFIG_PHYS_64BIT are going to fail mightily. Signed-off-by: Becky Bruce <becky.bruce@freescale.com> |
#
63cec581 |
|
02-Aug-2007 |
Ed Swarthout <Ed.Swarthout@freescale.com> |
Make MPC8641's PCI/PCI-E driver a common driver for many FSL parts. All of the PCI/PCI-Express driver and initialization code that was in the MPC8641HPCN port has now been moved into the common drivers/fsl_pci_init.c. In a subsequent patch, this will be utilized by the 85xx ports as well. Common PCI-E IMMAP register blocks for FSL 85xx/86xx are added. Also enable the second PCI-Express controller on 8641 by getting its BATS and CFG_ setup right. Fixed a u16 vendor compiler warning in AHCI driver too. Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com> Signed-off-by: Zhang Wei <wei.zhang@freescale.com> Signed-off-by: Jon Loeliger <jdl@freescale.com> |
#
13a7fcdf |
|
19-Oct-2006 |
Jon Loeliger <jdl@freescale.com> |
* Fix a bunch of compiler warnings for gcc 4.0 Signed-off-by: Matthew McClintock <msm@freescale.com> |
#
f0e6f57f |
|
28-Jun-2006 |
Matthew McClintock <msm@freescale.com> |
* Added PCI-X #defines for PCI-X initialization Patch by Andy Fleming on 17-Mar-2006 Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
7b230f61 |
|
12-Mar-2006 |
Wolfgang Denk <wd@pollux.denx.de> |
Merge with git://git.kernel.org/pub/scm/boot/u-boot/u-boot.git#pci
|
#
993a2275 |
|
12-Mar-2006 |
Wolfgang Denk <wd@pollux.denx.de> |
Fix bad declaration on pci_cfgfunc_nothing Patch by Sam Song, 19 Jun 2005 |
#
a179012e |
|
11-Jan-2006 |
Kumar Gala <galak@kernel.crashing.org> |
Added support for PCI prefetchable region and BARs If a host controller sets up a region as prefetchable and a device's BAR denotes it as prefetchable, allocate the BAR into the prefetch region. If a BAR is prefetchable and no prefetchable region has been setup by the controller we fall back to allocating the BAR into the normally memory region. Patch by Kumar Gala 11 Jan 2006 |
#
c157d8e2 |
|
01-Aug-2005 |
Stefan Roese <sr@denx.de> |
Add support for AMCC PPC440EP/GR eval boards Yosemite and Yellowstone. Patch by Steven Blakeslee, 27 Jul 2005 |
#
7a8e9bed |
|
31-May-2003 |
Wolfgang Denk <wdenk> |
* Patch by Marc Singer, 29 May 2003: Fixed rarp boot method for IA32 and other little-endian CPUs. * Patch by Marc Singer, 28 May 2003: Added port I/O commands. * Patch by Matthew McClintock, 28 May 2003 - cpu/mpc824x/start.S: fix relocation code when booting from RAM - minor patches for utx8245 * Patch by Daniel Engstr�m, 28 May 2003: x86 update * Patch by Dave Ellis, 9 May 2003 + 27 May 2003: add nand flash support to SXNI855T configuration fix/extend nand flash support: - fix 'nand erase' command so does not erase bad blocks - fix 'nand write' command so does not write to bad blocks - fix nand_probe() so handles no flash detected properly - add doc/README.nand - add .jffs2 and .oob options to nand read/write - add 'nand bad' command to list bad blocks - add 'clean' option to 'nand erase' to write JFFS2 clean markers - make NAND read/write faster * Patch by Rune Torgersen, 23 May 2003: Update for MPC8266ADS board |
#
c7de829c |
|
19-Nov-2002 |
Wolfgang Denk <wdenk> |
* Patch by Thomas Frieden, 13 Nov 2002: Add code for AmigaOne board (preliminary merge to U-Boot, still WIP) * Patch by Jon Diekema, 12 Nov 2002: - Adding URL for IEEE OUI lookup - Making the autoboot #defines dependent on CONFIG_AUTOBOOT_KEYED being defined. - In the CONFIG_EXTRA_ENV_SETTINGS #define, the root-on-initrd and root-on-nfs macros are designed to switch how the default boot method gets defined. |
#
c609719b |
|
02-Nov-2002 |
Wolfgang Denk <wdenk> |
Initial revision |
#
23cacd57 |
|
01-Aug-2021 |
Simon Glass <sjg@chromium.org> |
pci: Drop PCI_INDIRECT_BRIDGE This does not work with driver model so can be removed. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
26543cc6 |
|
01-Aug-2021 |
Simon Glass <sjg@chromium.org> |
pci: Drop old code from header file We don't need this code anymore since when PCI is enabled, driver model is always used. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
63814a69 |
|
01-Aug-2021 |
Simon Glass <sjg@chromium.org> |
pci: imx: Drop DM_PCI check from cpu driver We don't need this check anymore since when PCI is enabled, driver model is always used. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
e8c09d69 |
|
01-Aug-2021 |
Simon Glass <sjg@chromium.org> |
pci: Remove guard around compatibility functions This prevents use of IS_ENABLED() in other files. Functions should be visible in headers even if they are not available at link time. Fix it. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
f5cbb5c7 |
|
27-Jun-2021 |
Simon Glass <sjg@chromium.org> |
x86: pci: Allow binding of some devices before relocation At present only bridge devices are bound before relocation, to save space in pre-relocation memory. In some cases we do actually want to bind a device, e.g. because it provides the console UART. Add a devicetree binding to support this. Use the PCI_VENDEV() macro to encode the cell value. This is present in U-Boot but not used, so move it to the binding header-file. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
e58f3a7d |
|
27-Jun-2021 |
Simon Glass <sjg@chromium.org> |
pci: Use const for pci_find_device_id() etc. These functions don't modify the device-ID struct that is passed in, so mark the argument as const, so the data structure can be declared that way. This allows it to be placed in the rodata section. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
c7b36007 |
|
14-May-2021 |
Tom Rini <trini@konsulko.com> |
pci: Remove non-DM board_pci_fixup_dev() declaration With the ventana boards migrated to DM_PCI and DM_ETH, we can remove this prototype. Cc: Stefano Babic <sbabic@denx.de> Signed-off-by: Tom Rini <trini@konsulko.com> |
#
cecd013f |
|
16-Apr-2021 |
Tim Harvey <tharvey@gateworks.com> |
pci: pci-uclass: Add board_pci_fixup_dev for DM_PCI Add a board_pci_fixup_dev weak function to allow PCI device fixups during enumeration. Signed-off-by: Tim Harvey <tharvey@gateworks.com> |
#
8b85dfc6 |
|
16-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: Avoid accessing seq directly At present various drivers etc. access the device's 'seq' member directly. This makes it harder to change the meaning of that member. Change access to go through a function instead. The drivers/i2c/lpc32xx_i2c.c file is left unchanged for now. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
caa4daa2 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename 'platdata' variables to just 'plat' We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
284d062e |
|
09-Sep-2020 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
pci: add a few ARI related defines Add a few defines related to PCI ARI configuration. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
51eeae91 |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add VF BAR map support for Enhanced Allocation Makes dm_pci_map_bar API available to map BAR for Virtual function PCI devices which support Enhanced Allocation. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> |
#
b8852dcf |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add support for Single-Root I/O Virtualization SR-IOV - Single Root I/O Virtualization PF - Physical Function VF - Virtual Function If SR-IOV capability is present, use it to initialize Virtual Function PCI device instances. pci_sriov_init function will read SR-IOV registers to create VF devices under the PF PCI device and also bind driver if available. This function needs to be invoked from Physical function device driver which expects VF device support, creating minimal impact on existing framework. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> |
#
e0024741 |
|
23-Jul-2020 |
Stefan Roese <sr@denx.de> |
pci: pci-uclass: Dynamically allocate the PCI regions Instead of using a fixed length pre-allocated array of regions, this patch moves to dynamically allocating the regions based on the number of available regions plus the necessary regions for DRAM banks. Since MAX_PCI_REGIONS is not needed any more, its removed completely with this patch. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Thierry Reding <treding@nvidia.com> Cc: Marek Vasut <marek.vasut+renesas@gmail.com> |
#
143eb5b1 |
|
12-May-2020 |
Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
drivers: pci: add api to get dma regions Add api to get dma regions. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com> |
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com> |
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com> |
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
7d994067 |
|
23-Apr-2019 |
Tom Rini <trini@konsulko.com> |
Merge tag 'pull-24apr19' of git://git.denx.de/u-boot-dm Various minor sandbox iumprovements Fixes for tracing with sandbox Refactoring for boot_get_fdt()
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
a8c5f8d3 |
|
15-Oct-2018 |
Bin Meng <bmeng.cn@gmail.com> |
dm: pci: Add APIs to find next capability and extended capability This introduces two new APIs dm_pci_find_next_capability() and dm_pci_find_next_ext_capability() to get PCI capability address and PCI express extended capability address for a given PCI device starting from a given offset. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
dac01fd8 |
|
03-Aug-2018 |
Bin Meng <bmeng.cn@gmail.com> |
dm: pci: Add APIs to find capability and extended capability This introduces two new APIs dm_pci_find_capability() and dm_pci_find_ext_capability() to get PCI capability address and PCI express extended capability address for a given PCI device. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
5d544f96 |
|
03-Aug-2018 |
Bin Meng <bmeng.cn@gmail.com> |
pci: Add all known capability and extended capability ids Currently we don't have a complete list of capability and extended capability ids. This adds them. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
4345998a |
|
03-Aug-2018 |
Bin Meng <bmeng.cn@gmail.com> |
pci: sandbox: Support dynamically binding device driver At present all emulated sandbox pci devices must be present in the device tree in order to be used. The real world pci uclass driver supports pci device driver matching, and we should add such support on sandbox too. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
01259c93 |
|
03-Aug-2018 |
Bin Meng <bmeng.cn@gmail.com> |
pci: Remove 440ep-specific macros These macros should not be put in the generic pci.h header file. Since they are not referenced anywhere, remove them completely. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
5ce9aca8 |
|
14-May-2018 |
Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi> |
PCI: Document pciauto_region_allocate() Add a doc comment for pciauto_region_allocate(). Signed-off-by: Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
d71975ae |
|
14-May-2018 |
Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi> |
PCI: autoconfig: Don't allocate 64-bit addresses to 32-bit only resources Currently, if we happen to allocate an address requiring 64 bits to a device only supporting 32-bit BARs, the address eventually gets silently truncated to 32 bits. Avoid this by adding a new flag to pciauto_region_allocate() to bail out in such situations. Signed-off-by: Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
83d290c5 |
|
06-May-2018 |
Tom Rini <trini@konsulko.com> |
SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com> |
#
ed68ccbf |
|
13-Mar-2018 |
Stefan Roese <sr@denx.de> |
pci: Remove unused ppc4xx variable from struct pci_controller ppc4xx support was removed some time ago. Lets remove the now unused "pci_fb" variable from "struct pci_controller" as well. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Simon Glass <sjg@chromium.org> |
#
badb9922 |
|
19-Sep-2017 |
Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi> |
pci: Add helper for implementing memory-mapped config space accesses This sort of pattern for implementing memory-mapped PCI config space accesses appears in U-Boot twice already, and a third user is coming up. So add helper functions to avoid code duplication, similar to how Linux has pci_generic_config_write and pci_generic_config_read. Signed-off-by: Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
6ecbe137 |
|
12-May-2017 |
Tim Harvey <tharvey@gateworks.com> |
drivers: pci: imx: add imx_pcie_remove function There is no dedicated reset signal wired up for the MX6QDL thus if the bootloader enables the link we need some special handling to get the core back into a state where it is safe to touch it for configuration. While there has been some special handling in the Linux kernel to do this, it was removed in 4.11 thus we need to do it properly in the bootloader and therefore without this if you enable PCI in the bootloader you will hang while booting the 4.11 kernel. This puts the PCIe controller back into a safe state for the kernel driver before launching the kernel. Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com> Tested-by: Peter Senna Tschudin <peter.senna@collabora.com> |
#
eeb5b1ad |
|
10-Mar-2016 |
Stuart Yoder <stuart.yoder@nxp.com> |
pci: make pci_get_hose_head() available to external users Put pci_get_hose_head() prototype in header so it is available to external users, allowing them to find and iterate over all pci controllers. Signed-off-by: Stuart Yoder <stuart.yoder@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
4974a6ff |
|
06-Mar-2016 |
Simon Glass <sjg@chromium.org> |
pci: Correct a few comments and nits Two comments are missing a parameter and there is an extra blank line. Also two of the region access macros are misnamed. Correct these problems. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
319dba1f |
|
06-Mar-2016 |
Simon Glass <sjg@chromium.org> |
pci: Add functions to update PCI configuration registers It is common to read a config register value, clear and set some bits, then write back the updated value. Add functions to do this in one step, for convenience. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
308143ef |
|
02-Feb-2016 |
Bin Meng <bmeng.cn@gmail.com> |
dm: pci: Add missing forward declarations When CONFIG_DM_PCI_COMPAT is not on, there is only a forward declaration for pci_write_config32(). Add other missing ones. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
9d731c82 |
|
18-Jan-2016 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to write a BAR Add a driver-model version of the pci_write_bar32 function so that this is supported in the new API. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
7e78b9ef |
|
29-Nov-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Switch to DM API for PCI address mapping We should use the new address mapping functions unless we are in compatibility mode. Disable the old functions by default. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
21d1fe7e |
|
29-Nov-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add driver model API functions for address mapping At present the PCI address map functions use the old API. Add new functions for this so that drivers can be converted. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
bab17cf1 |
|
29-Nov-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR Add a driver-model function for reading the PCI BAR from a device. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
a0eb8356 |
|
29-Nov-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a driver-model version of pci_find_class() Add a function which scans the driver model device information rather than scanning the PCI bus again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> |
#
5c0bf647 |
|
29-Nov-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a driver-model version of pci_find_device() Add a function which scans the driver model device information rather than scanning the PCI bus again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> |
#
5e23b8b4 |
|
29-Nov-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Use driver model PCI API in auto-config At present we are using legacy functions even in the auto-configuration code used by driver model. Add a new pci_auto.c version which uses the correct API. Create a new pci_internal.h header to hold functions that are used within the PCI subsystem, but are not exported to other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> |
#
f3f1faef |
|
29-Nov-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a dm_ prefix to pci_bus_find_bdf() Most driver model PCI functions have a dm_ prefix. At some point, when the old code is converted to driver model and the old functions are removed, we will drop that prefix. For consistency, we should use the dm_ prefix for all driver model functions. Update pci_bus_find_bdf() accordingly. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
21ccce1b |
|
29-Nov-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a dm_ prefix to pci_get_bdf() Most driver model PCI functions have a dm_ prefix. At some point, when the old code is converted to driver model and the old functions are removed, we will drop that prefix. For consistency, we should use the dm_ prefix for all driver model functions. Update pci_get_bdf() accordingly. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
3ba5f74a |
|
26-Nov-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Disable PCI compatibility functions by default We eventually need to drop the compatibility functions for driver model. As a first step, create a configuration option to enable them and hide them when the option is disabled. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
54fe7b1c |
|
26-Nov-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a comment about how to find struct pci_controller With driver mode, struct pci_controller is stored as uclass-private data. Add a comment to that effect. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
f9260336 |
|
19-Nov-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to find the regions for a PCI bus This function looks up the controller and returns a pointer to each region type. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Stephen Warren <swarren@nvidia.com> Tested-by: Stephen Warren <swarren@nvidia.com> |
#
9f60fb0d |
|
19-Nov-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to get the controller for a bus A PCI bus may be a bridge device where the controller is the bridge's parent. Add a function to return the controller device, given a PCI device. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Stephen Warren <swarren@nvidia.com> Tested-by: Stephen Warren <swarren@nvidia.com> |
#
9289db6c |
|
19-Nov-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add functions to emulate 8- and 16-bit access Provide a few functions to support using 32-bit access to emulate 8- and 16-bit access. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Stephen Warren <swarren@nvidia.com> Tested-by: Stephen Warren <swarren@nvidia.com> |
#
bcbe3d15 |
|
28-Sep-2015 |
Simon Glass <sjg@chromium.org> |
dm: Rename dev_get_parentdata() to dev_get_parent_priv() The current name is inconsistent with other driver model data access functions. Rename it and fix up all users. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Joe Hershberger <joe.hershberger@ni.com> |
#
dc5740df |
|
22-Aug-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a comment to help find pci_hose_read_config_byte, etc. These functions are defined by macros so do not show up with grep. Add a comment to help. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
76c3fbcd |
|
10-Aug-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a way to iterate through all PCI devices These functions allow iteration through all PCI devices including bridges. The children of each PCI bus are returned in turn. This can be useful for configuring, checking or enumerating all the devices. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
66afb4ed |
|
10-Aug-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Provide friendly config access functions At present there are no PCI functions which allow access to PCI configuration using a struct udevice. This is a sad situation for driver model as it makes use of PCI harder. Add these functions. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
5f48d798 |
|
27-Jul-2015 |
Simon Glass <sjg@chromium.org> |
pci: Add a constant for an invalid interrupt Rather than using 0xff in the code, add a constant. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
ed5b580b |
|
09-Jul-2015 |
Minghuan Lian <Minghuan.Lian@freescale.com> |
drivers/pci: Add function to find an extended capability PCIe extends device's configuration space to 4k and provides extended capability. The patch adds function to find them. The code is ported from Linux PCIe driver. Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
4b515e4f |
|
06-Jul-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to get the BDF for a device It is useful to be able to find the full PCI address (bus, device and function) for a PCI device. Add a function to provide this. Adjust the existing code to use this. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
aba92962 |
|
06-Jul-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add support for PCI driver matching At present all PCI devices must be present in the device tree in order to be used. Many or most PCI devices don't require any configuration other than that which is done automatically by U-Boot. It is inefficent to add a node with nothing but a compatible string in order to get a device working. Add a mechanism whereby PCI drivers can be declared along with the device parameters they support (vendor/device/class). When no suitable driver is found in the device tree the list of such devices is consulted to determine the correct driver. If this also fails, then a generic driver is used as before. The mechanism used is very similar to that provided by Linux and the header file defintions are copied from Linux 4.1. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Joe Hershberger <joe.hershberger@ni.com> |
#
6c89663c |
|
07-Jul-2015 |
Bin Meng <bmeng.cn@gmail.com> |
pci: Configure expansion ROM during auto config process Currently PCI expansion ROM address is assigned by a call to pciauto_setup_rom() outside of the pci auto config process. This does not work when expansion ROM is on a device behind PCI bridge where bridge's memory limit register was already programmed to a value that does not cover the newly assigned expansion ROM address. To fix this, we should configure the ROM address during the auto config process. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Acked-by: Simon Glass <sjg@chromium.org> |
#
aec241df |
|
07-Jun-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Use the correct hose when configuring devices Only the PCI controller has access to the PCI region information. Make sure to use the controller (rather than any attached bridges) when configuring devices. This corrects a failure to scan and configure devices when driver model is enabled for PCI. Also add a comment to explain the problem. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
36d0d3b4 |
|
05-Mar-2015 |
Simon Glass <sjg@chromium.org> |
dm: sandbox: pci: Add a PCI emulation uclass Since sandbox does not have real devices (unless it borrows those from the host) it must use emulations. Provide a uclass which permits PCI operations to be passed through to an emulation device. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
ff3e077b |
|
05-Mar-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a uclass for PCI Add a uclass for PCI controllers and a generic one for PCI devices. Adjust the 'pci' command and the existing PCI support to work with this new uclass. Keep most of the compatibility code in a separate file so that it can be removed one day. TODO: Add more header file comments to the new parts of pci.h Signed-off-by: Simon Glass <sjg@chromium.org> |
#
aab6724c |
|
05-Mar-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move common PCI functions into their own file Driver model will share many functions with the existing PCI implementation. Move these into their own file to avoid duplication and confusion. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
250e039d |
|
27-Jan-2015 |
Simon Glass <sjg@chromium.org> |
pci: Add a function to find a device by class There is an existing function prototype in the header file but it is not implemented. Implement something similar. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
4a2708a0 |
|
14-Jan-2015 |
Simon Glass <sjg@chromium.org> |
x86: Access the VGA ROM when needed Add code to the generic pci_rom file to access the VGA ROM in PCI space when needed. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
d622ac39 |
|
15-Dec-2014 |
Masahiro Yamada <yamada.m@jp.panasonic.com> |
powerpc: mpc824x: remove MPC824X cpu support All the MPC824X boards are still non-generic boards: A3000, CPC45, CU824, eXalion, MVBLUE, MUSENKI, Sandpoint824x, utx8245 Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Josef Wagner <Wagner@Microsys.de> Cc: Torsten Demke <torsten.demke@fci.com> Cc: Jim Thompson <jim@musenki.com> Cc: Greg Allen <gallen@arlut.utexas.edu> |
#
e8a552eb |
|
14-Nov-2014 |
Simon Glass <sjg@chromium.org> |
pci: Add functions to read and write a BAR address Some PCI functions cannot be auto-configured. Add a function to set up a fixed BAR which can be used in these situations. Also add a function to read the current address of a BAR. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
4efe52bf |
|
12-Nov-2014 |
Thierry Reding <treding@nvidia.com> |
pci: Honour pci_skip_dev() When enumerating devices, honour the pci_skip_dev() function. This can be used by PCI controller drivers to restrict which devices will be probed. This is required by the NVIDIA Tegra PCIe controller driver, which will fail with a data abort exception if an access is attempted to a device number larger than 0 outside of bus 0. pci_skip_dev() is therefore implemented to prevent any such accesses. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Simon Glass <sjg@chromium.org> |
#
0991866c |
|
07-Aug-2014 |
Tim Harvey <tharvey@gateworks.com> |
pci: add support for board_pci_fixup_dev function Some board-level drivers may wish to have per-device fixup functions for PCI devices. Signed-off-by: Tim Harvey <tharvey@gateworks.com> |
#
fa5cec03 |
|
08-Nov-2013 |
Paul Burton <paul.burton@mips.com> |
pci.h: allow inclusion in assembly source This patch simply #ifdef's out the C-specific parts of pci.h when it is included by an assembly file. This will allow the macros it contains to be used from assembly source as will be done in a followup commit adding support for more modern MIPS Malta boards. Signed-off-by: Paul Burton <paul.burton@imgtec.com> |
#
287df01e |
|
11-Oct-2013 |
Zhao Qiang <B45475@freescale.com> |
PCIe:change the method to get the address of a requested capability in configuration space. Previously, the address of a requested capability is define like that "#define PCI_DCR 0x78" But, the addresses of capabilities is different with regard to PCIe revs. So this method is not flexible. Now a function to get the address of a requested capability is added and used. It can get the address dynamically by capability ID. The step of this function: 1. Read Status register in PCIe configuration space to confirm that Capabilities List is valid. 2. Find the address of Capabilities Pointer Register. 3. Find the address of requested capability from the first capability. Signed-off-by: Zhao Qiang <B45475@freescale.com> |
#
7b4e5844 |
|
03-Jul-2013 |
Zang Roy-R61911 <tie-fei.zang@freescale.com> |
powerpc/pcie: add PCIe version 3.x support T4240 PCIe IP is version 3.0 and has some update comparing previous QorIQ products. 1. Move Freescale specific register define to arch/powerpc/include/asm/fsl_pci.h and update the register offset define for T4240. 2. add the status/control register define use status/control register to judge the link status 3. The original code uses 'Programming Interface' field to judge if PCIE is EP or RC mode, however, T4240 does not support this functionality. According to PCIE specification, 'Header Type' offset 0x0e is used to indicate header type, so for PCIE controller, the patch changes code to use 'Header Type' field to identify if the PCIE is RC or EP mode. This patch fixes the PCIe card link up issue on T4240QDS. Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com> |
#
1a459660 |
|
08-Jul-2013 |
Wolfgang Denk <wd@denx.de> |
Add GPL-2.0+ SPDX-License-Identifier to source files Signed-off-by: Wolfgang Denk <wd@denx.de> [trini: Fixup common/cmd_io.c] Signed-off-by: Tom Rini <trini@ti.com> |
#
bc3442aa |
|
11-Jun-2013 |
Simon Glass <sjg@chromium.org> |
pci: Convert extern inline functions to static inline I am not sure of the meaning of extern inline, but this gives errors when building with function instrumenting enabled. Change these functions to static inline. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
842033e6 |
|
30-May-2013 |
Gabor Juhos <juhosg@openwrt.org> |
pci: introduce CONFIG_PCI_INDIRECT_BRIDGE option The pci_indirect.c file is always compiled when CONFIG_PCI is defined although the indirect PCI bridge support is not needed by every board. Introduce a new CONFIG_PCI_INDIRECT_BRIDGE config option and only compile indirect PCI bridge support if this options is enabled. Also add the new option into the configuration files of the boards which needs that. Compile tested for powerpc, x86, arm and nds32. MAKEALL results: powerpc: --------------------- SUMMARY ---------------------------- Boards compiled: 641 Boards with warnings but no errors: 2 ( ELPPC MPC8323ERDB ) ---------------------------------------------------------- Note: the warnings for ELPPC and MPC8323ERDB are present even without the actual patch. x86: --------------------- SUMMARY ---------------------------- Boards compiled: 1 ---------------------------------------------------------- arm: --------------------- SUMMARY ---------------------------- Boards compiled: 311 ---------------------------------------------------------- nds32: --------------------- SUMMARY ---------------------------- Boards compiled: 3 ---------------------------------------------------------- Cc: Tom Rini <trini@ti.com> Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com> Signed-off-by: Gabor Juhos <juhosg@openwrt.org> |
#
55ae10f8 |
|
20-Oct-2012 |
Bill Richardson <wfrichar@chromium.org> |
x86: gpio: Add GPIO driver for Intel ICH6 and later. Implement <asm-generic/gpio.h> functions for Intel ICH6 and later. Only GPIOs 0-31 are handled by this code. Signed-off-by: Bill Richardson <wfrichar@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org> |
#
a3a70725 |
|
24-Mar-2012 |
Linus Walleij <linus.walleij@linaro.org> |
pci: declare pciauto functions in header The FSL PCI driver uses local prototypes for pciauto_[pre|post]scan_setup_bridge(), this does not seem right, so move them to the <pci.h> file. Fixed a small extern declaration too, this is harmless but distracts the view since all other prototypes are explicitly external. Signed-off-by: Linus Walleij <linus.walleij@linaro.org> |
#
a1e47b66 |
|
03-Mar-2012 |
Linus Walleij <linus.walleij@linaro.org> |
pci: move pciauto_config_init() to pci.h Fixing build regressions for the Integrator I get find that a few boards try to work around the missing declaration of pciauto_config_init() by declaring it in the local scope. This does not make sense when the sibling functions are in <pci.h> so move the function to the header, ridding the build error in the Integrator and getting rid of the local declarations here and there. Reported-by: Wolfgang Denk <wd@denx.de> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> |
#
b03a466d |
|
01-Feb-2011 |
Prabhakar Kushwaha <prabhakar@freescale.com> |
powerpc/85xx: Handle PCIe initialization requires for P1021 class SoCs The P1011, P1012, P1015, P1016, P1020, P1021, P1024, & P1025 SoCs require that we initialize the SERDES registers if the lanes are configured for PCIe. Additionally these devices PCIe controller do not support ASPM and we have to explicitly disable it. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
10fa8d7c |
|
19-Jan-2011 |
Leo Liu <liucai.lfn@gmail.com> |
mpc83xx: fix pcie configuration space read/write This patch fix a problem for the pcie enumeration when the mpc83xx pcie controller is connected with switch or we use both of the two pcie controller. Signed-off-by: Leo Liu <liucai.lfn@gmail.com> fix codingstyle and compiler warning: 'pcie_priv' defined but not used Signed-off-by: Kim Phillips <kim.phillips@freescale.com> |
#
3a0e3c27 |
|
17-Dec-2010 |
Kumar Gala <galak@kernel.crashing.org> |
powerpc/fsl-pci: Determine pci_controller based on cfg addr for dts fixup Previously we passed in a specifically named struct pci_controller to determine if we had setup the particular PCI bus. Now we can search for the struct so we dont have to depend on the name or the struct being statically allocated. Introduced new find_hose_by_cfg_addr() to get back a pci_controller struct back by searching for it means we can do things like dynamically allocate them or not have to expose the static structures to all users. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Wolfgang Denk <wd@denx.de> |
#
983eb9d1 |
|
29-Oct-2010 |
Peter Tyser <ptyser@xes-inc.com> |
pci: Clean up PCI info when CONFIG_PCI_SCAN_SHOW This change does the following: - Removes the printing of the PCI interrupt line value. This is normally set to 0 by U-Boot on bootup and is rarely used during everyday operation. - Prints out the PCI function number of a device. Previously a device with multiple functions would be printed identically 2 times, which is generally confusing. For example, on an Intel 2 port gigabit Ethernet card the following was displayed: ... 04 01 8086 1010 0200 00 04 01 8086 1010 0200 00 ... - Prints a text description of each device's PCI class instead of the raw PCI class code. The textual description makes it much easier to determine what devices are installed on a PCI bus. - Changes the general formatting of the PCI device output. Previous output: PCIE1: connected as Root Complex 04 01 8086 1010 0200 00 04 01 8086 1010 0200 00 03 00 10b5 8112 0604 00 02 01 10b5 8518 0604 00 02 02 10b5 8518 0604 00 08 00 1957 0040 0b20 00 07 00 10b5 8518 0604 00 09 00 10b5 8112 0604 00 07 01 10b5 8518 0604 00 07 02 10b5 8518 0604 00 06 00 10b5 8518 0604 00 02 03 10b5 8518 0604 00 01 00 10b5 8518 0604 00 PCIE1: Bus 00 - 0b PCIE2: connected as Root Complex 0d 00 1957 0040 0b20 00 PCIE2: Bus 0c - 0d Updated output: PCIE1: connected as Root Complex 04:01.0 - 8086:1010 - Network controller 04:01.1 - 8086:1010 - Network controller 03:00.0 - 10b5:8112 - Bridge device 02:01.0 - 10b5:8518 - Bridge device 02:02.0 - 10b5:8518 - Bridge device 08:00.0 - 1957:0040 - Processor 07:00.0 - 10b5:8518 - Bridge device 09:00.0 - 10b5:8112 - Bridge device 07:01.0 - 10b5:8518 - Bridge device 07:02.0 - 10b5:8518 - Bridge device 06:00.0 - 10b5:8518 - Bridge device 02:03.0 - 10b5:8518 - Bridge device 01:00.0 - 10b5:8518 - Bridge device PCIE1: Bus 00 - 0b PCIE2: connected as Root Complex 0d:00.0 - 1957:0040 - Processor PCIE2: Bus 0c - 0d Signed-off-by: Peter Tyser <ptyser@xes-inc.com> |
#
8295b944 |
|
05-Aug-2009 |
Kumar Gala <galak@kernel.crashing.org> |
pci/fsl_pci_init: Use PCIe capability to determine if controller is PCIe Change the code to use the PCIe capabilities register to determine if we are a PCIe controller or not. Additionally cleaned up some white space and formatting in the file. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
cc2a8c77 |
|
19-Feb-2009 |
Anton Vorontsov <avorontsov@ru.mvista.com> |
PCI: Add pci_last_busno() helper This is just a handy routine that reports last PCI busno: we walk down all the hoses and return last hose's last_busno. Will be used by PCI/PCIe initialization code. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com> |
#
6e61fae4 |
|
03-Feb-2009 |
Becky Bruce <beckyb@kernel.crashing.org> |
drivers/pci: Create pci_map_bar function It is no longer always true that the pci bus address can be used as the virtual address for pci accesses. pci_map_bar() is created to return the virtual address for a pci region. Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org> |
#
ff4e66e9 |
|
06-Feb-2009 |
Kumar Gala <galak@kernel.crashing.org> |
pci: Rename PCI_REGION_MEMORY to PCI_REGION_SYS_MEMORY for clarity The PCI_REGION_MEMORY and PCI_REGION_MEM are a bit to similar and can be confusing when reading the code. Rename PCI_REGION_MEMORY to PCI_REGION_SYS_MEMORY to clarify its used for system memory mapping purposes. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
fd6646c0 |
|
07-Jan-2009 |
Anton Vorontsov <avorontsov@ru.mvista.com> |
mpc83xx: Add support for MPC83xx PCI-E controllers This patch adds support for MPC83xx PCI-E controllers in Root Complex mode. The patch is based on Tony Li and Dave Liu work[1]. Though unlike the original patch, by default we don't register PCI-E buses for use in U-Boot, we only configure the controllers for future use in other OSes (Linux). This is done because we don't have enough of spare BATs to map all the PCI-E regions. To actually use PCI-E in U-Boot, users should explicitly define CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES symbol in the board file. And only then U-Boot will able to access PCI-E, but at the cost of disabled address translation. [1] http://lists.denx.de/pipermail/u-boot/2008-January/027630.html Signed-off-by: Tony Li <tony.li@freescale.com> Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Acked-by: Dave Liu <daveliu@freescale.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com> |
#
30e76d5e |
|
21-Oct-2008 |
Kumar Gala <galak@kernel.crashing.org> |
pci: Allow for PCI addresses to be 64-bit PCI bus is inherently 64-bit. While not all system require access to the full 64-bit PCI address range some do. This allows those systems to enable the full PCI address width via CONFIG_SYS_PCI_64BIT. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Andrew Fleming-AFLEMING <afleming@freescale.com> Acked-by: Wolfgang Denk <wd@denx.de> |
#
36f32675 |
|
07-May-2008 |
Becky Bruce <bgill@freescale.com> |
Update pci code to use phys_addr_t Physical addrs need to be represented by phys_addr_t, not unsigned long. Otherwise, systems that use CONFIG_PHYS_64BIT are going to fail mightily. Signed-off-by: Becky Bruce <becky.bruce@freescale.com> |
#
63cec581 |
|
02-Aug-2007 |
Ed Swarthout <Ed.Swarthout@freescale.com> |
Make MPC8641's PCI/PCI-E driver a common driver for many FSL parts. All of the PCI/PCI-Express driver and initialization code that was in the MPC8641HPCN port has now been moved into the common drivers/fsl_pci_init.c. In a subsequent patch, this will be utilized by the 85xx ports as well. Common PCI-E IMMAP register blocks for FSL 85xx/86xx are added. Also enable the second PCI-Express controller on 8641 by getting its BATS and CFG_ setup right. Fixed a u16 vendor compiler warning in AHCI driver too. Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com> Signed-off-by: Zhang Wei <wei.zhang@freescale.com> Signed-off-by: Jon Loeliger <jdl@freescale.com> |
#
13a7fcdf |
|
19-Oct-2006 |
Jon Loeliger <jdl@freescale.com> |
* Fix a bunch of compiler warnings for gcc 4.0 Signed-off-by: Matthew McClintock <msm@freescale.com> |
#
f0e6f57f |
|
28-Jun-2006 |
Matthew McClintock <msm@freescale.com> |
* Added PCI-X #defines for PCI-X initialization Patch by Andy Fleming on 17-Mar-2006 Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
7b230f61 |
|
12-Mar-2006 |
Wolfgang Denk <wd@pollux.denx.de> |
Merge with git://git.kernel.org/pub/scm/boot/u-boot/u-boot.git#pci
|
#
993a2275 |
|
12-Mar-2006 |
Wolfgang Denk <wd@pollux.denx.de> |
Fix bad declaration on pci_cfgfunc_nothing Patch by Sam Song, 19 Jun 2005 |
#
a179012e |
|
11-Jan-2006 |
Kumar Gala <galak@kernel.crashing.org> |
Added support for PCI prefetchable region and BARs If a host controller sets up a region as prefetchable and a device's BAR denotes it as prefetchable, allocate the BAR into the prefetch region. If a BAR is prefetchable and no prefetchable region has been setup by the controller we fall back to allocating the BAR into the normally memory region. Patch by Kumar Gala 11 Jan 2006 |
#
c157d8e2 |
|
01-Aug-2005 |
Stefan Roese <sr@denx.de> |
Add support for AMCC PPC440EP/GR eval boards Yosemite and Yellowstone. Patch by Steven Blakeslee, 27 Jul 2005 |
#
7a8e9bed |
|
31-May-2003 |
Wolfgang Denk <wdenk> |
* Patch by Marc Singer, 29 May 2003: Fixed rarp boot method for IA32 and other little-endian CPUs. * Patch by Marc Singer, 28 May 2003: Added port I/O commands. * Patch by Matthew McClintock, 28 May 2003 - cpu/mpc824x/start.S: fix relocation code when booting from RAM - minor patches for utx8245 * Patch by Daniel Engstr�m, 28 May 2003: x86 update * Patch by Dave Ellis, 9 May 2003 + 27 May 2003: add nand flash support to SXNI855T configuration fix/extend nand flash support: - fix 'nand erase' command so does not erase bad blocks - fix 'nand write' command so does not write to bad blocks - fix nand_probe() so handles no flash detected properly - add doc/README.nand - add .jffs2 and .oob options to nand read/write - add 'nand bad' command to list bad blocks - add 'clean' option to 'nand erase' to write JFFS2 clean markers - make NAND read/write faster * Patch by Rune Torgersen, 23 May 2003: Update for MPC8266ADS board |
#
c7de829c |
|
19-Nov-2002 |
Wolfgang Denk <wdenk> |
* Patch by Thomas Frieden, 13 Nov 2002: Add code for AmigaOne board (preliminary merge to U-Boot, still WIP) * Patch by Jon Diekema, 12 Nov 2002: - Adding URL for IEEE OUI lookup - Making the autoboot #defines dependent on CONFIG_AUTOBOOT_KEYED being defined. - In the CONFIG_EXTRA_ENV_SETTINGS #define, the root-on-initrd and root-on-nfs macros are designed to switch how the default boot method gets defined. |
#
c609719b |
|
02-Nov-2002 |
Wolfgang Denk <wdenk> |
Initial revision |
#
63814a69 |
|
01-Aug-2021 |
Simon Glass <sjg@chromium.org> |
pci: imx: Drop DM_PCI check from cpu driver We don't need this check anymore since when PCI is enabled, driver model is always used. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
e8c09d69 |
|
01-Aug-2021 |
Simon Glass <sjg@chromium.org> |
pci: Remove guard around compatibility functions This prevents use of IS_ENABLED() in other files. Functions should be visible in headers even if they are not available at link time. Fix it. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
f5cbb5c7 |
|
27-Jun-2021 |
Simon Glass <sjg@chromium.org> |
x86: pci: Allow binding of some devices before relocation At present only bridge devices are bound before relocation, to save space in pre-relocation memory. In some cases we do actually want to bind a device, e.g. because it provides the console UART. Add a devicetree binding to support this. Use the PCI_VENDEV() macro to encode the cell value. This is present in U-Boot but not used, so move it to the binding header-file. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
e58f3a7d |
|
27-Jun-2021 |
Simon Glass <sjg@chromium.org> |
pci: Use const for pci_find_device_id() etc. These functions don't modify the device-ID struct that is passed in, so mark the argument as const, so the data structure can be declared that way. This allows it to be placed in the rodata section. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
c7b36007 |
|
14-May-2021 |
Tom Rini <trini@konsulko.com> |
pci: Remove non-DM board_pci_fixup_dev() declaration With the ventana boards migrated to DM_PCI and DM_ETH, we can remove this prototype. Cc: Stefano Babic <sbabic@denx.de> Signed-off-by: Tom Rini <trini@konsulko.com> |
#
cecd013f |
|
16-Apr-2021 |
Tim Harvey <tharvey@gateworks.com> |
pci: pci-uclass: Add board_pci_fixup_dev for DM_PCI Add a board_pci_fixup_dev weak function to allow PCI device fixups during enumeration. Signed-off-by: Tim Harvey <tharvey@gateworks.com> |
#
8b85dfc6 |
|
16-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: Avoid accessing seq directly At present various drivers etc. access the device's 'seq' member directly. This makes it harder to change the meaning of that member. Change access to go through a function instead. The drivers/i2c/lpc32xx_i2c.c file is left unchanged for now. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
caa4daa2 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename 'platdata' variables to just 'plat' We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
284d062e |
|
09-Sep-2020 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
pci: add a few ARI related defines Add a few defines related to PCI ARI configuration. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
51eeae91 |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add VF BAR map support for Enhanced Allocation Makes dm_pci_map_bar API available to map BAR for Virtual function PCI devices which support Enhanced Allocation. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> |
#
b8852dcf |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add support for Single-Root I/O Virtualization SR-IOV - Single Root I/O Virtualization PF - Physical Function VF - Virtual Function If SR-IOV capability is present, use it to initialize Virtual Function PCI device instances. pci_sriov_init function will read SR-IOV registers to create VF devices under the PF PCI device and also bind driver if available. This function needs to be invoked from Physical function device driver which expects VF device support, creating minimal impact on existing framework. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> |
#
e0024741 |
|
23-Jul-2020 |
Stefan Roese <sr@denx.de> |
pci: pci-uclass: Dynamically allocate the PCI regions Instead of using a fixed length pre-allocated array of regions, this patch moves to dynamically allocating the regions based on the number of available regions plus the necessary regions for DRAM banks. Since MAX_PCI_REGIONS is not needed any more, its removed completely with this patch. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Thierry Reding <treding@nvidia.com> Cc: Marek Vasut <marek.vasut+renesas@gmail.com> |
#
143eb5b1 |
|
12-May-2020 |
Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
drivers: pci: add api to get dma regions Add api to get dma regions. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com> |
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com> |
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com> |
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
7d994067 |
|
23-Apr-2019 |
Tom Rini <trini@konsulko.com> |
Merge tag 'pull-24apr19' of git://git.denx.de/u-boot-dm Various minor sandbox iumprovements Fixes for tracing with sandbox Refactoring for boot_get_fdt()
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
a8c5f8d3 |
|
15-Oct-2018 |
Bin Meng <bmeng.cn@gmail.com> |
dm: pci: Add APIs to find next capability and extended capability This introduces two new APIs dm_pci_find_next_capability() and dm_pci_find_next_ext_capability() to get PCI capability address and PCI express extended capability address for a given PCI device starting from a given offset. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
dac01fd8 |
|
03-Aug-2018 |
Bin Meng <bmeng.cn@gmail.com> |
dm: pci: Add APIs to find capability and extended capability This introduces two new APIs dm_pci_find_capability() and dm_pci_find_ext_capability() to get PCI capability address and PCI express extended capability address for a given PCI device. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
5d544f96 |
|
03-Aug-2018 |
Bin Meng <bmeng.cn@gmail.com> |
pci: Add all known capability and extended capability ids Currently we don't have a complete list of capability and extended capability ids. This adds them. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
4345998a |
|
03-Aug-2018 |
Bin Meng <bmeng.cn@gmail.com> |
pci: sandbox: Support dynamically binding device driver At present all emulated sandbox pci devices must be present in the device tree in order to be used. The real world pci uclass driver supports pci device driver matching, and we should add such support on sandbox too. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
01259c93 |
|
03-Aug-2018 |
Bin Meng <bmeng.cn@gmail.com> |
pci: Remove 440ep-specific macros These macros should not be put in the generic pci.h header file. Since they are not referenced anywhere, remove them completely. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
5ce9aca8 |
|
14-May-2018 |
Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi> |
PCI: Document pciauto_region_allocate() Add a doc comment for pciauto_region_allocate(). Signed-off-by: Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
d71975ae |
|
14-May-2018 |
Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi> |
PCI: autoconfig: Don't allocate 64-bit addresses to 32-bit only resources Currently, if we happen to allocate an address requiring 64 bits to a device only supporting 32-bit BARs, the address eventually gets silently truncated to 32 bits. Avoid this by adding a new flag to pciauto_region_allocate() to bail out in such situations. Signed-off-by: Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
83d290c5 |
|
06-May-2018 |
Tom Rini <trini@konsulko.com> |
SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com> |
#
ed68ccbf |
|
13-Mar-2018 |
Stefan Roese <sr@denx.de> |
pci: Remove unused ppc4xx variable from struct pci_controller ppc4xx support was removed some time ago. Lets remove the now unused "pci_fb" variable from "struct pci_controller" as well. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Simon Glass <sjg@chromium.org> |
#
badb9922 |
|
19-Sep-2017 |
Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi> |
pci: Add helper for implementing memory-mapped config space accesses This sort of pattern for implementing memory-mapped PCI config space accesses appears in U-Boot twice already, and a third user is coming up. So add helper functions to avoid code duplication, similar to how Linux has pci_generic_config_write and pci_generic_config_read. Signed-off-by: Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
6ecbe137 |
|
12-May-2017 |
Tim Harvey <tharvey@gateworks.com> |
drivers: pci: imx: add imx_pcie_remove function There is no dedicated reset signal wired up for the MX6QDL thus if the bootloader enables the link we need some special handling to get the core back into a state where it is safe to touch it for configuration. While there has been some special handling in the Linux kernel to do this, it was removed in 4.11 thus we need to do it properly in the bootloader and therefore without this if you enable PCI in the bootloader you will hang while booting the 4.11 kernel. This puts the PCIe controller back into a safe state for the kernel driver before launching the kernel. Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com> Tested-by: Peter Senna Tschudin <peter.senna@collabora.com> |
#
eeb5b1ad |
|
10-Mar-2016 |
Stuart Yoder <stuart.yoder@nxp.com> |
pci: make pci_get_hose_head() available to external users Put pci_get_hose_head() prototype in header so it is available to external users, allowing them to find and iterate over all pci controllers. Signed-off-by: Stuart Yoder <stuart.yoder@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
4974a6ff |
|
06-Mar-2016 |
Simon Glass <sjg@chromium.org> |
pci: Correct a few comments and nits Two comments are missing a parameter and there is an extra blank line. Also two of the region access macros are misnamed. Correct these problems. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
319dba1f |
|
06-Mar-2016 |
Simon Glass <sjg@chromium.org> |
pci: Add functions to update PCI configuration registers It is common to read a config register value, clear and set some bits, then write back the updated value. Add functions to do this in one step, for convenience. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
308143ef |
|
02-Feb-2016 |
Bin Meng <bmeng.cn@gmail.com> |
dm: pci: Add missing forward declarations When CONFIG_DM_PCI_COMPAT is not on, there is only a forward declaration for pci_write_config32(). Add other missing ones. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
9d731c82 |
|
18-Jan-2016 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to write a BAR Add a driver-model version of the pci_write_bar32 function so that this is supported in the new API. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
7e78b9ef |
|
29-Nov-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Switch to DM API for PCI address mapping We should use the new address mapping functions unless we are in compatibility mode. Disable the old functions by default. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
21d1fe7e |
|
29-Nov-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add driver model API functions for address mapping At present the PCI address map functions use the old API. Add new functions for this so that drivers can be converted. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
bab17cf1 |
|
29-Nov-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR Add a driver-model function for reading the PCI BAR from a device. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
a0eb8356 |
|
29-Nov-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a driver-model version of pci_find_class() Add a function which scans the driver model device information rather than scanning the PCI bus again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> |
#
5c0bf647 |
|
29-Nov-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a driver-model version of pci_find_device() Add a function which scans the driver model device information rather than scanning the PCI bus again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> |
#
5e23b8b4 |
|
29-Nov-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Use driver model PCI API in auto-config At present we are using legacy functions even in the auto-configuration code used by driver model. Add a new pci_auto.c version which uses the correct API. Create a new pci_internal.h header to hold functions that are used within the PCI subsystem, but are not exported to other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> |
#
f3f1faef |
|
29-Nov-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a dm_ prefix to pci_bus_find_bdf() Most driver model PCI functions have a dm_ prefix. At some point, when the old code is converted to driver model and the old functions are removed, we will drop that prefix. For consistency, we should use the dm_ prefix for all driver model functions. Update pci_bus_find_bdf() accordingly. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
21ccce1b |
|
29-Nov-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a dm_ prefix to pci_get_bdf() Most driver model PCI functions have a dm_ prefix. At some point, when the old code is converted to driver model and the old functions are removed, we will drop that prefix. For consistency, we should use the dm_ prefix for all driver model functions. Update pci_get_bdf() accordingly. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
3ba5f74a |
|
26-Nov-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Disable PCI compatibility functions by default We eventually need to drop the compatibility functions for driver model. As a first step, create a configuration option to enable them and hide them when the option is disabled. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
54fe7b1c |
|
26-Nov-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a comment about how to find struct pci_controller With driver mode, struct pci_controller is stored as uclass-private data. Add a comment to that effect. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
f9260336 |
|
19-Nov-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to find the regions for a PCI bus This function looks up the controller and returns a pointer to each region type. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Stephen Warren <swarren@nvidia.com> Tested-by: Stephen Warren <swarren@nvidia.com> |
#
9f60fb0d |
|
19-Nov-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to get the controller for a bus A PCI bus may be a bridge device where the controller is the bridge's parent. Add a function to return the controller device, given a PCI device. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Stephen Warren <swarren@nvidia.com> Tested-by: Stephen Warren <swarren@nvidia.com> |
#
9289db6c |
|
19-Nov-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add functions to emulate 8- and 16-bit access Provide a few functions to support using 32-bit access to emulate 8- and 16-bit access. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Stephen Warren <swarren@nvidia.com> Tested-by: Stephen Warren <swarren@nvidia.com> |
#
bcbe3d15 |
|
28-Sep-2015 |
Simon Glass <sjg@chromium.org> |
dm: Rename dev_get_parentdata() to dev_get_parent_priv() The current name is inconsistent with other driver model data access functions. Rename it and fix up all users. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Joe Hershberger <joe.hershberger@ni.com> |
#
dc5740df |
|
22-Aug-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a comment to help find pci_hose_read_config_byte, etc. These functions are defined by macros so do not show up with grep. Add a comment to help. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
76c3fbcd |
|
10-Aug-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a way to iterate through all PCI devices These functions allow iteration through all PCI devices including bridges. The children of each PCI bus are returned in turn. This can be useful for configuring, checking or enumerating all the devices. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
66afb4ed |
|
10-Aug-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Provide friendly config access functions At present there are no PCI functions which allow access to PCI configuration using a struct udevice. This is a sad situation for driver model as it makes use of PCI harder. Add these functions. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
5f48d798 |
|
27-Jul-2015 |
Simon Glass <sjg@chromium.org> |
pci: Add a constant for an invalid interrupt Rather than using 0xff in the code, add a constant. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
ed5b580b |
|
09-Jul-2015 |
Minghuan Lian <Minghuan.Lian@freescale.com> |
drivers/pci: Add function to find an extended capability PCIe extends device's configuration space to 4k and provides extended capability. The patch adds function to find them. The code is ported from Linux PCIe driver. Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
4b515e4f |
|
06-Jul-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to get the BDF for a device It is useful to be able to find the full PCI address (bus, device and function) for a PCI device. Add a function to provide this. Adjust the existing code to use this. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
aba92962 |
|
06-Jul-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add support for PCI driver matching At present all PCI devices must be present in the device tree in order to be used. Many or most PCI devices don't require any configuration other than that which is done automatically by U-Boot. It is inefficent to add a node with nothing but a compatible string in order to get a device working. Add a mechanism whereby PCI drivers can be declared along with the device parameters they support (vendor/device/class). When no suitable driver is found in the device tree the list of such devices is consulted to determine the correct driver. If this also fails, then a generic driver is used as before. The mechanism used is very similar to that provided by Linux and the header file defintions are copied from Linux 4.1. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Joe Hershberger <joe.hershberger@ni.com> |
#
6c89663c |
|
07-Jul-2015 |
Bin Meng <bmeng.cn@gmail.com> |
pci: Configure expansion ROM during auto config process Currently PCI expansion ROM address is assigned by a call to pciauto_setup_rom() outside of the pci auto config process. This does not work when expansion ROM is on a device behind PCI bridge where bridge's memory limit register was already programmed to a value that does not cover the newly assigned expansion ROM address. To fix this, we should configure the ROM address during the auto config process. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Acked-by: Simon Glass <sjg@chromium.org> |
#
aec241df |
|
07-Jun-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Use the correct hose when configuring devices Only the PCI controller has access to the PCI region information. Make sure to use the controller (rather than any attached bridges) when configuring devices. This corrects a failure to scan and configure devices when driver model is enabled for PCI. Also add a comment to explain the problem. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
36d0d3b4 |
|
05-Mar-2015 |
Simon Glass <sjg@chromium.org> |
dm: sandbox: pci: Add a PCI emulation uclass Since sandbox does not have real devices (unless it borrows those from the host) it must use emulations. Provide a uclass which permits PCI operations to be passed through to an emulation device. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
ff3e077b |
|
05-Mar-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a uclass for PCI Add a uclass for PCI controllers and a generic one for PCI devices. Adjust the 'pci' command and the existing PCI support to work with this new uclass. Keep most of the compatibility code in a separate file so that it can be removed one day. TODO: Add more header file comments to the new parts of pci.h Signed-off-by: Simon Glass <sjg@chromium.org> |
#
aab6724c |
|
05-Mar-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move common PCI functions into their own file Driver model will share many functions with the existing PCI implementation. Move these into their own file to avoid duplication and confusion. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
250e039d |
|
27-Jan-2015 |
Simon Glass <sjg@chromium.org> |
pci: Add a function to find a device by class There is an existing function prototype in the header file but it is not implemented. Implement something similar. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
4a2708a0 |
|
14-Jan-2015 |
Simon Glass <sjg@chromium.org> |
x86: Access the VGA ROM when needed Add code to the generic pci_rom file to access the VGA ROM in PCI space when needed. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
d622ac39 |
|
15-Dec-2014 |
Masahiro Yamada <yamada.m@jp.panasonic.com> |
powerpc: mpc824x: remove MPC824X cpu support All the MPC824X boards are still non-generic boards: A3000, CPC45, CU824, eXalion, MVBLUE, MUSENKI, Sandpoint824x, utx8245 Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Josef Wagner <Wagner@Microsys.de> Cc: Torsten Demke <torsten.demke@fci.com> Cc: Jim Thompson <jim@musenki.com> Cc: Greg Allen <gallen@arlut.utexas.edu> |
#
e8a552eb |
|
14-Nov-2014 |
Simon Glass <sjg@chromium.org> |
pci: Add functions to read and write a BAR address Some PCI functions cannot be auto-configured. Add a function to set up a fixed BAR which can be used in these situations. Also add a function to read the current address of a BAR. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
4efe52bf |
|
12-Nov-2014 |
Thierry Reding <treding@nvidia.com> |
pci: Honour pci_skip_dev() When enumerating devices, honour the pci_skip_dev() function. This can be used by PCI controller drivers to restrict which devices will be probed. This is required by the NVIDIA Tegra PCIe controller driver, which will fail with a data abort exception if an access is attempted to a device number larger than 0 outside of bus 0. pci_skip_dev() is therefore implemented to prevent any such accesses. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Simon Glass <sjg@chromium.org> |
#
0991866c |
|
07-Aug-2014 |
Tim Harvey <tharvey@gateworks.com> |
pci: add support for board_pci_fixup_dev function Some board-level drivers may wish to have per-device fixup functions for PCI devices. Signed-off-by: Tim Harvey <tharvey@gateworks.com> |
#
fa5cec03 |
|
08-Nov-2013 |
Paul Burton <paul.burton@mips.com> |
pci.h: allow inclusion in assembly source This patch simply #ifdef's out the C-specific parts of pci.h when it is included by an assembly file. This will allow the macros it contains to be used from assembly source as will be done in a followup commit adding support for more modern MIPS Malta boards. Signed-off-by: Paul Burton <paul.burton@imgtec.com> |
#
287df01e |
|
11-Oct-2013 |
Zhao Qiang <B45475@freescale.com> |
PCIe:change the method to get the address of a requested capability in configuration space. Previously, the address of a requested capability is define like that "#define PCI_DCR 0x78" But, the addresses of capabilities is different with regard to PCIe revs. So this method is not flexible. Now a function to get the address of a requested capability is added and used. It can get the address dynamically by capability ID. The step of this function: 1. Read Status register in PCIe configuration space to confirm that Capabilities List is valid. 2. Find the address of Capabilities Pointer Register. 3. Find the address of requested capability from the first capability. Signed-off-by: Zhao Qiang <B45475@freescale.com> |
#
7b4e5844 |
|
03-Jul-2013 |
Zang Roy-R61911 <tie-fei.zang@freescale.com> |
powerpc/pcie: add PCIe version 3.x support T4240 PCIe IP is version 3.0 and has some update comparing previous QorIQ products. 1. Move Freescale specific register define to arch/powerpc/include/asm/fsl_pci.h and update the register offset define for T4240. 2. add the status/control register define use status/control register to judge the link status 3. The original code uses 'Programming Interface' field to judge if PCIE is EP or RC mode, however, T4240 does not support this functionality. According to PCIE specification, 'Header Type' offset 0x0e is used to indicate header type, so for PCIE controller, the patch changes code to use 'Header Type' field to identify if the PCIE is RC or EP mode. This patch fixes the PCIe card link up issue on T4240QDS. Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com> |
#
1a459660 |
|
08-Jul-2013 |
Wolfgang Denk <wd@denx.de> |
Add GPL-2.0+ SPDX-License-Identifier to source files Signed-off-by: Wolfgang Denk <wd@denx.de> [trini: Fixup common/cmd_io.c] Signed-off-by: Tom Rini <trini@ti.com> |
#
bc3442aa |
|
11-Jun-2013 |
Simon Glass <sjg@chromium.org> |
pci: Convert extern inline functions to static inline I am not sure of the meaning of extern inline, but this gives errors when building with function instrumenting enabled. Change these functions to static inline. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
842033e6 |
|
30-May-2013 |
Gabor Juhos <juhosg@openwrt.org> |
pci: introduce CONFIG_PCI_INDIRECT_BRIDGE option The pci_indirect.c file is always compiled when CONFIG_PCI is defined although the indirect PCI bridge support is not needed by every board. Introduce a new CONFIG_PCI_INDIRECT_BRIDGE config option and only compile indirect PCI bridge support if this options is enabled. Also add the new option into the configuration files of the boards which needs that. Compile tested for powerpc, x86, arm and nds32. MAKEALL results: powerpc: --------------------- SUMMARY ---------------------------- Boards compiled: 641 Boards with warnings but no errors: 2 ( ELPPC MPC8323ERDB ) ---------------------------------------------------------- Note: the warnings for ELPPC and MPC8323ERDB are present even without the actual patch. x86: --------------------- SUMMARY ---------------------------- Boards compiled: 1 ---------------------------------------------------------- arm: --------------------- SUMMARY ---------------------------- Boards compiled: 311 ---------------------------------------------------------- nds32: --------------------- SUMMARY ---------------------------- Boards compiled: 3 ---------------------------------------------------------- Cc: Tom Rini <trini@ti.com> Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com> Signed-off-by: Gabor Juhos <juhosg@openwrt.org> |
#
55ae10f8 |
|
20-Oct-2012 |
Bill Richardson <wfrichar@chromium.org> |
x86: gpio: Add GPIO driver for Intel ICH6 and later. Implement <asm-generic/gpio.h> functions for Intel ICH6 and later. Only GPIOs 0-31 are handled by this code. Signed-off-by: Bill Richardson <wfrichar@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org> |
#
a3a70725 |
|
24-Mar-2012 |
Linus Walleij <linus.walleij@linaro.org> |
pci: declare pciauto functions in header The FSL PCI driver uses local prototypes for pciauto_[pre|post]scan_setup_bridge(), this does not seem right, so move them to the <pci.h> file. Fixed a small extern declaration too, this is harmless but distracts the view since all other prototypes are explicitly external. Signed-off-by: Linus Walleij <linus.walleij@linaro.org> |
#
a1e47b66 |
|
03-Mar-2012 |
Linus Walleij <linus.walleij@linaro.org> |
pci: move pciauto_config_init() to pci.h Fixing build regressions for the Integrator I get find that a few boards try to work around the missing declaration of pciauto_config_init() by declaring it in the local scope. This does not make sense when the sibling functions are in <pci.h> so move the function to the header, ridding the build error in the Integrator and getting rid of the local declarations here and there. Reported-by: Wolfgang Denk <wd@denx.de> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> |
#
b03a466d |
|
01-Feb-2011 |
Prabhakar Kushwaha <prabhakar@freescale.com> |
powerpc/85xx: Handle PCIe initialization requires for P1021 class SoCs The P1011, P1012, P1015, P1016, P1020, P1021, P1024, & P1025 SoCs require that we initialize the SERDES registers if the lanes are configured for PCIe. Additionally these devices PCIe controller do not support ASPM and we have to explicitly disable it. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
10fa8d7c |
|
19-Jan-2011 |
Leo Liu <liucai.lfn@gmail.com> |
mpc83xx: fix pcie configuration space read/write This patch fix a problem for the pcie enumeration when the mpc83xx pcie controller is connected with switch or we use both of the two pcie controller. Signed-off-by: Leo Liu <liucai.lfn@gmail.com> fix codingstyle and compiler warning: 'pcie_priv' defined but not used Signed-off-by: Kim Phillips <kim.phillips@freescale.com> |
#
3a0e3c27 |
|
17-Dec-2010 |
Kumar Gala <galak@kernel.crashing.org> |
powerpc/fsl-pci: Determine pci_controller based on cfg addr for dts fixup Previously we passed in a specifically named struct pci_controller to determine if we had setup the particular PCI bus. Now we can search for the struct so we dont have to depend on the name or the struct being statically allocated. Introduced new find_hose_by_cfg_addr() to get back a pci_controller struct back by searching for it means we can do things like dynamically allocate them or not have to expose the static structures to all users. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Wolfgang Denk <wd@denx.de> |
#
983eb9d1 |
|
29-Oct-2010 |
Peter Tyser <ptyser@xes-inc.com> |
pci: Clean up PCI info when CONFIG_PCI_SCAN_SHOW This change does the following: - Removes the printing of the PCI interrupt line value. This is normally set to 0 by U-Boot on bootup and is rarely used during everyday operation. - Prints out the PCI function number of a device. Previously a device with multiple functions would be printed identically 2 times, which is generally confusing. For example, on an Intel 2 port gigabit Ethernet card the following was displayed: ... 04 01 8086 1010 0200 00 04 01 8086 1010 0200 00 ... - Prints a text description of each device's PCI class instead of the raw PCI class code. The textual description makes it much easier to determine what devices are installed on a PCI bus. - Changes the general formatting of the PCI device output. Previous output: PCIE1: connected as Root Complex 04 01 8086 1010 0200 00 04 01 8086 1010 0200 00 03 00 10b5 8112 0604 00 02 01 10b5 8518 0604 00 02 02 10b5 8518 0604 00 08 00 1957 0040 0b20 00 07 00 10b5 8518 0604 00 09 00 10b5 8112 0604 00 07 01 10b5 8518 0604 00 07 02 10b5 8518 0604 00 06 00 10b5 8518 0604 00 02 03 10b5 8518 0604 00 01 00 10b5 8518 0604 00 PCIE1: Bus 00 - 0b PCIE2: connected as Root Complex 0d 00 1957 0040 0b20 00 PCIE2: Bus 0c - 0d Updated output: PCIE1: connected as Root Complex 04:01.0 - 8086:1010 - Network controller 04:01.1 - 8086:1010 - Network controller 03:00.0 - 10b5:8112 - Bridge device 02:01.0 - 10b5:8518 - Bridge device 02:02.0 - 10b5:8518 - Bridge device 08:00.0 - 1957:0040 - Processor 07:00.0 - 10b5:8518 - Bridge device 09:00.0 - 10b5:8112 - Bridge device 07:01.0 - 10b5:8518 - Bridge device 07:02.0 - 10b5:8518 - Bridge device 06:00.0 - 10b5:8518 - Bridge device 02:03.0 - 10b5:8518 - Bridge device 01:00.0 - 10b5:8518 - Bridge device PCIE1: Bus 00 - 0b PCIE2: connected as Root Complex 0d:00.0 - 1957:0040 - Processor PCIE2: Bus 0c - 0d Signed-off-by: Peter Tyser <ptyser@xes-inc.com> |
#
8295b944 |
|
05-Aug-2009 |
Kumar Gala <galak@kernel.crashing.org> |
pci/fsl_pci_init: Use PCIe capability to determine if controller is PCIe Change the code to use the PCIe capabilities register to determine if we are a PCIe controller or not. Additionally cleaned up some white space and formatting in the file. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
cc2a8c77 |
|
19-Feb-2009 |
Anton Vorontsov <avorontsov@ru.mvista.com> |
PCI: Add pci_last_busno() helper This is just a handy routine that reports last PCI busno: we walk down all the hoses and return last hose's last_busno. Will be used by PCI/PCIe initialization code. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com> |
#
6e61fae4 |
|
03-Feb-2009 |
Becky Bruce <beckyb@kernel.crashing.org> |
drivers/pci: Create pci_map_bar function It is no longer always true that the pci bus address can be used as the virtual address for pci accesses. pci_map_bar() is created to return the virtual address for a pci region. Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org> |
#
ff4e66e9 |
|
06-Feb-2009 |
Kumar Gala <galak@kernel.crashing.org> |
pci: Rename PCI_REGION_MEMORY to PCI_REGION_SYS_MEMORY for clarity The PCI_REGION_MEMORY and PCI_REGION_MEM are a bit to similar and can be confusing when reading the code. Rename PCI_REGION_MEMORY to PCI_REGION_SYS_MEMORY to clarify its used for system memory mapping purposes. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
fd6646c0 |
|
07-Jan-2009 |
Anton Vorontsov <avorontsov@ru.mvista.com> |
mpc83xx: Add support for MPC83xx PCI-E controllers This patch adds support for MPC83xx PCI-E controllers in Root Complex mode. The patch is based on Tony Li and Dave Liu work[1]. Though unlike the original patch, by default we don't register PCI-E buses for use in U-Boot, we only configure the controllers for future use in other OSes (Linux). This is done because we don't have enough of spare BATs to map all the PCI-E regions. To actually use PCI-E in U-Boot, users should explicitly define CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES symbol in the board file. And only then U-Boot will able to access PCI-E, but at the cost of disabled address translation. [1] http://lists.denx.de/pipermail/u-boot/2008-January/027630.html Signed-off-by: Tony Li <tony.li@freescale.com> Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Acked-by: Dave Liu <daveliu@freescale.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com> |
#
30e76d5e |
|
21-Oct-2008 |
Kumar Gala <galak@kernel.crashing.org> |
pci: Allow for PCI addresses to be 64-bit PCI bus is inherently 64-bit. While not all system require access to the full 64-bit PCI address range some do. This allows those systems to enable the full PCI address width via CONFIG_SYS_PCI_64BIT. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Andrew Fleming-AFLEMING <afleming@freescale.com> Acked-by: Wolfgang Denk <wd@denx.de> |
#
36f32675 |
|
07-May-2008 |
Becky Bruce <bgill@freescale.com> |
Update pci code to use phys_addr_t Physical addrs need to be represented by phys_addr_t, not unsigned long. Otherwise, systems that use CONFIG_PHYS_64BIT are going to fail mightily. Signed-off-by: Becky Bruce <becky.bruce@freescale.com> |
#
63cec581 |
|
02-Aug-2007 |
Ed Swarthout <Ed.Swarthout@freescale.com> |
Make MPC8641's PCI/PCI-E driver a common driver for many FSL parts. All of the PCI/PCI-Express driver and initialization code that was in the MPC8641HPCN port has now been moved into the common drivers/fsl_pci_init.c. In a subsequent patch, this will be utilized by the 85xx ports as well. Common PCI-E IMMAP register blocks for FSL 85xx/86xx are added. Also enable the second PCI-Express controller on 8641 by getting its BATS and CFG_ setup right. Fixed a u16 vendor compiler warning in AHCI driver too. Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com> Signed-off-by: Zhang Wei <wei.zhang@freescale.com> Signed-off-by: Jon Loeliger <jdl@freescale.com> |
#
13a7fcdf |
|
19-Oct-2006 |
Jon Loeliger <jdl@freescale.com> |
* Fix a bunch of compiler warnings for gcc 4.0 Signed-off-by: Matthew McClintock <msm@freescale.com> |
#
f0e6f57f |
|
28-Jun-2006 |
Matthew McClintock <msm@freescale.com> |
* Added PCI-X #defines for PCI-X initialization Patch by Andy Fleming on 17-Mar-2006 Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
7b230f61 |
|
12-Mar-2006 |
Wolfgang Denk <wd@pollux.denx.de> |
Merge with git://git.kernel.org/pub/scm/boot/u-boot/u-boot.git#pci
|
#
993a2275 |
|
12-Mar-2006 |
Wolfgang Denk <wd@pollux.denx.de> |
Fix bad declaration on pci_cfgfunc_nothing Patch by Sam Song, 19 Jun 2005 |
#
a179012e |
|
11-Jan-2006 |
Kumar Gala <galak@kernel.crashing.org> |
Added support for PCI prefetchable region and BARs If a host controller sets up a region as prefetchable and a device's BAR denotes it as prefetchable, allocate the BAR into the prefetch region. If a BAR is prefetchable and no prefetchable region has been setup by the controller we fall back to allocating the BAR into the normally memory region. Patch by Kumar Gala 11 Jan 2006 |
#
c157d8e2 |
|
01-Aug-2005 |
Stefan Roese <sr@denx.de> |
Add support for AMCC PPC440EP/GR eval boards Yosemite and Yellowstone. Patch by Steven Blakeslee, 27 Jul 2005 |
#
7a8e9bed |
|
31-May-2003 |
Wolfgang Denk <wdenk> |
* Patch by Marc Singer, 29 May 2003: Fixed rarp boot method for IA32 and other little-endian CPUs. * Patch by Marc Singer, 28 May 2003: Added port I/O commands. * Patch by Matthew McClintock, 28 May 2003 - cpu/mpc824x/start.S: fix relocation code when booting from RAM - minor patches for utx8245 * Patch by Daniel Engstr�m, 28 May 2003: x86 update * Patch by Dave Ellis, 9 May 2003 + 27 May 2003: add nand flash support to SXNI855T configuration fix/extend nand flash support: - fix 'nand erase' command so does not erase bad blocks - fix 'nand write' command so does not write to bad blocks - fix nand_probe() so handles no flash detected properly - add doc/README.nand - add .jffs2 and .oob options to nand read/write - add 'nand bad' command to list bad blocks - add 'clean' option to 'nand erase' to write JFFS2 clean markers - make NAND read/write faster * Patch by Rune Torgersen, 23 May 2003: Update for MPC8266ADS board |
#
c7de829c |
|
19-Nov-2002 |
Wolfgang Denk <wdenk> |
* Patch by Thomas Frieden, 13 Nov 2002: Add code for AmigaOne board (preliminary merge to U-Boot, still WIP) * Patch by Jon Diekema, 12 Nov 2002: - Adding URL for IEEE OUI lookup - Making the autoboot #defines dependent on CONFIG_AUTOBOOT_KEYED being defined. - In the CONFIG_EXTRA_ENV_SETTINGS #define, the root-on-initrd and root-on-nfs macros are designed to switch how the default boot method gets defined. |
#
c609719b |
|
02-Nov-2002 |
Wolfgang Denk <wdenk> |
Initial revision |
#
f5cbb5c7 |
|
27-Jun-2021 |
Simon Glass <sjg@chromium.org> |
x86: pci: Allow binding of some devices before relocation At present only bridge devices are bound before relocation, to save space in pre-relocation memory. In some cases we do actually want to bind a device, e.g. because it provides the console UART. Add a devicetree binding to support this. Use the PCI_VENDEV() macro to encode the cell value. This is present in U-Boot but not used, so move it to the binding header-file. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
e58f3a7d |
|
27-Jun-2021 |
Simon Glass <sjg@chromium.org> |
pci: Use const for pci_find_device_id() etc. These functions don't modify the device-ID struct that is passed in, so mark the argument as const, so the data structure can be declared that way. This allows it to be placed in the rodata section. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
c7b36007 |
|
14-May-2021 |
Tom Rini <trini@konsulko.com> |
pci: Remove non-DM board_pci_fixup_dev() declaration With the ventana boards migrated to DM_PCI and DM_ETH, we can remove this prototype. Cc: Stefano Babic <sbabic@denx.de> Signed-off-by: Tom Rini <trini@konsulko.com> |
#
cecd013f |
|
16-Apr-2021 |
Tim Harvey <tharvey@gateworks.com> |
pci: pci-uclass: Add board_pci_fixup_dev for DM_PCI Add a board_pci_fixup_dev weak function to allow PCI device fixups during enumeration. Signed-off-by: Tim Harvey <tharvey@gateworks.com> |
#
8b85dfc6 |
|
16-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: Avoid accessing seq directly At present various drivers etc. access the device's 'seq' member directly. This makes it harder to change the meaning of that member. Change access to go through a function instead. The drivers/i2c/lpc32xx_i2c.c file is left unchanged for now. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
caa4daa2 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename 'platdata' variables to just 'plat' We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
284d062e |
|
09-Sep-2020 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
pci: add a few ARI related defines Add a few defines related to PCI ARI configuration. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
51eeae91 |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add VF BAR map support for Enhanced Allocation Makes dm_pci_map_bar API available to map BAR for Virtual function PCI devices which support Enhanced Allocation. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> |
#
b8852dcf |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add support for Single-Root I/O Virtualization SR-IOV - Single Root I/O Virtualization PF - Physical Function VF - Virtual Function If SR-IOV capability is present, use it to initialize Virtual Function PCI device instances. pci_sriov_init function will read SR-IOV registers to create VF devices under the PF PCI device and also bind driver if available. This function needs to be invoked from Physical function device driver which expects VF device support, creating minimal impact on existing framework. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> |
#
e0024741 |
|
23-Jul-2020 |
Stefan Roese <sr@denx.de> |
pci: pci-uclass: Dynamically allocate the PCI regions Instead of using a fixed length pre-allocated array of regions, this patch moves to dynamically allocating the regions based on the number of available regions plus the necessary regions for DRAM banks. Since MAX_PCI_REGIONS is not needed any more, its removed completely with this patch. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Thierry Reding <treding@nvidia.com> Cc: Marek Vasut <marek.vasut+renesas@gmail.com> |
#
143eb5b1 |
|
12-May-2020 |
Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
drivers: pci: add api to get dma regions Add api to get dma regions. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com> |
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com> |
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com> |
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
7d994067 |
|
23-Apr-2019 |
Tom Rini <trini@konsulko.com> |
Merge tag 'pull-24apr19' of git://git.denx.de/u-boot-dm Various minor sandbox iumprovements Fixes for tracing with sandbox Refactoring for boot_get_fdt()
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
a8c5f8d3 |
|
15-Oct-2018 |
Bin Meng <bmeng.cn@gmail.com> |
dm: pci: Add APIs to find next capability and extended capability This introduces two new APIs dm_pci_find_next_capability() and dm_pci_find_next_ext_capability() to get PCI capability address and PCI express extended capability address for a given PCI device starting from a given offset. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
dac01fd8 |
|
03-Aug-2018 |
Bin Meng <bmeng.cn@gmail.com> |
dm: pci: Add APIs to find capability and extended capability This introduces two new APIs dm_pci_find_capability() and dm_pci_find_ext_capability() to get PCI capability address and PCI express extended capability address for a given PCI device. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
5d544f96 |
|
03-Aug-2018 |
Bin Meng <bmeng.cn@gmail.com> |
pci: Add all known capability and extended capability ids Currently we don't have a complete list of capability and extended capability ids. This adds them. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
4345998a |
|
03-Aug-2018 |
Bin Meng <bmeng.cn@gmail.com> |
pci: sandbox: Support dynamically binding device driver At present all emulated sandbox pci devices must be present in the device tree in order to be used. The real world pci uclass driver supports pci device driver matching, and we should add such support on sandbox too. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
01259c93 |
|
03-Aug-2018 |
Bin Meng <bmeng.cn@gmail.com> |
pci: Remove 440ep-specific macros These macros should not be put in the generic pci.h header file. Since they are not referenced anywhere, remove them completely. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
5ce9aca8 |
|
14-May-2018 |
Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi> |
PCI: Document pciauto_region_allocate() Add a doc comment for pciauto_region_allocate(). Signed-off-by: Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
d71975ae |
|
14-May-2018 |
Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi> |
PCI: autoconfig: Don't allocate 64-bit addresses to 32-bit only resources Currently, if we happen to allocate an address requiring 64 bits to a device only supporting 32-bit BARs, the address eventually gets silently truncated to 32 bits. Avoid this by adding a new flag to pciauto_region_allocate() to bail out in such situations. Signed-off-by: Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
83d290c5 |
|
06-May-2018 |
Tom Rini <trini@konsulko.com> |
SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com> |
#
ed68ccbf |
|
13-Mar-2018 |
Stefan Roese <sr@denx.de> |
pci: Remove unused ppc4xx variable from struct pci_controller ppc4xx support was removed some time ago. Lets remove the now unused "pci_fb" variable from "struct pci_controller" as well. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Simon Glass <sjg@chromium.org> |
#
badb9922 |
|
19-Sep-2017 |
Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi> |
pci: Add helper for implementing memory-mapped config space accesses This sort of pattern for implementing memory-mapped PCI config space accesses appears in U-Boot twice already, and a third user is coming up. So add helper functions to avoid code duplication, similar to how Linux has pci_generic_config_write and pci_generic_config_read. Signed-off-by: Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
6ecbe137 |
|
12-May-2017 |
Tim Harvey <tharvey@gateworks.com> |
drivers: pci: imx: add imx_pcie_remove function There is no dedicated reset signal wired up for the MX6QDL thus if the bootloader enables the link we need some special handling to get the core back into a state where it is safe to touch it for configuration. While there has been some special handling in the Linux kernel to do this, it was removed in 4.11 thus we need to do it properly in the bootloader and therefore without this if you enable PCI in the bootloader you will hang while booting the 4.11 kernel. This puts the PCIe controller back into a safe state for the kernel driver before launching the kernel. Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com> Tested-by: Peter Senna Tschudin <peter.senna@collabora.com> |
#
eeb5b1ad |
|
10-Mar-2016 |
Stuart Yoder <stuart.yoder@nxp.com> |
pci: make pci_get_hose_head() available to external users Put pci_get_hose_head() prototype in header so it is available to external users, allowing them to find and iterate over all pci controllers. Signed-off-by: Stuart Yoder <stuart.yoder@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
4974a6ff |
|
06-Mar-2016 |
Simon Glass <sjg@chromium.org> |
pci: Correct a few comments and nits Two comments are missing a parameter and there is an extra blank line. Also two of the region access macros are misnamed. Correct these problems. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
319dba1f |
|
06-Mar-2016 |
Simon Glass <sjg@chromium.org> |
pci: Add functions to update PCI configuration registers It is common to read a config register value, clear and set some bits, then write back the updated value. Add functions to do this in one step, for convenience. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
308143ef |
|
02-Feb-2016 |
Bin Meng <bmeng.cn@gmail.com> |
dm: pci: Add missing forward declarations When CONFIG_DM_PCI_COMPAT is not on, there is only a forward declaration for pci_write_config32(). Add other missing ones. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
9d731c82 |
|
18-Jan-2016 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to write a BAR Add a driver-model version of the pci_write_bar32 function so that this is supported in the new API. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
7e78b9ef |
|
29-Nov-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Switch to DM API for PCI address mapping We should use the new address mapping functions unless we are in compatibility mode. Disable the old functions by default. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
21d1fe7e |
|
29-Nov-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add driver model API functions for address mapping At present the PCI address map functions use the old API. Add new functions for this so that drivers can be converted. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
bab17cf1 |
|
29-Nov-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR Add a driver-model function for reading the PCI BAR from a device. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
a0eb8356 |
|
29-Nov-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a driver-model version of pci_find_class() Add a function which scans the driver model device information rather than scanning the PCI bus again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> |
#
5c0bf647 |
|
29-Nov-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a driver-model version of pci_find_device() Add a function which scans the driver model device information rather than scanning the PCI bus again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> |
#
5e23b8b4 |
|
29-Nov-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Use driver model PCI API in auto-config At present we are using legacy functions even in the auto-configuration code used by driver model. Add a new pci_auto.c version which uses the correct API. Create a new pci_internal.h header to hold functions that are used within the PCI subsystem, but are not exported to other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> |
#
f3f1faef |
|
29-Nov-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a dm_ prefix to pci_bus_find_bdf() Most driver model PCI functions have a dm_ prefix. At some point, when the old code is converted to driver model and the old functions are removed, we will drop that prefix. For consistency, we should use the dm_ prefix for all driver model functions. Update pci_bus_find_bdf() accordingly. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
21ccce1b |
|
29-Nov-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a dm_ prefix to pci_get_bdf() Most driver model PCI functions have a dm_ prefix. At some point, when the old code is converted to driver model and the old functions are removed, we will drop that prefix. For consistency, we should use the dm_ prefix for all driver model functions. Update pci_get_bdf() accordingly. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
3ba5f74a |
|
26-Nov-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Disable PCI compatibility functions by default We eventually need to drop the compatibility functions for driver model. As a first step, create a configuration option to enable them and hide them when the option is disabled. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
54fe7b1c |
|
26-Nov-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a comment about how to find struct pci_controller With driver mode, struct pci_controller is stored as uclass-private data. Add a comment to that effect. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
f9260336 |
|
19-Nov-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to find the regions for a PCI bus This function looks up the controller and returns a pointer to each region type. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Stephen Warren <swarren@nvidia.com> Tested-by: Stephen Warren <swarren@nvidia.com> |
#
9f60fb0d |
|
19-Nov-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to get the controller for a bus A PCI bus may be a bridge device where the controller is the bridge's parent. Add a function to return the controller device, given a PCI device. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Stephen Warren <swarren@nvidia.com> Tested-by: Stephen Warren <swarren@nvidia.com> |
#
9289db6c |
|
19-Nov-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add functions to emulate 8- and 16-bit access Provide a few functions to support using 32-bit access to emulate 8- and 16-bit access. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Stephen Warren <swarren@nvidia.com> Tested-by: Stephen Warren <swarren@nvidia.com> |
#
bcbe3d15 |
|
28-Sep-2015 |
Simon Glass <sjg@chromium.org> |
dm: Rename dev_get_parentdata() to dev_get_parent_priv() The current name is inconsistent with other driver model data access functions. Rename it and fix up all users. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Joe Hershberger <joe.hershberger@ni.com> |
#
dc5740df |
|
22-Aug-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a comment to help find pci_hose_read_config_byte, etc. These functions are defined by macros so do not show up with grep. Add a comment to help. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
76c3fbcd |
|
10-Aug-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a way to iterate through all PCI devices These functions allow iteration through all PCI devices including bridges. The children of each PCI bus are returned in turn. This can be useful for configuring, checking or enumerating all the devices. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
66afb4ed |
|
10-Aug-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Provide friendly config access functions At present there are no PCI functions which allow access to PCI configuration using a struct udevice. This is a sad situation for driver model as it makes use of PCI harder. Add these functions. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
5f48d798 |
|
27-Jul-2015 |
Simon Glass <sjg@chromium.org> |
pci: Add a constant for an invalid interrupt Rather than using 0xff in the code, add a constant. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
ed5b580b |
|
09-Jul-2015 |
Minghuan Lian <Minghuan.Lian@freescale.com> |
drivers/pci: Add function to find an extended capability PCIe extends device's configuration space to 4k and provides extended capability. The patch adds function to find them. The code is ported from Linux PCIe driver. Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
4b515e4f |
|
06-Jul-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to get the BDF for a device It is useful to be able to find the full PCI address (bus, device and function) for a PCI device. Add a function to provide this. Adjust the existing code to use this. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
aba92962 |
|
06-Jul-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add support for PCI driver matching At present all PCI devices must be present in the device tree in order to be used. Many or most PCI devices don't require any configuration other than that which is done automatically by U-Boot. It is inefficent to add a node with nothing but a compatible string in order to get a device working. Add a mechanism whereby PCI drivers can be declared along with the device parameters they support (vendor/device/class). When no suitable driver is found in the device tree the list of such devices is consulted to determine the correct driver. If this also fails, then a generic driver is used as before. The mechanism used is very similar to that provided by Linux and the header file defintions are copied from Linux 4.1. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Joe Hershberger <joe.hershberger@ni.com> |
#
6c89663c |
|
07-Jul-2015 |
Bin Meng <bmeng.cn@gmail.com> |
pci: Configure expansion ROM during auto config process Currently PCI expansion ROM address is assigned by a call to pciauto_setup_rom() outside of the pci auto config process. This does not work when expansion ROM is on a device behind PCI bridge where bridge's memory limit register was already programmed to a value that does not cover the newly assigned expansion ROM address. To fix this, we should configure the ROM address during the auto config process. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Acked-by: Simon Glass <sjg@chromium.org> |
#
aec241df |
|
07-Jun-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Use the correct hose when configuring devices Only the PCI controller has access to the PCI region information. Make sure to use the controller (rather than any attached bridges) when configuring devices. This corrects a failure to scan and configure devices when driver model is enabled for PCI. Also add a comment to explain the problem. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
36d0d3b4 |
|
05-Mar-2015 |
Simon Glass <sjg@chromium.org> |
dm: sandbox: pci: Add a PCI emulation uclass Since sandbox does not have real devices (unless it borrows those from the host) it must use emulations. Provide a uclass which permits PCI operations to be passed through to an emulation device. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
ff3e077b |
|
05-Mar-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a uclass for PCI Add a uclass for PCI controllers and a generic one for PCI devices. Adjust the 'pci' command and the existing PCI support to work with this new uclass. Keep most of the compatibility code in a separate file so that it can be removed one day. TODO: Add more header file comments to the new parts of pci.h Signed-off-by: Simon Glass <sjg@chromium.org> |
#
aab6724c |
|
05-Mar-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move common PCI functions into their own file Driver model will share many functions with the existing PCI implementation. Move these into their own file to avoid duplication and confusion. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
250e039d |
|
27-Jan-2015 |
Simon Glass <sjg@chromium.org> |
pci: Add a function to find a device by class There is an existing function prototype in the header file but it is not implemented. Implement something similar. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
4a2708a0 |
|
14-Jan-2015 |
Simon Glass <sjg@chromium.org> |
x86: Access the VGA ROM when needed Add code to the generic pci_rom file to access the VGA ROM in PCI space when needed. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
d622ac39 |
|
15-Dec-2014 |
Masahiro Yamada <yamada.m@jp.panasonic.com> |
powerpc: mpc824x: remove MPC824X cpu support All the MPC824X boards are still non-generic boards: A3000, CPC45, CU824, eXalion, MVBLUE, MUSENKI, Sandpoint824x, utx8245 Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Josef Wagner <Wagner@Microsys.de> Cc: Torsten Demke <torsten.demke@fci.com> Cc: Jim Thompson <jim@musenki.com> Cc: Greg Allen <gallen@arlut.utexas.edu> |
#
e8a552eb |
|
14-Nov-2014 |
Simon Glass <sjg@chromium.org> |
pci: Add functions to read and write a BAR address Some PCI functions cannot be auto-configured. Add a function to set up a fixed BAR which can be used in these situations. Also add a function to read the current address of a BAR. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
4efe52bf |
|
12-Nov-2014 |
Thierry Reding <treding@nvidia.com> |
pci: Honour pci_skip_dev() When enumerating devices, honour the pci_skip_dev() function. This can be used by PCI controller drivers to restrict which devices will be probed. This is required by the NVIDIA Tegra PCIe controller driver, which will fail with a data abort exception if an access is attempted to a device number larger than 0 outside of bus 0. pci_skip_dev() is therefore implemented to prevent any such accesses. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Simon Glass <sjg@chromium.org> |
#
0991866c |
|
07-Aug-2014 |
Tim Harvey <tharvey@gateworks.com> |
pci: add support for board_pci_fixup_dev function Some board-level drivers may wish to have per-device fixup functions for PCI devices. Signed-off-by: Tim Harvey <tharvey@gateworks.com> |
#
fa5cec03 |
|
08-Nov-2013 |
Paul Burton <paul.burton@mips.com> |
pci.h: allow inclusion in assembly source This patch simply #ifdef's out the C-specific parts of pci.h when it is included by an assembly file. This will allow the macros it contains to be used from assembly source as will be done in a followup commit adding support for more modern MIPS Malta boards. Signed-off-by: Paul Burton <paul.burton@imgtec.com> |
#
287df01e |
|
11-Oct-2013 |
Zhao Qiang <B45475@freescale.com> |
PCIe:change the method to get the address of a requested capability in configuration space. Previously, the address of a requested capability is define like that "#define PCI_DCR 0x78" But, the addresses of capabilities is different with regard to PCIe revs. So this method is not flexible. Now a function to get the address of a requested capability is added and used. It can get the address dynamically by capability ID. The step of this function: 1. Read Status register in PCIe configuration space to confirm that Capabilities List is valid. 2. Find the address of Capabilities Pointer Register. 3. Find the address of requested capability from the first capability. Signed-off-by: Zhao Qiang <B45475@freescale.com> |
#
7b4e5844 |
|
03-Jul-2013 |
Zang Roy-R61911 <tie-fei.zang@freescale.com> |
powerpc/pcie: add PCIe version 3.x support T4240 PCIe IP is version 3.0 and has some update comparing previous QorIQ products. 1. Move Freescale specific register define to arch/powerpc/include/asm/fsl_pci.h and update the register offset define for T4240. 2. add the status/control register define use status/control register to judge the link status 3. The original code uses 'Programming Interface' field to judge if PCIE is EP or RC mode, however, T4240 does not support this functionality. According to PCIE specification, 'Header Type' offset 0x0e is used to indicate header type, so for PCIE controller, the patch changes code to use 'Header Type' field to identify if the PCIE is RC or EP mode. This patch fixes the PCIe card link up issue on T4240QDS. Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com> |
#
1a459660 |
|
08-Jul-2013 |
Wolfgang Denk <wd@denx.de> |
Add GPL-2.0+ SPDX-License-Identifier to source files Signed-off-by: Wolfgang Denk <wd@denx.de> [trini: Fixup common/cmd_io.c] Signed-off-by: Tom Rini <trini@ti.com> |
#
bc3442aa |
|
11-Jun-2013 |
Simon Glass <sjg@chromium.org> |
pci: Convert extern inline functions to static inline I am not sure of the meaning of extern inline, but this gives errors when building with function instrumenting enabled. Change these functions to static inline. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
842033e6 |
|
30-May-2013 |
Gabor Juhos <juhosg@openwrt.org> |
pci: introduce CONFIG_PCI_INDIRECT_BRIDGE option The pci_indirect.c file is always compiled when CONFIG_PCI is defined although the indirect PCI bridge support is not needed by every board. Introduce a new CONFIG_PCI_INDIRECT_BRIDGE config option and only compile indirect PCI bridge support if this options is enabled. Also add the new option into the configuration files of the boards which needs that. Compile tested for powerpc, x86, arm and nds32. MAKEALL results: powerpc: --------------------- SUMMARY ---------------------------- Boards compiled: 641 Boards with warnings but no errors: 2 ( ELPPC MPC8323ERDB ) ---------------------------------------------------------- Note: the warnings for ELPPC and MPC8323ERDB are present even without the actual patch. x86: --------------------- SUMMARY ---------------------------- Boards compiled: 1 ---------------------------------------------------------- arm: --------------------- SUMMARY ---------------------------- Boards compiled: 311 ---------------------------------------------------------- nds32: --------------------- SUMMARY ---------------------------- Boards compiled: 3 ---------------------------------------------------------- Cc: Tom Rini <trini@ti.com> Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com> Signed-off-by: Gabor Juhos <juhosg@openwrt.org> |
#
55ae10f8 |
|
20-Oct-2012 |
Bill Richardson <wfrichar@chromium.org> |
x86: gpio: Add GPIO driver for Intel ICH6 and later. Implement <asm-generic/gpio.h> functions for Intel ICH6 and later. Only GPIOs 0-31 are handled by this code. Signed-off-by: Bill Richardson <wfrichar@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org> |
#
a3a70725 |
|
24-Mar-2012 |
Linus Walleij <linus.walleij@linaro.org> |
pci: declare pciauto functions in header The FSL PCI driver uses local prototypes for pciauto_[pre|post]scan_setup_bridge(), this does not seem right, so move them to the <pci.h> file. Fixed a small extern declaration too, this is harmless but distracts the view since all other prototypes are explicitly external. Signed-off-by: Linus Walleij <linus.walleij@linaro.org> |
#
a1e47b66 |
|
03-Mar-2012 |
Linus Walleij <linus.walleij@linaro.org> |
pci: move pciauto_config_init() to pci.h Fixing build regressions for the Integrator I get find that a few boards try to work around the missing declaration of pciauto_config_init() by declaring it in the local scope. This does not make sense when the sibling functions are in <pci.h> so move the function to the header, ridding the build error in the Integrator and getting rid of the local declarations here and there. Reported-by: Wolfgang Denk <wd@denx.de> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> |
#
b03a466d |
|
01-Feb-2011 |
Prabhakar Kushwaha <prabhakar@freescale.com> |
powerpc/85xx: Handle PCIe initialization requires for P1021 class SoCs The P1011, P1012, P1015, P1016, P1020, P1021, P1024, & P1025 SoCs require that we initialize the SERDES registers if the lanes are configured for PCIe. Additionally these devices PCIe controller do not support ASPM and we have to explicitly disable it. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
10fa8d7c |
|
19-Jan-2011 |
Leo Liu <liucai.lfn@gmail.com> |
mpc83xx: fix pcie configuration space read/write This patch fix a problem for the pcie enumeration when the mpc83xx pcie controller is connected with switch or we use both of the two pcie controller. Signed-off-by: Leo Liu <liucai.lfn@gmail.com> fix codingstyle and compiler warning: 'pcie_priv' defined but not used Signed-off-by: Kim Phillips <kim.phillips@freescale.com> |
#
3a0e3c27 |
|
17-Dec-2010 |
Kumar Gala <galak@kernel.crashing.org> |
powerpc/fsl-pci: Determine pci_controller based on cfg addr for dts fixup Previously we passed in a specifically named struct pci_controller to determine if we had setup the particular PCI bus. Now we can search for the struct so we dont have to depend on the name or the struct being statically allocated. Introduced new find_hose_by_cfg_addr() to get back a pci_controller struct back by searching for it means we can do things like dynamically allocate them or not have to expose the static structures to all users. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Wolfgang Denk <wd@denx.de> |
#
983eb9d1 |
|
29-Oct-2010 |
Peter Tyser <ptyser@xes-inc.com> |
pci: Clean up PCI info when CONFIG_PCI_SCAN_SHOW This change does the following: - Removes the printing of the PCI interrupt line value. This is normally set to 0 by U-Boot on bootup and is rarely used during everyday operation. - Prints out the PCI function number of a device. Previously a device with multiple functions would be printed identically 2 times, which is generally confusing. For example, on an Intel 2 port gigabit Ethernet card the following was displayed: ... 04 01 8086 1010 0200 00 04 01 8086 1010 0200 00 ... - Prints a text description of each device's PCI class instead of the raw PCI class code. The textual description makes it much easier to determine what devices are installed on a PCI bus. - Changes the general formatting of the PCI device output. Previous output: PCIE1: connected as Root Complex 04 01 8086 1010 0200 00 04 01 8086 1010 0200 00 03 00 10b5 8112 0604 00 02 01 10b5 8518 0604 00 02 02 10b5 8518 0604 00 08 00 1957 0040 0b20 00 07 00 10b5 8518 0604 00 09 00 10b5 8112 0604 00 07 01 10b5 8518 0604 00 07 02 10b5 8518 0604 00 06 00 10b5 8518 0604 00 02 03 10b5 8518 0604 00 01 00 10b5 8518 0604 00 PCIE1: Bus 00 - 0b PCIE2: connected as Root Complex 0d 00 1957 0040 0b20 00 PCIE2: Bus 0c - 0d Updated output: PCIE1: connected as Root Complex 04:01.0 - 8086:1010 - Network controller 04:01.1 - 8086:1010 - Network controller 03:00.0 - 10b5:8112 - Bridge device 02:01.0 - 10b5:8518 - Bridge device 02:02.0 - 10b5:8518 - Bridge device 08:00.0 - 1957:0040 - Processor 07:00.0 - 10b5:8518 - Bridge device 09:00.0 - 10b5:8112 - Bridge device 07:01.0 - 10b5:8518 - Bridge device 07:02.0 - 10b5:8518 - Bridge device 06:00.0 - 10b5:8518 - Bridge device 02:03.0 - 10b5:8518 - Bridge device 01:00.0 - 10b5:8518 - Bridge device PCIE1: Bus 00 - 0b PCIE2: connected as Root Complex 0d:00.0 - 1957:0040 - Processor PCIE2: Bus 0c - 0d Signed-off-by: Peter Tyser <ptyser@xes-inc.com> |
#
8295b944 |
|
05-Aug-2009 |
Kumar Gala <galak@kernel.crashing.org> |
pci/fsl_pci_init: Use PCIe capability to determine if controller is PCIe Change the code to use the PCIe capabilities register to determine if we are a PCIe controller or not. Additionally cleaned up some white space and formatting in the file. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
cc2a8c77 |
|
19-Feb-2009 |
Anton Vorontsov <avorontsov@ru.mvista.com> |
PCI: Add pci_last_busno() helper This is just a handy routine that reports last PCI busno: we walk down all the hoses and return last hose's last_busno. Will be used by PCI/PCIe initialization code. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com> |
#
6e61fae4 |
|
03-Feb-2009 |
Becky Bruce <beckyb@kernel.crashing.org> |
drivers/pci: Create pci_map_bar function It is no longer always true that the pci bus address can be used as the virtual address for pci accesses. pci_map_bar() is created to return the virtual address for a pci region. Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org> |
#
ff4e66e9 |
|
06-Feb-2009 |
Kumar Gala <galak@kernel.crashing.org> |
pci: Rename PCI_REGION_MEMORY to PCI_REGION_SYS_MEMORY for clarity The PCI_REGION_MEMORY and PCI_REGION_MEM are a bit to similar and can be confusing when reading the code. Rename PCI_REGION_MEMORY to PCI_REGION_SYS_MEMORY to clarify its used for system memory mapping purposes. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
fd6646c0 |
|
07-Jan-2009 |
Anton Vorontsov <avorontsov@ru.mvista.com> |
mpc83xx: Add support for MPC83xx PCI-E controllers This patch adds support for MPC83xx PCI-E controllers in Root Complex mode. The patch is based on Tony Li and Dave Liu work[1]. Though unlike the original patch, by default we don't register PCI-E buses for use in U-Boot, we only configure the controllers for future use in other OSes (Linux). This is done because we don't have enough of spare BATs to map all the PCI-E regions. To actually use PCI-E in U-Boot, users should explicitly define CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES symbol in the board file. And only then U-Boot will able to access PCI-E, but at the cost of disabled address translation. [1] http://lists.denx.de/pipermail/u-boot/2008-January/027630.html Signed-off-by: Tony Li <tony.li@freescale.com> Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Acked-by: Dave Liu <daveliu@freescale.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com> |
#
30e76d5e |
|
21-Oct-2008 |
Kumar Gala <galak@kernel.crashing.org> |
pci: Allow for PCI addresses to be 64-bit PCI bus is inherently 64-bit. While not all system require access to the full 64-bit PCI address range some do. This allows those systems to enable the full PCI address width via CONFIG_SYS_PCI_64BIT. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Andrew Fleming-AFLEMING <afleming@freescale.com> Acked-by: Wolfgang Denk <wd@denx.de> |
#
36f32675 |
|
07-May-2008 |
Becky Bruce <bgill@freescale.com> |
Update pci code to use phys_addr_t Physical addrs need to be represented by phys_addr_t, not unsigned long. Otherwise, systems that use CONFIG_PHYS_64BIT are going to fail mightily. Signed-off-by: Becky Bruce <becky.bruce@freescale.com> |
#
63cec581 |
|
02-Aug-2007 |
Ed Swarthout <Ed.Swarthout@freescale.com> |
Make MPC8641's PCI/PCI-E driver a common driver for many FSL parts. All of the PCI/PCI-Express driver and initialization code that was in the MPC8641HPCN port has now been moved into the common drivers/fsl_pci_init.c. In a subsequent patch, this will be utilized by the 85xx ports as well. Common PCI-E IMMAP register blocks for FSL 85xx/86xx are added. Also enable the second PCI-Express controller on 8641 by getting its BATS and CFG_ setup right. Fixed a u16 vendor compiler warning in AHCI driver too. Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com> Signed-off-by: Zhang Wei <wei.zhang@freescale.com> Signed-off-by: Jon Loeliger <jdl@freescale.com> |
#
13a7fcdf |
|
19-Oct-2006 |
Jon Loeliger <jdl@freescale.com> |
* Fix a bunch of compiler warnings for gcc 4.0 Signed-off-by: Matthew McClintock <msm@freescale.com> |
#
f0e6f57f |
|
28-Jun-2006 |
Matthew McClintock <msm@freescale.com> |
* Added PCI-X #defines for PCI-X initialization Patch by Andy Fleming on 17-Mar-2006 Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
7b230f61 |
|
12-Mar-2006 |
Wolfgang Denk <wd@pollux.denx.de> |
Merge with git://git.kernel.org/pub/scm/boot/u-boot/u-boot.git#pci
|
#
993a2275 |
|
12-Mar-2006 |
Wolfgang Denk <wd@pollux.denx.de> |
Fix bad declaration on pci_cfgfunc_nothing Patch by Sam Song, 19 Jun 2005 |
#
a179012e |
|
11-Jan-2006 |
Kumar Gala <galak@kernel.crashing.org> |
Added support for PCI prefetchable region and BARs If a host controller sets up a region as prefetchable and a device's BAR denotes it as prefetchable, allocate the BAR into the prefetch region. If a BAR is prefetchable and no prefetchable region has been setup by the controller we fall back to allocating the BAR into the normally memory region. Patch by Kumar Gala 11 Jan 2006 |
#
c157d8e2 |
|
01-Aug-2005 |
Stefan Roese <sr@denx.de> |
Add support for AMCC PPC440EP/GR eval boards Yosemite and Yellowstone. Patch by Steven Blakeslee, 27 Jul 2005 |
#
7a8e9bed |
|
31-May-2003 |
Wolfgang Denk <wdenk> |
* Patch by Marc Singer, 29 May 2003: Fixed rarp boot method for IA32 and other little-endian CPUs. * Patch by Marc Singer, 28 May 2003: Added port I/O commands. * Patch by Matthew McClintock, 28 May 2003 - cpu/mpc824x/start.S: fix relocation code when booting from RAM - minor patches for utx8245 * Patch by Daniel Engstr�m, 28 May 2003: x86 update * Patch by Dave Ellis, 9 May 2003 + 27 May 2003: add nand flash support to SXNI855T configuration fix/extend nand flash support: - fix 'nand erase' command so does not erase bad blocks - fix 'nand write' command so does not write to bad blocks - fix nand_probe() so handles no flash detected properly - add doc/README.nand - add .jffs2 and .oob options to nand read/write - add 'nand bad' command to list bad blocks - add 'clean' option to 'nand erase' to write JFFS2 clean markers - make NAND read/write faster * Patch by Rune Torgersen, 23 May 2003: Update for MPC8266ADS board |
#
c7de829c |
|
19-Nov-2002 |
Wolfgang Denk <wdenk> |
* Patch by Thomas Frieden, 13 Nov 2002: Add code for AmigaOne board (preliminary merge to U-Boot, still WIP) * Patch by Jon Diekema, 12 Nov 2002: - Adding URL for IEEE OUI lookup - Making the autoboot #defines dependent on CONFIG_AUTOBOOT_KEYED being defined. - In the CONFIG_EXTRA_ENV_SETTINGS #define, the root-on-initrd and root-on-nfs macros are designed to switch how the default boot method gets defined. |
#
c609719b |
|
02-Nov-2002 |
Wolfgang Denk <wdenk> |
Initial revision |
#
c7b36007 |
|
14-May-2021 |
Tom Rini <trini@konsulko.com> |
pci: Remove non-DM board_pci_fixup_dev() declaration With the ventana boards migrated to DM_PCI and DM_ETH, we can remove this prototype. Cc: Stefano Babic <sbabic@denx.de> Signed-off-by: Tom Rini <trini@konsulko.com> |
#
cecd013f |
|
16-Apr-2021 |
Tim Harvey <tharvey@gateworks.com> |
pci: pci-uclass: Add board_pci_fixup_dev for DM_PCI Add a board_pci_fixup_dev weak function to allow PCI device fixups during enumeration. Signed-off-by: Tim Harvey <tharvey@gateworks.com> |
#
8b85dfc6 |
|
16-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: Avoid accessing seq directly At present various drivers etc. access the device's 'seq' member directly. This makes it harder to change the meaning of that member. Change access to go through a function instead. The drivers/i2c/lpc32xx_i2c.c file is left unchanged for now. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
caa4daa2 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename 'platdata' variables to just 'plat' We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
284d062e |
|
09-Sep-2020 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
pci: add a few ARI related defines Add a few defines related to PCI ARI configuration. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
51eeae91 |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add VF BAR map support for Enhanced Allocation Makes dm_pci_map_bar API available to map BAR for Virtual function PCI devices which support Enhanced Allocation. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> |
#
b8852dcf |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add support for Single-Root I/O Virtualization SR-IOV - Single Root I/O Virtualization PF - Physical Function VF - Virtual Function If SR-IOV capability is present, use it to initialize Virtual Function PCI device instances. pci_sriov_init function will read SR-IOV registers to create VF devices under the PF PCI device and also bind driver if available. This function needs to be invoked from Physical function device driver which expects VF device support, creating minimal impact on existing framework. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> |
#
e0024741 |
|
23-Jul-2020 |
Stefan Roese <sr@denx.de> |
pci: pci-uclass: Dynamically allocate the PCI regions Instead of using a fixed length pre-allocated array of regions, this patch moves to dynamically allocating the regions based on the number of available regions plus the necessary regions for DRAM banks. Since MAX_PCI_REGIONS is not needed any more, its removed completely with this patch. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Thierry Reding <treding@nvidia.com> Cc: Marek Vasut <marek.vasut+renesas@gmail.com> |
#
143eb5b1 |
|
12-May-2020 |
Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
drivers: pci: add api to get dma regions Add api to get dma regions. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com> |
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com> |
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com> |
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
7d994067 |
|
23-Apr-2019 |
Tom Rini <trini@konsulko.com> |
Merge tag 'pull-24apr19' of git://git.denx.de/u-boot-dm Various minor sandbox iumprovements Fixes for tracing with sandbox Refactoring for boot_get_fdt()
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
a8c5f8d3 |
|
15-Oct-2018 |
Bin Meng <bmeng.cn@gmail.com> |
dm: pci: Add APIs to find next capability and extended capability This introduces two new APIs dm_pci_find_next_capability() and dm_pci_find_next_ext_capability() to get PCI capability address and PCI express extended capability address for a given PCI device starting from a given offset. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
dac01fd8 |
|
03-Aug-2018 |
Bin Meng <bmeng.cn@gmail.com> |
dm: pci: Add APIs to find capability and extended capability This introduces two new APIs dm_pci_find_capability() and dm_pci_find_ext_capability() to get PCI capability address and PCI express extended capability address for a given PCI device. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
5d544f96 |
|
03-Aug-2018 |
Bin Meng <bmeng.cn@gmail.com> |
pci: Add all known capability and extended capability ids Currently we don't have a complete list of capability and extended capability ids. This adds them. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
4345998a |
|
03-Aug-2018 |
Bin Meng <bmeng.cn@gmail.com> |
pci: sandbox: Support dynamically binding device driver At present all emulated sandbox pci devices must be present in the device tree in order to be used. The real world pci uclass driver supports pci device driver matching, and we should add such support on sandbox too. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
01259c93 |
|
03-Aug-2018 |
Bin Meng <bmeng.cn@gmail.com> |
pci: Remove 440ep-specific macros These macros should not be put in the generic pci.h header file. Since they are not referenced anywhere, remove them completely. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
5ce9aca8 |
|
14-May-2018 |
Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi> |
PCI: Document pciauto_region_allocate() Add a doc comment for pciauto_region_allocate(). Signed-off-by: Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
d71975ae |
|
14-May-2018 |
Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi> |
PCI: autoconfig: Don't allocate 64-bit addresses to 32-bit only resources Currently, if we happen to allocate an address requiring 64 bits to a device only supporting 32-bit BARs, the address eventually gets silently truncated to 32 bits. Avoid this by adding a new flag to pciauto_region_allocate() to bail out in such situations. Signed-off-by: Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
83d290c5 |
|
06-May-2018 |
Tom Rini <trini@konsulko.com> |
SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com> |
#
ed68ccbf |
|
13-Mar-2018 |
Stefan Roese <sr@denx.de> |
pci: Remove unused ppc4xx variable from struct pci_controller ppc4xx support was removed some time ago. Lets remove the now unused "pci_fb" variable from "struct pci_controller" as well. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Simon Glass <sjg@chromium.org> |
#
badb9922 |
|
19-Sep-2017 |
Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi> |
pci: Add helper for implementing memory-mapped config space accesses This sort of pattern for implementing memory-mapped PCI config space accesses appears in U-Boot twice already, and a third user is coming up. So add helper functions to avoid code duplication, similar to how Linux has pci_generic_config_write and pci_generic_config_read. Signed-off-by: Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
6ecbe137 |
|
12-May-2017 |
Tim Harvey <tharvey@gateworks.com> |
drivers: pci: imx: add imx_pcie_remove function There is no dedicated reset signal wired up for the MX6QDL thus if the bootloader enables the link we need some special handling to get the core back into a state where it is safe to touch it for configuration. While there has been some special handling in the Linux kernel to do this, it was removed in 4.11 thus we need to do it properly in the bootloader and therefore without this if you enable PCI in the bootloader you will hang while booting the 4.11 kernel. This puts the PCIe controller back into a safe state for the kernel driver before launching the kernel. Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com> Tested-by: Peter Senna Tschudin <peter.senna@collabora.com> |
#
eeb5b1ad |
|
10-Mar-2016 |
Stuart Yoder <stuart.yoder@nxp.com> |
pci: make pci_get_hose_head() available to external users Put pci_get_hose_head() prototype in header so it is available to external users, allowing them to find and iterate over all pci controllers. Signed-off-by: Stuart Yoder <stuart.yoder@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
4974a6ff |
|
06-Mar-2016 |
Simon Glass <sjg@chromium.org> |
pci: Correct a few comments and nits Two comments are missing a parameter and there is an extra blank line. Also two of the region access macros are misnamed. Correct these problems. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
319dba1f |
|
06-Mar-2016 |
Simon Glass <sjg@chromium.org> |
pci: Add functions to update PCI configuration registers It is common to read a config register value, clear and set some bits, then write back the updated value. Add functions to do this in one step, for convenience. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
308143ef |
|
02-Feb-2016 |
Bin Meng <bmeng.cn@gmail.com> |
dm: pci: Add missing forward declarations When CONFIG_DM_PCI_COMPAT is not on, there is only a forward declaration for pci_write_config32(). Add other missing ones. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
9d731c82 |
|
18-Jan-2016 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to write a BAR Add a driver-model version of the pci_write_bar32 function so that this is supported in the new API. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
7e78b9ef |
|
29-Nov-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Switch to DM API for PCI address mapping We should use the new address mapping functions unless we are in compatibility mode. Disable the old functions by default. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
21d1fe7e |
|
29-Nov-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add driver model API functions for address mapping At present the PCI address map functions use the old API. Add new functions for this so that drivers can be converted. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
bab17cf1 |
|
29-Nov-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR Add a driver-model function for reading the PCI BAR from a device. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
a0eb8356 |
|
29-Nov-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a driver-model version of pci_find_class() Add a function which scans the driver model device information rather than scanning the PCI bus again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> |
#
5c0bf647 |
|
29-Nov-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a driver-model version of pci_find_device() Add a function which scans the driver model device information rather than scanning the PCI bus again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> |
#
5e23b8b4 |
|
29-Nov-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Use driver model PCI API in auto-config At present we are using legacy functions even in the auto-configuration code used by driver model. Add a new pci_auto.c version which uses the correct API. Create a new pci_internal.h header to hold functions that are used within the PCI subsystem, but are not exported to other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> |
#
f3f1faef |
|
29-Nov-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a dm_ prefix to pci_bus_find_bdf() Most driver model PCI functions have a dm_ prefix. At some point, when the old code is converted to driver model and the old functions are removed, we will drop that prefix. For consistency, we should use the dm_ prefix for all driver model functions. Update pci_bus_find_bdf() accordingly. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
21ccce1b |
|
29-Nov-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a dm_ prefix to pci_get_bdf() Most driver model PCI functions have a dm_ prefix. At some point, when the old code is converted to driver model and the old functions are removed, we will drop that prefix. For consistency, we should use the dm_ prefix for all driver model functions. Update pci_get_bdf() accordingly. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
3ba5f74a |
|
26-Nov-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Disable PCI compatibility functions by default We eventually need to drop the compatibility functions for driver model. As a first step, create a configuration option to enable them and hide them when the option is disabled. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
54fe7b1c |
|
26-Nov-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a comment about how to find struct pci_controller With driver mode, struct pci_controller is stored as uclass-private data. Add a comment to that effect. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
f9260336 |
|
19-Nov-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to find the regions for a PCI bus This function looks up the controller and returns a pointer to each region type. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Stephen Warren <swarren@nvidia.com> Tested-by: Stephen Warren <swarren@nvidia.com> |
#
9f60fb0d |
|
19-Nov-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to get the controller for a bus A PCI bus may be a bridge device where the controller is the bridge's parent. Add a function to return the controller device, given a PCI device. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Stephen Warren <swarren@nvidia.com> Tested-by: Stephen Warren <swarren@nvidia.com> |
#
9289db6c |
|
19-Nov-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add functions to emulate 8- and 16-bit access Provide a few functions to support using 32-bit access to emulate 8- and 16-bit access. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Stephen Warren <swarren@nvidia.com> Tested-by: Stephen Warren <swarren@nvidia.com> |
#
bcbe3d15 |
|
28-Sep-2015 |
Simon Glass <sjg@chromium.org> |
dm: Rename dev_get_parentdata() to dev_get_parent_priv() The current name is inconsistent with other driver model data access functions. Rename it and fix up all users. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Joe Hershberger <joe.hershberger@ni.com> |
#
dc5740df |
|
22-Aug-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a comment to help find pci_hose_read_config_byte, etc. These functions are defined by macros so do not show up with grep. Add a comment to help. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
76c3fbcd |
|
10-Aug-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a way to iterate through all PCI devices These functions allow iteration through all PCI devices including bridges. The children of each PCI bus are returned in turn. This can be useful for configuring, checking or enumerating all the devices. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
66afb4ed |
|
10-Aug-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Provide friendly config access functions At present there are no PCI functions which allow access to PCI configuration using a struct udevice. This is a sad situation for driver model as it makes use of PCI harder. Add these functions. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
5f48d798 |
|
27-Jul-2015 |
Simon Glass <sjg@chromium.org> |
pci: Add a constant for an invalid interrupt Rather than using 0xff in the code, add a constant. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
ed5b580b |
|
09-Jul-2015 |
Minghuan Lian <Minghuan.Lian@freescale.com> |
drivers/pci: Add function to find an extended capability PCIe extends device's configuration space to 4k and provides extended capability. The patch adds function to find them. The code is ported from Linux PCIe driver. Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
4b515e4f |
|
06-Jul-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to get the BDF for a device It is useful to be able to find the full PCI address (bus, device and function) for a PCI device. Add a function to provide this. Adjust the existing code to use this. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
aba92962 |
|
06-Jul-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add support for PCI driver matching At present all PCI devices must be present in the device tree in order to be used. Many or most PCI devices don't require any configuration other than that which is done automatically by U-Boot. It is inefficent to add a node with nothing but a compatible string in order to get a device working. Add a mechanism whereby PCI drivers can be declared along with the device parameters they support (vendor/device/class). When no suitable driver is found in the device tree the list of such devices is consulted to determine the correct driver. If this also fails, then a generic driver is used as before. The mechanism used is very similar to that provided by Linux and the header file defintions are copied from Linux 4.1. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Joe Hershberger <joe.hershberger@ni.com> |
#
6c89663c |
|
07-Jul-2015 |
Bin Meng <bmeng.cn@gmail.com> |
pci: Configure expansion ROM during auto config process Currently PCI expansion ROM address is assigned by a call to pciauto_setup_rom() outside of the pci auto config process. This does not work when expansion ROM is on a device behind PCI bridge where bridge's memory limit register was already programmed to a value that does not cover the newly assigned expansion ROM address. To fix this, we should configure the ROM address during the auto config process. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Acked-by: Simon Glass <sjg@chromium.org> |
#
aec241df |
|
07-Jun-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Use the correct hose when configuring devices Only the PCI controller has access to the PCI region information. Make sure to use the controller (rather than any attached bridges) when configuring devices. This corrects a failure to scan and configure devices when driver model is enabled for PCI. Also add a comment to explain the problem. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
36d0d3b4 |
|
05-Mar-2015 |
Simon Glass <sjg@chromium.org> |
dm: sandbox: pci: Add a PCI emulation uclass Since sandbox does not have real devices (unless it borrows those from the host) it must use emulations. Provide a uclass which permits PCI operations to be passed through to an emulation device. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
ff3e077b |
|
05-Mar-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a uclass for PCI Add a uclass for PCI controllers and a generic one for PCI devices. Adjust the 'pci' command and the existing PCI support to work with this new uclass. Keep most of the compatibility code in a separate file so that it can be removed one day. TODO: Add more header file comments to the new parts of pci.h Signed-off-by: Simon Glass <sjg@chromium.org> |
#
aab6724c |
|
05-Mar-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move common PCI functions into their own file Driver model will share many functions with the existing PCI implementation. Move these into their own file to avoid duplication and confusion. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
250e039d |
|
27-Jan-2015 |
Simon Glass <sjg@chromium.org> |
pci: Add a function to find a device by class There is an existing function prototype in the header file but it is not implemented. Implement something similar. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
4a2708a0 |
|
14-Jan-2015 |
Simon Glass <sjg@chromium.org> |
x86: Access the VGA ROM when needed Add code to the generic pci_rom file to access the VGA ROM in PCI space when needed. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
d622ac39 |
|
15-Dec-2014 |
Masahiro Yamada <yamada.m@jp.panasonic.com> |
powerpc: mpc824x: remove MPC824X cpu support All the MPC824X boards are still non-generic boards: A3000, CPC45, CU824, eXalion, MVBLUE, MUSENKI, Sandpoint824x, utx8245 Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Josef Wagner <Wagner@Microsys.de> Cc: Torsten Demke <torsten.demke@fci.com> Cc: Jim Thompson <jim@musenki.com> Cc: Greg Allen <gallen@arlut.utexas.edu> |
#
e8a552eb |
|
14-Nov-2014 |
Simon Glass <sjg@chromium.org> |
pci: Add functions to read and write a BAR address Some PCI functions cannot be auto-configured. Add a function to set up a fixed BAR which can be used in these situations. Also add a function to read the current address of a BAR. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
4efe52bf |
|
12-Nov-2014 |
Thierry Reding <treding@nvidia.com> |
pci: Honour pci_skip_dev() When enumerating devices, honour the pci_skip_dev() function. This can be used by PCI controller drivers to restrict which devices will be probed. This is required by the NVIDIA Tegra PCIe controller driver, which will fail with a data abort exception if an access is attempted to a device number larger than 0 outside of bus 0. pci_skip_dev() is therefore implemented to prevent any such accesses. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Simon Glass <sjg@chromium.org> |
#
0991866c |
|
07-Aug-2014 |
Tim Harvey <tharvey@gateworks.com> |
pci: add support for board_pci_fixup_dev function Some board-level drivers may wish to have per-device fixup functions for PCI devices. Signed-off-by: Tim Harvey <tharvey@gateworks.com> |
#
fa5cec03 |
|
08-Nov-2013 |
Paul Burton <paul.burton@mips.com> |
pci.h: allow inclusion in assembly source This patch simply #ifdef's out the C-specific parts of pci.h when it is included by an assembly file. This will allow the macros it contains to be used from assembly source as will be done in a followup commit adding support for more modern MIPS Malta boards. Signed-off-by: Paul Burton <paul.burton@imgtec.com> |
#
287df01e |
|
11-Oct-2013 |
Zhao Qiang <B45475@freescale.com> |
PCIe:change the method to get the address of a requested capability in configuration space. Previously, the address of a requested capability is define like that "#define PCI_DCR 0x78" But, the addresses of capabilities is different with regard to PCIe revs. So this method is not flexible. Now a function to get the address of a requested capability is added and used. It can get the address dynamically by capability ID. The step of this function: 1. Read Status register in PCIe configuration space to confirm that Capabilities List is valid. 2. Find the address of Capabilities Pointer Register. 3. Find the address of requested capability from the first capability. Signed-off-by: Zhao Qiang <B45475@freescale.com> |
#
7b4e5844 |
|
03-Jul-2013 |
Zang Roy-R61911 <tie-fei.zang@freescale.com> |
powerpc/pcie: add PCIe version 3.x support T4240 PCIe IP is version 3.0 and has some update comparing previous QorIQ products. 1. Move Freescale specific register define to arch/powerpc/include/asm/fsl_pci.h and update the register offset define for T4240. 2. add the status/control register define use status/control register to judge the link status 3. The original code uses 'Programming Interface' field to judge if PCIE is EP or RC mode, however, T4240 does not support this functionality. According to PCIE specification, 'Header Type' offset 0x0e is used to indicate header type, so for PCIE controller, the patch changes code to use 'Header Type' field to identify if the PCIE is RC or EP mode. This patch fixes the PCIe card link up issue on T4240QDS. Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com> |
#
1a459660 |
|
08-Jul-2013 |
Wolfgang Denk <wd@denx.de> |
Add GPL-2.0+ SPDX-License-Identifier to source files Signed-off-by: Wolfgang Denk <wd@denx.de> [trini: Fixup common/cmd_io.c] Signed-off-by: Tom Rini <trini@ti.com> |
#
bc3442aa |
|
11-Jun-2013 |
Simon Glass <sjg@chromium.org> |
pci: Convert extern inline functions to static inline I am not sure of the meaning of extern inline, but this gives errors when building with function instrumenting enabled. Change these functions to static inline. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
842033e6 |
|
30-May-2013 |
Gabor Juhos <juhosg@openwrt.org> |
pci: introduce CONFIG_PCI_INDIRECT_BRIDGE option The pci_indirect.c file is always compiled when CONFIG_PCI is defined although the indirect PCI bridge support is not needed by every board. Introduce a new CONFIG_PCI_INDIRECT_BRIDGE config option and only compile indirect PCI bridge support if this options is enabled. Also add the new option into the configuration files of the boards which needs that. Compile tested for powerpc, x86, arm and nds32. MAKEALL results: powerpc: --------------------- SUMMARY ---------------------------- Boards compiled: 641 Boards with warnings but no errors: 2 ( ELPPC MPC8323ERDB ) ---------------------------------------------------------- Note: the warnings for ELPPC and MPC8323ERDB are present even without the actual patch. x86: --------------------- SUMMARY ---------------------------- Boards compiled: 1 ---------------------------------------------------------- arm: --------------------- SUMMARY ---------------------------- Boards compiled: 311 ---------------------------------------------------------- nds32: --------------------- SUMMARY ---------------------------- Boards compiled: 3 ---------------------------------------------------------- Cc: Tom Rini <trini@ti.com> Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com> Signed-off-by: Gabor Juhos <juhosg@openwrt.org> |
#
55ae10f8 |
|
20-Oct-2012 |
Bill Richardson <wfrichar@chromium.org> |
x86: gpio: Add GPIO driver for Intel ICH6 and later. Implement <asm-generic/gpio.h> functions for Intel ICH6 and later. Only GPIOs 0-31 are handled by this code. Signed-off-by: Bill Richardson <wfrichar@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org> |
#
a3a70725 |
|
24-Mar-2012 |
Linus Walleij <linus.walleij@linaro.org> |
pci: declare pciauto functions in header The FSL PCI driver uses local prototypes for pciauto_[pre|post]scan_setup_bridge(), this does not seem right, so move them to the <pci.h> file. Fixed a small extern declaration too, this is harmless but distracts the view since all other prototypes are explicitly external. Signed-off-by: Linus Walleij <linus.walleij@linaro.org> |
#
a1e47b66 |
|
03-Mar-2012 |
Linus Walleij <linus.walleij@linaro.org> |
pci: move pciauto_config_init() to pci.h Fixing build regressions for the Integrator I get find that a few boards try to work around the missing declaration of pciauto_config_init() by declaring it in the local scope. This does not make sense when the sibling functions are in <pci.h> so move the function to the header, ridding the build error in the Integrator and getting rid of the local declarations here and there. Reported-by: Wolfgang Denk <wd@denx.de> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> |
#
b03a466d |
|
01-Feb-2011 |
Prabhakar Kushwaha <prabhakar@freescale.com> |
powerpc/85xx: Handle PCIe initialization requires for P1021 class SoCs The P1011, P1012, P1015, P1016, P1020, P1021, P1024, & P1025 SoCs require that we initialize the SERDES registers if the lanes are configured for PCIe. Additionally these devices PCIe controller do not support ASPM and we have to explicitly disable it. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
10fa8d7c |
|
19-Jan-2011 |
Leo Liu <liucai.lfn@gmail.com> |
mpc83xx: fix pcie configuration space read/write This patch fix a problem for the pcie enumeration when the mpc83xx pcie controller is connected with switch or we use both of the two pcie controller. Signed-off-by: Leo Liu <liucai.lfn@gmail.com> fix codingstyle and compiler warning: 'pcie_priv' defined but not used Signed-off-by: Kim Phillips <kim.phillips@freescale.com> |
#
3a0e3c27 |
|
17-Dec-2010 |
Kumar Gala <galak@kernel.crashing.org> |
powerpc/fsl-pci: Determine pci_controller based on cfg addr for dts fixup Previously we passed in a specifically named struct pci_controller to determine if we had setup the particular PCI bus. Now we can search for the struct so we dont have to depend on the name or the struct being statically allocated. Introduced new find_hose_by_cfg_addr() to get back a pci_controller struct back by searching for it means we can do things like dynamically allocate them or not have to expose the static structures to all users. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Wolfgang Denk <wd@denx.de> |
#
983eb9d1 |
|
29-Oct-2010 |
Peter Tyser <ptyser@xes-inc.com> |
pci: Clean up PCI info when CONFIG_PCI_SCAN_SHOW This change does the following: - Removes the printing of the PCI interrupt line value. This is normally set to 0 by U-Boot on bootup and is rarely used during everyday operation. - Prints out the PCI function number of a device. Previously a device with multiple functions would be printed identically 2 times, which is generally confusing. For example, on an Intel 2 port gigabit Ethernet card the following was displayed: ... 04 01 8086 1010 0200 00 04 01 8086 1010 0200 00 ... - Prints a text description of each device's PCI class instead of the raw PCI class code. The textual description makes it much easier to determine what devices are installed on a PCI bus. - Changes the general formatting of the PCI device output. Previous output: PCIE1: connected as Root Complex 04 01 8086 1010 0200 00 04 01 8086 1010 0200 00 03 00 10b5 8112 0604 00 02 01 10b5 8518 0604 00 02 02 10b5 8518 0604 00 08 00 1957 0040 0b20 00 07 00 10b5 8518 0604 00 09 00 10b5 8112 0604 00 07 01 10b5 8518 0604 00 07 02 10b5 8518 0604 00 06 00 10b5 8518 0604 00 02 03 10b5 8518 0604 00 01 00 10b5 8518 0604 00 PCIE1: Bus 00 - 0b PCIE2: connected as Root Complex 0d 00 1957 0040 0b20 00 PCIE2: Bus 0c - 0d Updated output: PCIE1: connected as Root Complex 04:01.0 - 8086:1010 - Network controller 04:01.1 - 8086:1010 - Network controller 03:00.0 - 10b5:8112 - Bridge device 02:01.0 - 10b5:8518 - Bridge device 02:02.0 - 10b5:8518 - Bridge device 08:00.0 - 1957:0040 - Processor 07:00.0 - 10b5:8518 - Bridge device 09:00.0 - 10b5:8112 - Bridge device 07:01.0 - 10b5:8518 - Bridge device 07:02.0 - 10b5:8518 - Bridge device 06:00.0 - 10b5:8518 - Bridge device 02:03.0 - 10b5:8518 - Bridge device 01:00.0 - 10b5:8518 - Bridge device PCIE1: Bus 00 - 0b PCIE2: connected as Root Complex 0d:00.0 - 1957:0040 - Processor PCIE2: Bus 0c - 0d Signed-off-by: Peter Tyser <ptyser@xes-inc.com> |
#
8295b944 |
|
05-Aug-2009 |
Kumar Gala <galak@kernel.crashing.org> |
pci/fsl_pci_init: Use PCIe capability to determine if controller is PCIe Change the code to use the PCIe capabilities register to determine if we are a PCIe controller or not. Additionally cleaned up some white space and formatting in the file. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
cc2a8c77 |
|
19-Feb-2009 |
Anton Vorontsov <avorontsov@ru.mvista.com> |
PCI: Add pci_last_busno() helper This is just a handy routine that reports last PCI busno: we walk down all the hoses and return last hose's last_busno. Will be used by PCI/PCIe initialization code. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com> |
#
6e61fae4 |
|
03-Feb-2009 |
Becky Bruce <beckyb@kernel.crashing.org> |
drivers/pci: Create pci_map_bar function It is no longer always true that the pci bus address can be used as the virtual address for pci accesses. pci_map_bar() is created to return the virtual address for a pci region. Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org> |
#
ff4e66e9 |
|
06-Feb-2009 |
Kumar Gala <galak@kernel.crashing.org> |
pci: Rename PCI_REGION_MEMORY to PCI_REGION_SYS_MEMORY for clarity The PCI_REGION_MEMORY and PCI_REGION_MEM are a bit to similar and can be confusing when reading the code. Rename PCI_REGION_MEMORY to PCI_REGION_SYS_MEMORY to clarify its used for system memory mapping purposes. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
fd6646c0 |
|
07-Jan-2009 |
Anton Vorontsov <avorontsov@ru.mvista.com> |
mpc83xx: Add support for MPC83xx PCI-E controllers This patch adds support for MPC83xx PCI-E controllers in Root Complex mode. The patch is based on Tony Li and Dave Liu work[1]. Though unlike the original patch, by default we don't register PCI-E buses for use in U-Boot, we only configure the controllers for future use in other OSes (Linux). This is done because we don't have enough of spare BATs to map all the PCI-E regions. To actually use PCI-E in U-Boot, users should explicitly define CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES symbol in the board file. And only then U-Boot will able to access PCI-E, but at the cost of disabled address translation. [1] http://lists.denx.de/pipermail/u-boot/2008-January/027630.html Signed-off-by: Tony Li <tony.li@freescale.com> Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Acked-by: Dave Liu <daveliu@freescale.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com> |
#
30e76d5e |
|
21-Oct-2008 |
Kumar Gala <galak@kernel.crashing.org> |
pci: Allow for PCI addresses to be 64-bit PCI bus is inherently 64-bit. While not all system require access to the full 64-bit PCI address range some do. This allows those systems to enable the full PCI address width via CONFIG_SYS_PCI_64BIT. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Andrew Fleming-AFLEMING <afleming@freescale.com> Acked-by: Wolfgang Denk <wd@denx.de> |
#
36f32675 |
|
07-May-2008 |
Becky Bruce <bgill@freescale.com> |
Update pci code to use phys_addr_t Physical addrs need to be represented by phys_addr_t, not unsigned long. Otherwise, systems that use CONFIG_PHYS_64BIT are going to fail mightily. Signed-off-by: Becky Bruce <becky.bruce@freescale.com> |
#
63cec581 |
|
02-Aug-2007 |
Ed Swarthout <Ed.Swarthout@freescale.com> |
Make MPC8641's PCI/PCI-E driver a common driver for many FSL parts. All of the PCI/PCI-Express driver and initialization code that was in the MPC8641HPCN port has now been moved into the common drivers/fsl_pci_init.c. In a subsequent patch, this will be utilized by the 85xx ports as well. Common PCI-E IMMAP register blocks for FSL 85xx/86xx are added. Also enable the second PCI-Express controller on 8641 by getting its BATS and CFG_ setup right. Fixed a u16 vendor compiler warning in AHCI driver too. Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com> Signed-off-by: Zhang Wei <wei.zhang@freescale.com> Signed-off-by: Jon Loeliger <jdl@freescale.com> |
#
13a7fcdf |
|
19-Oct-2006 |
Jon Loeliger <jdl@freescale.com> |
* Fix a bunch of compiler warnings for gcc 4.0 Signed-off-by: Matthew McClintock <msm@freescale.com> |
#
f0e6f57f |
|
28-Jun-2006 |
Matthew McClintock <msm@freescale.com> |
* Added PCI-X #defines for PCI-X initialization Patch by Andy Fleming on 17-Mar-2006 Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
7b230f61 |
|
12-Mar-2006 |
Wolfgang Denk <wd@pollux.denx.de> |
Merge with git://git.kernel.org/pub/scm/boot/u-boot/u-boot.git#pci
|
#
993a2275 |
|
12-Mar-2006 |
Wolfgang Denk <wd@pollux.denx.de> |
Fix bad declaration on pci_cfgfunc_nothing Patch by Sam Song, 19 Jun 2005 |
#
a179012e |
|
11-Jan-2006 |
Kumar Gala <galak@kernel.crashing.org> |
Added support for PCI prefetchable region and BARs If a host controller sets up a region as prefetchable and a device's BAR denotes it as prefetchable, allocate the BAR into the prefetch region. If a BAR is prefetchable and no prefetchable region has been setup by the controller we fall back to allocating the BAR into the normally memory region. Patch by Kumar Gala 11 Jan 2006 |
#
c157d8e2 |
|
01-Aug-2005 |
Stefan Roese <sr@denx.de> |
Add support for AMCC PPC440EP/GR eval boards Yosemite and Yellowstone. Patch by Steven Blakeslee, 27 Jul 2005 |
#
7a8e9bed |
|
31-May-2003 |
Wolfgang Denk <wdenk> |
* Patch by Marc Singer, 29 May 2003: Fixed rarp boot method for IA32 and other little-endian CPUs. * Patch by Marc Singer, 28 May 2003: Added port I/O commands. * Patch by Matthew McClintock, 28 May 2003 - cpu/mpc824x/start.S: fix relocation code when booting from RAM - minor patches for utx8245 * Patch by Daniel Engstr�m, 28 May 2003: x86 update * Patch by Dave Ellis, 9 May 2003 + 27 May 2003: add nand flash support to SXNI855T configuration fix/extend nand flash support: - fix 'nand erase' command so does not erase bad blocks - fix 'nand write' command so does not write to bad blocks - fix nand_probe() so handles no flash detected properly - add doc/README.nand - add .jffs2 and .oob options to nand read/write - add 'nand bad' command to list bad blocks - add 'clean' option to 'nand erase' to write JFFS2 clean markers - make NAND read/write faster * Patch by Rune Torgersen, 23 May 2003: Update for MPC8266ADS board |
#
c7de829c |
|
19-Nov-2002 |
Wolfgang Denk <wdenk> |
* Patch by Thomas Frieden, 13 Nov 2002: Add code for AmigaOne board (preliminary merge to U-Boot, still WIP) * Patch by Jon Diekema, 12 Nov 2002: - Adding URL for IEEE OUI lookup - Making the autoboot #defines dependent on CONFIG_AUTOBOOT_KEYED being defined. - In the CONFIG_EXTRA_ENV_SETTINGS #define, the root-on-initrd and root-on-nfs macros are designed to switch how the default boot method gets defined. |
#
c609719b |
|
02-Nov-2002 |
Wolfgang Denk <wdenk> |
Initial revision |
#
cecd013f |
|
16-Apr-2021 |
Tim Harvey <tharvey@gateworks.com> |
pci: pci-uclass: Add board_pci_fixup_dev for DM_PCI Add a board_pci_fixup_dev weak function to allow PCI device fixups during enumeration. Signed-off-by: Tim Harvey <tharvey@gateworks.com> |
#
8b85dfc6 |
|
16-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: Avoid accessing seq directly At present various drivers etc. access the device's 'seq' member directly. This makes it harder to change the meaning of that member. Change access to go through a function instead. The drivers/i2c/lpc32xx_i2c.c file is left unchanged for now. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
caa4daa2 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename 'platdata' variables to just 'plat' We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
284d062e |
|
09-Sep-2020 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
pci: add a few ARI related defines Add a few defines related to PCI ARI configuration. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
51eeae91 |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add VF BAR map support for Enhanced Allocation Makes dm_pci_map_bar API available to map BAR for Virtual function PCI devices which support Enhanced Allocation. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> |
#
b8852dcf |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add support for Single-Root I/O Virtualization SR-IOV - Single Root I/O Virtualization PF - Physical Function VF - Virtual Function If SR-IOV capability is present, use it to initialize Virtual Function PCI device instances. pci_sriov_init function will read SR-IOV registers to create VF devices under the PF PCI device and also bind driver if available. This function needs to be invoked from Physical function device driver which expects VF device support, creating minimal impact on existing framework. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> |
#
e0024741 |
|
23-Jul-2020 |
Stefan Roese <sr@denx.de> |
pci: pci-uclass: Dynamically allocate the PCI regions Instead of using a fixed length pre-allocated array of regions, this patch moves to dynamically allocating the regions based on the number of available regions plus the necessary regions for DRAM banks. Since MAX_PCI_REGIONS is not needed any more, its removed completely with this patch. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Thierry Reding <treding@nvidia.com> Cc: Marek Vasut <marek.vasut+renesas@gmail.com> |
#
143eb5b1 |
|
12-May-2020 |
Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
drivers: pci: add api to get dma regions Add api to get dma regions. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com> |
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com> |
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com> |
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
7d994067 |
|
23-Apr-2019 |
Tom Rini <trini@konsulko.com> |
Merge tag 'pull-24apr19' of git://git.denx.de/u-boot-dm Various minor sandbox iumprovements Fixes for tracing with sandbox Refactoring for boot_get_fdt()
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
a8c5f8d3 |
|
15-Oct-2018 |
Bin Meng <bmeng.cn@gmail.com> |
dm: pci: Add APIs to find next capability and extended capability This introduces two new APIs dm_pci_find_next_capability() and dm_pci_find_next_ext_capability() to get PCI capability address and PCI express extended capability address for a given PCI device starting from a given offset. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
dac01fd8 |
|
03-Aug-2018 |
Bin Meng <bmeng.cn@gmail.com> |
dm: pci: Add APIs to find capability and extended capability This introduces two new APIs dm_pci_find_capability() and dm_pci_find_ext_capability() to get PCI capability address and PCI express extended capability address for a given PCI device. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
5d544f96 |
|
03-Aug-2018 |
Bin Meng <bmeng.cn@gmail.com> |
pci: Add all known capability and extended capability ids Currently we don't have a complete list of capability and extended capability ids. This adds them. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
4345998a |
|
03-Aug-2018 |
Bin Meng <bmeng.cn@gmail.com> |
pci: sandbox: Support dynamically binding device driver At present all emulated sandbox pci devices must be present in the device tree in order to be used. The real world pci uclass driver supports pci device driver matching, and we should add such support on sandbox too. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
01259c93 |
|
03-Aug-2018 |
Bin Meng <bmeng.cn@gmail.com> |
pci: Remove 440ep-specific macros These macros should not be put in the generic pci.h header file. Since they are not referenced anywhere, remove them completely. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
5ce9aca8 |
|
14-May-2018 |
Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi> |
PCI: Document pciauto_region_allocate() Add a doc comment for pciauto_region_allocate(). Signed-off-by: Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
d71975ae |
|
14-May-2018 |
Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi> |
PCI: autoconfig: Don't allocate 64-bit addresses to 32-bit only resources Currently, if we happen to allocate an address requiring 64 bits to a device only supporting 32-bit BARs, the address eventually gets silently truncated to 32 bits. Avoid this by adding a new flag to pciauto_region_allocate() to bail out in such situations. Signed-off-by: Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
83d290c5 |
|
06-May-2018 |
Tom Rini <trini@konsulko.com> |
SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com> |
#
ed68ccbf |
|
13-Mar-2018 |
Stefan Roese <sr@denx.de> |
pci: Remove unused ppc4xx variable from struct pci_controller ppc4xx support was removed some time ago. Lets remove the now unused "pci_fb" variable from "struct pci_controller" as well. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Simon Glass <sjg@chromium.org> |
#
badb9922 |
|
19-Sep-2017 |
Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi> |
pci: Add helper for implementing memory-mapped config space accesses This sort of pattern for implementing memory-mapped PCI config space accesses appears in U-Boot twice already, and a third user is coming up. So add helper functions to avoid code duplication, similar to how Linux has pci_generic_config_write and pci_generic_config_read. Signed-off-by: Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
6ecbe137 |
|
12-May-2017 |
Tim Harvey <tharvey@gateworks.com> |
drivers: pci: imx: add imx_pcie_remove function There is no dedicated reset signal wired up for the MX6QDL thus if the bootloader enables the link we need some special handling to get the core back into a state where it is safe to touch it for configuration. While there has been some special handling in the Linux kernel to do this, it was removed in 4.11 thus we need to do it properly in the bootloader and therefore without this if you enable PCI in the bootloader you will hang while booting the 4.11 kernel. This puts the PCIe controller back into a safe state for the kernel driver before launching the kernel. Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com> Tested-by: Peter Senna Tschudin <peter.senna@collabora.com> |
#
eeb5b1ad |
|
10-Mar-2016 |
Stuart Yoder <stuart.yoder@nxp.com> |
pci: make pci_get_hose_head() available to external users Put pci_get_hose_head() prototype in header so it is available to external users, allowing them to find and iterate over all pci controllers. Signed-off-by: Stuart Yoder <stuart.yoder@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
4974a6ff |
|
06-Mar-2016 |
Simon Glass <sjg@chromium.org> |
pci: Correct a few comments and nits Two comments are missing a parameter and there is an extra blank line. Also two of the region access macros are misnamed. Correct these problems. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
319dba1f |
|
06-Mar-2016 |
Simon Glass <sjg@chromium.org> |
pci: Add functions to update PCI configuration registers It is common to read a config register value, clear and set some bits, then write back the updated value. Add functions to do this in one step, for convenience. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
308143ef |
|
02-Feb-2016 |
Bin Meng <bmeng.cn@gmail.com> |
dm: pci: Add missing forward declarations When CONFIG_DM_PCI_COMPAT is not on, there is only a forward declaration for pci_write_config32(). Add other missing ones. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
9d731c82 |
|
18-Jan-2016 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to write a BAR Add a driver-model version of the pci_write_bar32 function so that this is supported in the new API. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
7e78b9ef |
|
29-Nov-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Switch to DM API for PCI address mapping We should use the new address mapping functions unless we are in compatibility mode. Disable the old functions by default. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
21d1fe7e |
|
29-Nov-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add driver model API functions for address mapping At present the PCI address map functions use the old API. Add new functions for this so that drivers can be converted. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
bab17cf1 |
|
29-Nov-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR Add a driver-model function for reading the PCI BAR from a device. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
a0eb8356 |
|
29-Nov-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a driver-model version of pci_find_class() Add a function which scans the driver model device information rather than scanning the PCI bus again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> |
#
5c0bf647 |
|
29-Nov-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a driver-model version of pci_find_device() Add a function which scans the driver model device information rather than scanning the PCI bus again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> |
#
5e23b8b4 |
|
29-Nov-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Use driver model PCI API in auto-config At present we are using legacy functions even in the auto-configuration code used by driver model. Add a new pci_auto.c version which uses the correct API. Create a new pci_internal.h header to hold functions that are used within the PCI subsystem, but are not exported to other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> |
#
f3f1faef |
|
29-Nov-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a dm_ prefix to pci_bus_find_bdf() Most driver model PCI functions have a dm_ prefix. At some point, when the old code is converted to driver model and the old functions are removed, we will drop that prefix. For consistency, we should use the dm_ prefix for all driver model functions. Update pci_bus_find_bdf() accordingly. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
21ccce1b |
|
29-Nov-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a dm_ prefix to pci_get_bdf() Most driver model PCI functions have a dm_ prefix. At some point, when the old code is converted to driver model and the old functions are removed, we will drop that prefix. For consistency, we should use the dm_ prefix for all driver model functions. Update pci_get_bdf() accordingly. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
3ba5f74a |
|
26-Nov-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Disable PCI compatibility functions by default We eventually need to drop the compatibility functions for driver model. As a first step, create a configuration option to enable them and hide them when the option is disabled. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
54fe7b1c |
|
26-Nov-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a comment about how to find struct pci_controller With driver mode, struct pci_controller is stored as uclass-private data. Add a comment to that effect. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
f9260336 |
|
19-Nov-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to find the regions for a PCI bus This function looks up the controller and returns a pointer to each region type. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Stephen Warren <swarren@nvidia.com> Tested-by: Stephen Warren <swarren@nvidia.com> |
#
9f60fb0d |
|
19-Nov-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to get the controller for a bus A PCI bus may be a bridge device where the controller is the bridge's parent. Add a function to return the controller device, given a PCI device. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Stephen Warren <swarren@nvidia.com> Tested-by: Stephen Warren <swarren@nvidia.com> |
#
9289db6c |
|
19-Nov-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add functions to emulate 8- and 16-bit access Provide a few functions to support using 32-bit access to emulate 8- and 16-bit access. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Stephen Warren <swarren@nvidia.com> Tested-by: Stephen Warren <swarren@nvidia.com> |
#
bcbe3d15 |
|
28-Sep-2015 |
Simon Glass <sjg@chromium.org> |
dm: Rename dev_get_parentdata() to dev_get_parent_priv() The current name is inconsistent with other driver model data access functions. Rename it and fix up all users. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Joe Hershberger <joe.hershberger@ni.com> |
#
dc5740df |
|
22-Aug-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a comment to help find pci_hose_read_config_byte, etc. These functions are defined by macros so do not show up with grep. Add a comment to help. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
76c3fbcd |
|
10-Aug-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a way to iterate through all PCI devices These functions allow iteration through all PCI devices including bridges. The children of each PCI bus are returned in turn. This can be useful for configuring, checking or enumerating all the devices. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
66afb4ed |
|
10-Aug-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Provide friendly config access functions At present there are no PCI functions which allow access to PCI configuration using a struct udevice. This is a sad situation for driver model as it makes use of PCI harder. Add these functions. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
5f48d798 |
|
27-Jul-2015 |
Simon Glass <sjg@chromium.org> |
pci: Add a constant for an invalid interrupt Rather than using 0xff in the code, add a constant. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
ed5b580b |
|
09-Jul-2015 |
Minghuan Lian <Minghuan.Lian@freescale.com> |
drivers/pci: Add function to find an extended capability PCIe extends device's configuration space to 4k and provides extended capability. The patch adds function to find them. The code is ported from Linux PCIe driver. Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
4b515e4f |
|
06-Jul-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to get the BDF for a device It is useful to be able to find the full PCI address (bus, device and function) for a PCI device. Add a function to provide this. Adjust the existing code to use this. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
aba92962 |
|
06-Jul-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add support for PCI driver matching At present all PCI devices must be present in the device tree in order to be used. Many or most PCI devices don't require any configuration other than that which is done automatically by U-Boot. It is inefficent to add a node with nothing but a compatible string in order to get a device working. Add a mechanism whereby PCI drivers can be declared along with the device parameters they support (vendor/device/class). When no suitable driver is found in the device tree the list of such devices is consulted to determine the correct driver. If this also fails, then a generic driver is used as before. The mechanism used is very similar to that provided by Linux and the header file defintions are copied from Linux 4.1. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Joe Hershberger <joe.hershberger@ni.com> |
#
6c89663c |
|
07-Jul-2015 |
Bin Meng <bmeng.cn@gmail.com> |
pci: Configure expansion ROM during auto config process Currently PCI expansion ROM address is assigned by a call to pciauto_setup_rom() outside of the pci auto config process. This does not work when expansion ROM is on a device behind PCI bridge where bridge's memory limit register was already programmed to a value that does not cover the newly assigned expansion ROM address. To fix this, we should configure the ROM address during the auto config process. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Acked-by: Simon Glass <sjg@chromium.org> |
#
aec241df |
|
07-Jun-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Use the correct hose when configuring devices Only the PCI controller has access to the PCI region information. Make sure to use the controller (rather than any attached bridges) when configuring devices. This corrects a failure to scan and configure devices when driver model is enabled for PCI. Also add a comment to explain the problem. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
36d0d3b4 |
|
05-Mar-2015 |
Simon Glass <sjg@chromium.org> |
dm: sandbox: pci: Add a PCI emulation uclass Since sandbox does not have real devices (unless it borrows those from the host) it must use emulations. Provide a uclass which permits PCI operations to be passed through to an emulation device. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
ff3e077b |
|
05-Mar-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a uclass for PCI Add a uclass for PCI controllers and a generic one for PCI devices. Adjust the 'pci' command and the existing PCI support to work with this new uclass. Keep most of the compatibility code in a separate file so that it can be removed one day. TODO: Add more header file comments to the new parts of pci.h Signed-off-by: Simon Glass <sjg@chromium.org> |
#
aab6724c |
|
05-Mar-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move common PCI functions into their own file Driver model will share many functions with the existing PCI implementation. Move these into their own file to avoid duplication and confusion. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
250e039d |
|
27-Jan-2015 |
Simon Glass <sjg@chromium.org> |
pci: Add a function to find a device by class There is an existing function prototype in the header file but it is not implemented. Implement something similar. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
4a2708a0 |
|
14-Jan-2015 |
Simon Glass <sjg@chromium.org> |
x86: Access the VGA ROM when needed Add code to the generic pci_rom file to access the VGA ROM in PCI space when needed. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
d622ac39 |
|
15-Dec-2014 |
Masahiro Yamada <yamada.m@jp.panasonic.com> |
powerpc: mpc824x: remove MPC824X cpu support All the MPC824X boards are still non-generic boards: A3000, CPC45, CU824, eXalion, MVBLUE, MUSENKI, Sandpoint824x, utx8245 Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Josef Wagner <Wagner@Microsys.de> Cc: Torsten Demke <torsten.demke@fci.com> Cc: Jim Thompson <jim@musenki.com> Cc: Greg Allen <gallen@arlut.utexas.edu> |
#
e8a552eb |
|
14-Nov-2014 |
Simon Glass <sjg@chromium.org> |
pci: Add functions to read and write a BAR address Some PCI functions cannot be auto-configured. Add a function to set up a fixed BAR which can be used in these situations. Also add a function to read the current address of a BAR. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
4efe52bf |
|
12-Nov-2014 |
Thierry Reding <treding@nvidia.com> |
pci: Honour pci_skip_dev() When enumerating devices, honour the pci_skip_dev() function. This can be used by PCI controller drivers to restrict which devices will be probed. This is required by the NVIDIA Tegra PCIe controller driver, which will fail with a data abort exception if an access is attempted to a device number larger than 0 outside of bus 0. pci_skip_dev() is therefore implemented to prevent any such accesses. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Simon Glass <sjg@chromium.org> |
#
0991866c |
|
07-Aug-2014 |
Tim Harvey <tharvey@gateworks.com> |
pci: add support for board_pci_fixup_dev function Some board-level drivers may wish to have per-device fixup functions for PCI devices. Signed-off-by: Tim Harvey <tharvey@gateworks.com> |
#
fa5cec03 |
|
08-Nov-2013 |
Paul Burton <paul.burton@mips.com> |
pci.h: allow inclusion in assembly source This patch simply #ifdef's out the C-specific parts of pci.h when it is included by an assembly file. This will allow the macros it contains to be used from assembly source as will be done in a followup commit adding support for more modern MIPS Malta boards. Signed-off-by: Paul Burton <paul.burton@imgtec.com> |
#
287df01e |
|
11-Oct-2013 |
Zhao Qiang <B45475@freescale.com> |
PCIe:change the method to get the address of a requested capability in configuration space. Previously, the address of a requested capability is define like that "#define PCI_DCR 0x78" But, the addresses of capabilities is different with regard to PCIe revs. So this method is not flexible. Now a function to get the address of a requested capability is added and used. It can get the address dynamically by capability ID. The step of this function: 1. Read Status register in PCIe configuration space to confirm that Capabilities List is valid. 2. Find the address of Capabilities Pointer Register. 3. Find the address of requested capability from the first capability. Signed-off-by: Zhao Qiang <B45475@freescale.com> |
#
7b4e5844 |
|
03-Jul-2013 |
Zang Roy-R61911 <tie-fei.zang@freescale.com> |
powerpc/pcie: add PCIe version 3.x support T4240 PCIe IP is version 3.0 and has some update comparing previous QorIQ products. 1. Move Freescale specific register define to arch/powerpc/include/asm/fsl_pci.h and update the register offset define for T4240. 2. add the status/control register define use status/control register to judge the link status 3. The original code uses 'Programming Interface' field to judge if PCIE is EP or RC mode, however, T4240 does not support this functionality. According to PCIE specification, 'Header Type' offset 0x0e is used to indicate header type, so for PCIE controller, the patch changes code to use 'Header Type' field to identify if the PCIE is RC or EP mode. This patch fixes the PCIe card link up issue on T4240QDS. Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com> |
#
1a459660 |
|
08-Jul-2013 |
Wolfgang Denk <wd@denx.de> |
Add GPL-2.0+ SPDX-License-Identifier to source files Signed-off-by: Wolfgang Denk <wd@denx.de> [trini: Fixup common/cmd_io.c] Signed-off-by: Tom Rini <trini@ti.com> |
#
bc3442aa |
|
11-Jun-2013 |
Simon Glass <sjg@chromium.org> |
pci: Convert extern inline functions to static inline I am not sure of the meaning of extern inline, but this gives errors when building with function instrumenting enabled. Change these functions to static inline. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
842033e6 |
|
30-May-2013 |
Gabor Juhos <juhosg@openwrt.org> |
pci: introduce CONFIG_PCI_INDIRECT_BRIDGE option The pci_indirect.c file is always compiled when CONFIG_PCI is defined although the indirect PCI bridge support is not needed by every board. Introduce a new CONFIG_PCI_INDIRECT_BRIDGE config option and only compile indirect PCI bridge support if this options is enabled. Also add the new option into the configuration files of the boards which needs that. Compile tested for powerpc, x86, arm and nds32. MAKEALL results: powerpc: --------------------- SUMMARY ---------------------------- Boards compiled: 641 Boards with warnings but no errors: 2 ( ELPPC MPC8323ERDB ) ---------------------------------------------------------- Note: the warnings for ELPPC and MPC8323ERDB are present even without the actual patch. x86: --------------------- SUMMARY ---------------------------- Boards compiled: 1 ---------------------------------------------------------- arm: --------------------- SUMMARY ---------------------------- Boards compiled: 311 ---------------------------------------------------------- nds32: --------------------- SUMMARY ---------------------------- Boards compiled: 3 ---------------------------------------------------------- Cc: Tom Rini <trini@ti.com> Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com> Signed-off-by: Gabor Juhos <juhosg@openwrt.org> |
#
55ae10f8 |
|
20-Oct-2012 |
Bill Richardson <wfrichar@chromium.org> |
x86: gpio: Add GPIO driver for Intel ICH6 and later. Implement <asm-generic/gpio.h> functions for Intel ICH6 and later. Only GPIOs 0-31 are handled by this code. Signed-off-by: Bill Richardson <wfrichar@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org> |
#
a3a70725 |
|
24-Mar-2012 |
Linus Walleij <linus.walleij@linaro.org> |
pci: declare pciauto functions in header The FSL PCI driver uses local prototypes for pciauto_[pre|post]scan_setup_bridge(), this does not seem right, so move them to the <pci.h> file. Fixed a small extern declaration too, this is harmless but distracts the view since all other prototypes are explicitly external. Signed-off-by: Linus Walleij <linus.walleij@linaro.org> |
#
a1e47b66 |
|
03-Mar-2012 |
Linus Walleij <linus.walleij@linaro.org> |
pci: move pciauto_config_init() to pci.h Fixing build regressions for the Integrator I get find that a few boards try to work around the missing declaration of pciauto_config_init() by declaring it in the local scope. This does not make sense when the sibling functions are in <pci.h> so move the function to the header, ridding the build error in the Integrator and getting rid of the local declarations here and there. Reported-by: Wolfgang Denk <wd@denx.de> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> |
#
b03a466d |
|
01-Feb-2011 |
Prabhakar Kushwaha <prabhakar@freescale.com> |
powerpc/85xx: Handle PCIe initialization requires for P1021 class SoCs The P1011, P1012, P1015, P1016, P1020, P1021, P1024, & P1025 SoCs require that we initialize the SERDES registers if the lanes are configured for PCIe. Additionally these devices PCIe controller do not support ASPM and we have to explicitly disable it. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
10fa8d7c |
|
19-Jan-2011 |
Leo Liu <liucai.lfn@gmail.com> |
mpc83xx: fix pcie configuration space read/write This patch fix a problem for the pcie enumeration when the mpc83xx pcie controller is connected with switch or we use both of the two pcie controller. Signed-off-by: Leo Liu <liucai.lfn@gmail.com> fix codingstyle and compiler warning: 'pcie_priv' defined but not used Signed-off-by: Kim Phillips <kim.phillips@freescale.com> |
#
3a0e3c27 |
|
17-Dec-2010 |
Kumar Gala <galak@kernel.crashing.org> |
powerpc/fsl-pci: Determine pci_controller based on cfg addr for dts fixup Previously we passed in a specifically named struct pci_controller to determine if we had setup the particular PCI bus. Now we can search for the struct so we dont have to depend on the name or the struct being statically allocated. Introduced new find_hose_by_cfg_addr() to get back a pci_controller struct back by searching for it means we can do things like dynamically allocate them or not have to expose the static structures to all users. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Wolfgang Denk <wd@denx.de> |
#
983eb9d1 |
|
29-Oct-2010 |
Peter Tyser <ptyser@xes-inc.com> |
pci: Clean up PCI info when CONFIG_PCI_SCAN_SHOW This change does the following: - Removes the printing of the PCI interrupt line value. This is normally set to 0 by U-Boot on bootup and is rarely used during everyday operation. - Prints out the PCI function number of a device. Previously a device with multiple functions would be printed identically 2 times, which is generally confusing. For example, on an Intel 2 port gigabit Ethernet card the following was displayed: ... 04 01 8086 1010 0200 00 04 01 8086 1010 0200 00 ... - Prints a text description of each device's PCI class instead of the raw PCI class code. The textual description makes it much easier to determine what devices are installed on a PCI bus. - Changes the general formatting of the PCI device output. Previous output: PCIE1: connected as Root Complex 04 01 8086 1010 0200 00 04 01 8086 1010 0200 00 03 00 10b5 8112 0604 00 02 01 10b5 8518 0604 00 02 02 10b5 8518 0604 00 08 00 1957 0040 0b20 00 07 00 10b5 8518 0604 00 09 00 10b5 8112 0604 00 07 01 10b5 8518 0604 00 07 02 10b5 8518 0604 00 06 00 10b5 8518 0604 00 02 03 10b5 8518 0604 00 01 00 10b5 8518 0604 00 PCIE1: Bus 00 - 0b PCIE2: connected as Root Complex 0d 00 1957 0040 0b20 00 PCIE2: Bus 0c - 0d Updated output: PCIE1: connected as Root Complex 04:01.0 - 8086:1010 - Network controller 04:01.1 - 8086:1010 - Network controller 03:00.0 - 10b5:8112 - Bridge device 02:01.0 - 10b5:8518 - Bridge device 02:02.0 - 10b5:8518 - Bridge device 08:00.0 - 1957:0040 - Processor 07:00.0 - 10b5:8518 - Bridge device 09:00.0 - 10b5:8112 - Bridge device 07:01.0 - 10b5:8518 - Bridge device 07:02.0 - 10b5:8518 - Bridge device 06:00.0 - 10b5:8518 - Bridge device 02:03.0 - 10b5:8518 - Bridge device 01:00.0 - 10b5:8518 - Bridge device PCIE1: Bus 00 - 0b PCIE2: connected as Root Complex 0d:00.0 - 1957:0040 - Processor PCIE2: Bus 0c - 0d Signed-off-by: Peter Tyser <ptyser@xes-inc.com> |
#
8295b944 |
|
05-Aug-2009 |
Kumar Gala <galak@kernel.crashing.org> |
pci/fsl_pci_init: Use PCIe capability to determine if controller is PCIe Change the code to use the PCIe capabilities register to determine if we are a PCIe controller or not. Additionally cleaned up some white space and formatting in the file. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
cc2a8c77 |
|
19-Feb-2009 |
Anton Vorontsov <avorontsov@ru.mvista.com> |
PCI: Add pci_last_busno() helper This is just a handy routine that reports last PCI busno: we walk down all the hoses and return last hose's last_busno. Will be used by PCI/PCIe initialization code. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com> |
#
6e61fae4 |
|
03-Feb-2009 |
Becky Bruce <beckyb@kernel.crashing.org> |
drivers/pci: Create pci_map_bar function It is no longer always true that the pci bus address can be used as the virtual address for pci accesses. pci_map_bar() is created to return the virtual address for a pci region. Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org> |
#
ff4e66e9 |
|
06-Feb-2009 |
Kumar Gala <galak@kernel.crashing.org> |
pci: Rename PCI_REGION_MEMORY to PCI_REGION_SYS_MEMORY for clarity The PCI_REGION_MEMORY and PCI_REGION_MEM are a bit to similar and can be confusing when reading the code. Rename PCI_REGION_MEMORY to PCI_REGION_SYS_MEMORY to clarify its used for system memory mapping purposes. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
fd6646c0 |
|
07-Jan-2009 |
Anton Vorontsov <avorontsov@ru.mvista.com> |
mpc83xx: Add support for MPC83xx PCI-E controllers This patch adds support for MPC83xx PCI-E controllers in Root Complex mode. The patch is based on Tony Li and Dave Liu work[1]. Though unlike the original patch, by default we don't register PCI-E buses for use in U-Boot, we only configure the controllers for future use in other OSes (Linux). This is done because we don't have enough of spare BATs to map all the PCI-E regions. To actually use PCI-E in U-Boot, users should explicitly define CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES symbol in the board file. And only then U-Boot will able to access PCI-E, but at the cost of disabled address translation. [1] http://lists.denx.de/pipermail/u-boot/2008-January/027630.html Signed-off-by: Tony Li <tony.li@freescale.com> Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Acked-by: Dave Liu <daveliu@freescale.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com> |
#
30e76d5e |
|
21-Oct-2008 |
Kumar Gala <galak@kernel.crashing.org> |
pci: Allow for PCI addresses to be 64-bit PCI bus is inherently 64-bit. While not all system require access to the full 64-bit PCI address range some do. This allows those systems to enable the full PCI address width via CONFIG_SYS_PCI_64BIT. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Andrew Fleming-AFLEMING <afleming@freescale.com> Acked-by: Wolfgang Denk <wd@denx.de> |
#
36f32675 |
|
07-May-2008 |
Becky Bruce <bgill@freescale.com> |
Update pci code to use phys_addr_t Physical addrs need to be represented by phys_addr_t, not unsigned long. Otherwise, systems that use CONFIG_PHYS_64BIT are going to fail mightily. Signed-off-by: Becky Bruce <becky.bruce@freescale.com> |
#
63cec581 |
|
02-Aug-2007 |
Ed Swarthout <Ed.Swarthout@freescale.com> |
Make MPC8641's PCI/PCI-E driver a common driver for many FSL parts. All of the PCI/PCI-Express driver and initialization code that was in the MPC8641HPCN port has now been moved into the common drivers/fsl_pci_init.c. In a subsequent patch, this will be utilized by the 85xx ports as well. Common PCI-E IMMAP register blocks for FSL 85xx/86xx are added. Also enable the second PCI-Express controller on 8641 by getting its BATS and CFG_ setup right. Fixed a u16 vendor compiler warning in AHCI driver too. Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com> Signed-off-by: Zhang Wei <wei.zhang@freescale.com> Signed-off-by: Jon Loeliger <jdl@freescale.com> |
#
13a7fcdf |
|
19-Oct-2006 |
Jon Loeliger <jdl@freescale.com> |
* Fix a bunch of compiler warnings for gcc 4.0 Signed-off-by: Matthew McClintock <msm@freescale.com> |
#
f0e6f57f |
|
28-Jun-2006 |
Matthew McClintock <msm@freescale.com> |
* Added PCI-X #defines for PCI-X initialization Patch by Andy Fleming on 17-Mar-2006 Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
7b230f61 |
|
12-Mar-2006 |
Wolfgang Denk <wd@pollux.denx.de> |
Merge with git://git.kernel.org/pub/scm/boot/u-boot/u-boot.git#pci
|
#
993a2275 |
|
12-Mar-2006 |
Wolfgang Denk <wd@pollux.denx.de> |
Fix bad declaration on pci_cfgfunc_nothing Patch by Sam Song, 19 Jun 2005 |
#
a179012e |
|
11-Jan-2006 |
Kumar Gala <galak@kernel.crashing.org> |
Added support for PCI prefetchable region and BARs If a host controller sets up a region as prefetchable and a device's BAR denotes it as prefetchable, allocate the BAR into the prefetch region. If a BAR is prefetchable and no prefetchable region has been setup by the controller we fall back to allocating the BAR into the normally memory region. Patch by Kumar Gala 11 Jan 2006 |
#
c157d8e2 |
|
01-Aug-2005 |
Stefan Roese <sr@denx.de> |
Add support for AMCC PPC440EP/GR eval boards Yosemite and Yellowstone. Patch by Steven Blakeslee, 27 Jul 2005 |
#
7a8e9bed |
|
31-May-2003 |
Wolfgang Denk <wdenk> |
* Patch by Marc Singer, 29 May 2003: Fixed rarp boot method for IA32 and other little-endian CPUs. * Patch by Marc Singer, 28 May 2003: Added port I/O commands. * Patch by Matthew McClintock, 28 May 2003 - cpu/mpc824x/start.S: fix relocation code when booting from RAM - minor patches for utx8245 * Patch by Daniel Engstr�m, 28 May 2003: x86 update * Patch by Dave Ellis, 9 May 2003 + 27 May 2003: add nand flash support to SXNI855T configuration fix/extend nand flash support: - fix 'nand erase' command so does not erase bad blocks - fix 'nand write' command so does not write to bad blocks - fix nand_probe() so handles no flash detected properly - add doc/README.nand - add .jffs2 and .oob options to nand read/write - add 'nand bad' command to list bad blocks - add 'clean' option to 'nand erase' to write JFFS2 clean markers - make NAND read/write faster * Patch by Rune Torgersen, 23 May 2003: Update for MPC8266ADS board |
#
c7de829c |
|
19-Nov-2002 |
Wolfgang Denk <wdenk> |
* Patch by Thomas Frieden, 13 Nov 2002: Add code for AmigaOne board (preliminary merge to U-Boot, still WIP) * Patch by Jon Diekema, 12 Nov 2002: - Adding URL for IEEE OUI lookup - Making the autoboot #defines dependent on CONFIG_AUTOBOOT_KEYED being defined. - In the CONFIG_EXTRA_ENV_SETTINGS #define, the root-on-initrd and root-on-nfs macros are designed to switch how the default boot method gets defined. |
#
c609719b |
|
02-Nov-2002 |
Wolfgang Denk <wdenk> |
Initial revision |
#
8b85dfc6 |
|
16-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: Avoid accessing seq directly At present various drivers etc. access the device's 'seq' member directly. This makes it harder to change the meaning of that member. Change access to go through a function instead. The drivers/i2c/lpc32xx_i2c.c file is left unchanged for now. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
caa4daa2 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename 'platdata' variables to just 'plat' We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
284d062e |
|
09-Sep-2020 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
pci: add a few ARI related defines Add a few defines related to PCI ARI configuration. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
51eeae91 |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add VF BAR map support for Enhanced Allocation Makes dm_pci_map_bar API available to map BAR for Virtual function PCI devices which support Enhanced Allocation. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
b8852dcf |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add support for Single-Root I/O Virtualization SR-IOV - Single Root I/O Virtualization PF - Physical Function VF - Virtual Function If SR-IOV capability is present, use it to initialize Virtual Function PCI device instances. pci_sriov_init function will read SR-IOV registers to create VF devices under the PF PCI device and also bind driver if available. This function needs to be invoked from Physical function device driver which expects VF device support, creating minimal impact on existing framework. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
e0024741 |
|
23-Jul-2020 |
Stefan Roese <sr@denx.de> |
pci: pci-uclass: Dynamically allocate the PCI regions Instead of using a fixed length pre-allocated array of regions, this patch moves to dynamically allocating the regions based on the number of available regions plus the necessary regions for DRAM banks. Since MAX_PCI_REGIONS is not needed any more, its removed completely with this patch. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Thierry Reding <treding@nvidia.com> Cc: Marek Vasut <marek.vasut+renesas@gmail.com>
|
#
143eb5b1 |
|
12-May-2020 |
Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
drivers: pci: add api to get dma regions Add api to get dma regions. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8b85dfc6 |
|
16-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: Avoid accessing seq directly At present various drivers etc. access the device's 'seq' member directly. This makes it harder to change the meaning of that member. Change access to go through a function instead. The drivers/i2c/lpc32xx_i2c.c file is left unchanged for now. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
caa4daa2 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename 'platdata' variables to just 'plat' We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
284d062e |
|
09-Sep-2020 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
pci: add a few ARI related defines Add a few defines related to PCI ARI configuration. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
51eeae91 |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add VF BAR map support for Enhanced Allocation Makes dm_pci_map_bar API available to map BAR for Virtual function PCI devices which support Enhanced Allocation. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
b8852dcf |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add support for Single-Root I/O Virtualization SR-IOV - Single Root I/O Virtualization PF - Physical Function VF - Virtual Function If SR-IOV capability is present, use it to initialize Virtual Function PCI device instances. pci_sriov_init function will read SR-IOV registers to create VF devices under the PF PCI device and also bind driver if available. This function needs to be invoked from Physical function device driver which expects VF device support, creating minimal impact on existing framework. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
e0024741 |
|
23-Jul-2020 |
Stefan Roese <sr@denx.de> |
pci: pci-uclass: Dynamically allocate the PCI regions Instead of using a fixed length pre-allocated array of regions, this patch moves to dynamically allocating the regions based on the number of available regions plus the necessary regions for DRAM banks. Since MAX_PCI_REGIONS is not needed any more, its removed completely with this patch. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Thierry Reding <treding@nvidia.com> Cc: Marek Vasut <marek.vasut+renesas@gmail.com>
|
#
143eb5b1 |
|
12-May-2020 |
Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
drivers: pci: add api to get dma regions Add api to get dma regions. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8b85dfc6 |
|
16-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: Avoid accessing seq directly At present various drivers etc. access the device's 'seq' member directly. This makes it harder to change the meaning of that member. Change access to go through a function instead. The drivers/i2c/lpc32xx_i2c.c file is left unchanged for now. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
caa4daa2 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename 'platdata' variables to just 'plat' We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
284d062e |
|
09-Sep-2020 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
pci: add a few ARI related defines Add a few defines related to PCI ARI configuration. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
51eeae91 |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add VF BAR map support for Enhanced Allocation Makes dm_pci_map_bar API available to map BAR for Virtual function PCI devices which support Enhanced Allocation. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
b8852dcf |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add support for Single-Root I/O Virtualization SR-IOV - Single Root I/O Virtualization PF - Physical Function VF - Virtual Function If SR-IOV capability is present, use it to initialize Virtual Function PCI device instances. pci_sriov_init function will read SR-IOV registers to create VF devices under the PF PCI device and also bind driver if available. This function needs to be invoked from Physical function device driver which expects VF device support, creating minimal impact on existing framework. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
e0024741 |
|
23-Jul-2020 |
Stefan Roese <sr@denx.de> |
pci: pci-uclass: Dynamically allocate the PCI regions Instead of using a fixed length pre-allocated array of regions, this patch moves to dynamically allocating the regions based on the number of available regions plus the necessary regions for DRAM banks. Since MAX_PCI_REGIONS is not needed any more, its removed completely with this patch. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Thierry Reding <treding@nvidia.com> Cc: Marek Vasut <marek.vasut+renesas@gmail.com>
|
#
143eb5b1 |
|
12-May-2020 |
Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
drivers: pci: add api to get dma regions Add api to get dma regions. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8b85dfc6 |
|
16-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: Avoid accessing seq directly At present various drivers etc. access the device's 'seq' member directly. This makes it harder to change the meaning of that member. Change access to go through a function instead. The drivers/i2c/lpc32xx_i2c.c file is left unchanged for now. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
caa4daa2 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename 'platdata' variables to just 'plat' We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
284d062e |
|
09-Sep-2020 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
pci: add a few ARI related defines Add a few defines related to PCI ARI configuration. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
51eeae91 |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add VF BAR map support for Enhanced Allocation Makes dm_pci_map_bar API available to map BAR for Virtual function PCI devices which support Enhanced Allocation. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
b8852dcf |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add support for Single-Root I/O Virtualization SR-IOV - Single Root I/O Virtualization PF - Physical Function VF - Virtual Function If SR-IOV capability is present, use it to initialize Virtual Function PCI device instances. pci_sriov_init function will read SR-IOV registers to create VF devices under the PF PCI device and also bind driver if available. This function needs to be invoked from Physical function device driver which expects VF device support, creating minimal impact on existing framework. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
e0024741 |
|
23-Jul-2020 |
Stefan Roese <sr@denx.de> |
pci: pci-uclass: Dynamically allocate the PCI regions Instead of using a fixed length pre-allocated array of regions, this patch moves to dynamically allocating the regions based on the number of available regions plus the necessary regions for DRAM banks. Since MAX_PCI_REGIONS is not needed any more, its removed completely with this patch. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Thierry Reding <treding@nvidia.com> Cc: Marek Vasut <marek.vasut+renesas@gmail.com>
|
#
143eb5b1 |
|
12-May-2020 |
Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
drivers: pci: add api to get dma regions Add api to get dma regions. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8b85dfc6 |
|
16-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: Avoid accessing seq directly At present various drivers etc. access the device's 'seq' member directly. This makes it harder to change the meaning of that member. Change access to go through a function instead. The drivers/i2c/lpc32xx_i2c.c file is left unchanged for now. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
caa4daa2 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename 'platdata' variables to just 'plat' We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
284d062e |
|
09-Sep-2020 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
pci: add a few ARI related defines Add a few defines related to PCI ARI configuration. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
51eeae91 |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add VF BAR map support for Enhanced Allocation Makes dm_pci_map_bar API available to map BAR for Virtual function PCI devices which support Enhanced Allocation. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
b8852dcf |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add support for Single-Root I/O Virtualization SR-IOV - Single Root I/O Virtualization PF - Physical Function VF - Virtual Function If SR-IOV capability is present, use it to initialize Virtual Function PCI device instances. pci_sriov_init function will read SR-IOV registers to create VF devices under the PF PCI device and also bind driver if available. This function needs to be invoked from Physical function device driver which expects VF device support, creating minimal impact on existing framework. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
e0024741 |
|
23-Jul-2020 |
Stefan Roese <sr@denx.de> |
pci: pci-uclass: Dynamically allocate the PCI regions Instead of using a fixed length pre-allocated array of regions, this patch moves to dynamically allocating the regions based on the number of available regions plus the necessary regions for DRAM banks. Since MAX_PCI_REGIONS is not needed any more, its removed completely with this patch. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Thierry Reding <treding@nvidia.com> Cc: Marek Vasut <marek.vasut+renesas@gmail.com>
|
#
143eb5b1 |
|
12-May-2020 |
Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
drivers: pci: add api to get dma regions Add api to get dma regions. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8b85dfc6 |
|
16-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: Avoid accessing seq directly At present various drivers etc. access the device's 'seq' member directly. This makes it harder to change the meaning of that member. Change access to go through a function instead. The drivers/i2c/lpc32xx_i2c.c file is left unchanged for now. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
caa4daa2 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename 'platdata' variables to just 'plat' We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
284d062e |
|
09-Sep-2020 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
pci: add a few ARI related defines Add a few defines related to PCI ARI configuration. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
51eeae91 |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add VF BAR map support for Enhanced Allocation Makes dm_pci_map_bar API available to map BAR for Virtual function PCI devices which support Enhanced Allocation. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
b8852dcf |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add support for Single-Root I/O Virtualization SR-IOV - Single Root I/O Virtualization PF - Physical Function VF - Virtual Function If SR-IOV capability is present, use it to initialize Virtual Function PCI device instances. pci_sriov_init function will read SR-IOV registers to create VF devices under the PF PCI device and also bind driver if available. This function needs to be invoked from Physical function device driver which expects VF device support, creating minimal impact on existing framework. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
e0024741 |
|
23-Jul-2020 |
Stefan Roese <sr@denx.de> |
pci: pci-uclass: Dynamically allocate the PCI regions Instead of using a fixed length pre-allocated array of regions, this patch moves to dynamically allocating the regions based on the number of available regions plus the necessary regions for DRAM banks. Since MAX_PCI_REGIONS is not needed any more, its removed completely with this patch. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Thierry Reding <treding@nvidia.com> Cc: Marek Vasut <marek.vasut+renesas@gmail.com>
|
#
143eb5b1 |
|
12-May-2020 |
Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
drivers: pci: add api to get dma regions Add api to get dma regions. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8b85dfc6 |
|
16-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: Avoid accessing seq directly At present various drivers etc. access the device's 'seq' member directly. This makes it harder to change the meaning of that member. Change access to go through a function instead. The drivers/i2c/lpc32xx_i2c.c file is left unchanged for now. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
caa4daa2 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename 'platdata' variables to just 'plat' We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
284d062e |
|
09-Sep-2020 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
pci: add a few ARI related defines Add a few defines related to PCI ARI configuration. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
51eeae91 |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add VF BAR map support for Enhanced Allocation Makes dm_pci_map_bar API available to map BAR for Virtual function PCI devices which support Enhanced Allocation. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
b8852dcf |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add support for Single-Root I/O Virtualization SR-IOV - Single Root I/O Virtualization PF - Physical Function VF - Virtual Function If SR-IOV capability is present, use it to initialize Virtual Function PCI device instances. pci_sriov_init function will read SR-IOV registers to create VF devices under the PF PCI device and also bind driver if available. This function needs to be invoked from Physical function device driver which expects VF device support, creating minimal impact on existing framework. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
e0024741 |
|
23-Jul-2020 |
Stefan Roese <sr@denx.de> |
pci: pci-uclass: Dynamically allocate the PCI regions Instead of using a fixed length pre-allocated array of regions, this patch moves to dynamically allocating the regions based on the number of available regions plus the necessary regions for DRAM banks. Since MAX_PCI_REGIONS is not needed any more, its removed completely with this patch. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Thierry Reding <treding@nvidia.com> Cc: Marek Vasut <marek.vasut+renesas@gmail.com>
|
#
143eb5b1 |
|
12-May-2020 |
Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
drivers: pci: add api to get dma regions Add api to get dma regions. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8b85dfc6 |
|
16-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: Avoid accessing seq directly At present various drivers etc. access the device's 'seq' member directly. This makes it harder to change the meaning of that member. Change access to go through a function instead. The drivers/i2c/lpc32xx_i2c.c file is left unchanged for now. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
caa4daa2 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename 'platdata' variables to just 'plat' We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
284d062e |
|
09-Sep-2020 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
pci: add a few ARI related defines Add a few defines related to PCI ARI configuration. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
51eeae91 |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add VF BAR map support for Enhanced Allocation Makes dm_pci_map_bar API available to map BAR for Virtual function PCI devices which support Enhanced Allocation. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
b8852dcf |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add support for Single-Root I/O Virtualization SR-IOV - Single Root I/O Virtualization PF - Physical Function VF - Virtual Function If SR-IOV capability is present, use it to initialize Virtual Function PCI device instances. pci_sriov_init function will read SR-IOV registers to create VF devices under the PF PCI device and also bind driver if available. This function needs to be invoked from Physical function device driver which expects VF device support, creating minimal impact on existing framework. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
e0024741 |
|
23-Jul-2020 |
Stefan Roese <sr@denx.de> |
pci: pci-uclass: Dynamically allocate the PCI regions Instead of using a fixed length pre-allocated array of regions, this patch moves to dynamically allocating the regions based on the number of available regions plus the necessary regions for DRAM banks. Since MAX_PCI_REGIONS is not needed any more, its removed completely with this patch. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Thierry Reding <treding@nvidia.com> Cc: Marek Vasut <marek.vasut+renesas@gmail.com>
|
#
143eb5b1 |
|
12-May-2020 |
Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
drivers: pci: add api to get dma regions Add api to get dma regions. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8b85dfc6 |
|
16-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: Avoid accessing seq directly At present various drivers etc. access the device's 'seq' member directly. This makes it harder to change the meaning of that member. Change access to go through a function instead. The drivers/i2c/lpc32xx_i2c.c file is left unchanged for now. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
caa4daa2 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename 'platdata' variables to just 'plat' We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
284d062e |
|
09-Sep-2020 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
pci: add a few ARI related defines Add a few defines related to PCI ARI configuration. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
51eeae91 |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add VF BAR map support for Enhanced Allocation Makes dm_pci_map_bar API available to map BAR for Virtual function PCI devices which support Enhanced Allocation. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
b8852dcf |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add support for Single-Root I/O Virtualization SR-IOV - Single Root I/O Virtualization PF - Physical Function VF - Virtual Function If SR-IOV capability is present, use it to initialize Virtual Function PCI device instances. pci_sriov_init function will read SR-IOV registers to create VF devices under the PF PCI device and also bind driver if available. This function needs to be invoked from Physical function device driver which expects VF device support, creating minimal impact on existing framework. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
e0024741 |
|
23-Jul-2020 |
Stefan Roese <sr@denx.de> |
pci: pci-uclass: Dynamically allocate the PCI regions Instead of using a fixed length pre-allocated array of regions, this patch moves to dynamically allocating the regions based on the number of available regions plus the necessary regions for DRAM banks. Since MAX_PCI_REGIONS is not needed any more, its removed completely with this patch. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Thierry Reding <treding@nvidia.com> Cc: Marek Vasut <marek.vasut+renesas@gmail.com>
|
#
143eb5b1 |
|
12-May-2020 |
Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
drivers: pci: add api to get dma regions Add api to get dma regions. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8b85dfc6 |
|
16-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: Avoid accessing seq directly At present various drivers etc. access the device's 'seq' member directly. This makes it harder to change the meaning of that member. Change access to go through a function instead. The drivers/i2c/lpc32xx_i2c.c file is left unchanged for now. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
caa4daa2 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename 'platdata' variables to just 'plat' We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
284d062e |
|
09-Sep-2020 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
pci: add a few ARI related defines Add a few defines related to PCI ARI configuration. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
51eeae91 |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add VF BAR map support for Enhanced Allocation Makes dm_pci_map_bar API available to map BAR for Virtual function PCI devices which support Enhanced Allocation. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
b8852dcf |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add support for Single-Root I/O Virtualization SR-IOV - Single Root I/O Virtualization PF - Physical Function VF - Virtual Function If SR-IOV capability is present, use it to initialize Virtual Function PCI device instances. pci_sriov_init function will read SR-IOV registers to create VF devices under the PF PCI device and also bind driver if available. This function needs to be invoked from Physical function device driver which expects VF device support, creating minimal impact on existing framework. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
e0024741 |
|
23-Jul-2020 |
Stefan Roese <sr@denx.de> |
pci: pci-uclass: Dynamically allocate the PCI regions Instead of using a fixed length pre-allocated array of regions, this patch moves to dynamically allocating the regions based on the number of available regions plus the necessary regions for DRAM banks. Since MAX_PCI_REGIONS is not needed any more, its removed completely with this patch. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Thierry Reding <treding@nvidia.com> Cc: Marek Vasut <marek.vasut+renesas@gmail.com>
|
#
143eb5b1 |
|
12-May-2020 |
Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
drivers: pci: add api to get dma regions Add api to get dma regions. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8b85dfc6 |
|
16-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: Avoid accessing seq directly At present various drivers etc. access the device's 'seq' member directly. This makes it harder to change the meaning of that member. Change access to go through a function instead. The drivers/i2c/lpc32xx_i2c.c file is left unchanged for now. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
caa4daa2 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename 'platdata' variables to just 'plat' We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
284d062e |
|
09-Sep-2020 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
pci: add a few ARI related defines Add a few defines related to PCI ARI configuration. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
51eeae91 |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add VF BAR map support for Enhanced Allocation Makes dm_pci_map_bar API available to map BAR for Virtual function PCI devices which support Enhanced Allocation. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
b8852dcf |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add support for Single-Root I/O Virtualization SR-IOV - Single Root I/O Virtualization PF - Physical Function VF - Virtual Function If SR-IOV capability is present, use it to initialize Virtual Function PCI device instances. pci_sriov_init function will read SR-IOV registers to create VF devices under the PF PCI device and also bind driver if available. This function needs to be invoked from Physical function device driver which expects VF device support, creating minimal impact on existing framework. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
e0024741 |
|
23-Jul-2020 |
Stefan Roese <sr@denx.de> |
pci: pci-uclass: Dynamically allocate the PCI regions Instead of using a fixed length pre-allocated array of regions, this patch moves to dynamically allocating the regions based on the number of available regions plus the necessary regions for DRAM banks. Since MAX_PCI_REGIONS is not needed any more, its removed completely with this patch. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Thierry Reding <treding@nvidia.com> Cc: Marek Vasut <marek.vasut+renesas@gmail.com>
|
#
143eb5b1 |
|
12-May-2020 |
Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
drivers: pci: add api to get dma regions Add api to get dma regions. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8b85dfc6 |
|
16-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: Avoid accessing seq directly At present various drivers etc. access the device's 'seq' member directly. This makes it harder to change the meaning of that member. Change access to go through a function instead. The drivers/i2c/lpc32xx_i2c.c file is left unchanged for now. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
caa4daa2 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename 'platdata' variables to just 'plat' We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
284d062e |
|
09-Sep-2020 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
pci: add a few ARI related defines Add a few defines related to PCI ARI configuration. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
51eeae91 |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add VF BAR map support for Enhanced Allocation Makes dm_pci_map_bar API available to map BAR for Virtual function PCI devices which support Enhanced Allocation. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
b8852dcf |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add support for Single-Root I/O Virtualization SR-IOV - Single Root I/O Virtualization PF - Physical Function VF - Virtual Function If SR-IOV capability is present, use it to initialize Virtual Function PCI device instances. pci_sriov_init function will read SR-IOV registers to create VF devices under the PF PCI device and also bind driver if available. This function needs to be invoked from Physical function device driver which expects VF device support, creating minimal impact on existing framework. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
e0024741 |
|
23-Jul-2020 |
Stefan Roese <sr@denx.de> |
pci: pci-uclass: Dynamically allocate the PCI regions Instead of using a fixed length pre-allocated array of regions, this patch moves to dynamically allocating the regions based on the number of available regions plus the necessary regions for DRAM banks. Since MAX_PCI_REGIONS is not needed any more, its removed completely with this patch. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Thierry Reding <treding@nvidia.com> Cc: Marek Vasut <marek.vasut+renesas@gmail.com>
|
#
143eb5b1 |
|
12-May-2020 |
Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
drivers: pci: add api to get dma regions Add api to get dma regions. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8b85dfc6 |
|
16-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: Avoid accessing seq directly At present various drivers etc. access the device's 'seq' member directly. This makes it harder to change the meaning of that member. Change access to go through a function instead. The drivers/i2c/lpc32xx_i2c.c file is left unchanged for now. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
caa4daa2 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename 'platdata' variables to just 'plat' We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
284d062e |
|
09-Sep-2020 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
pci: add a few ARI related defines Add a few defines related to PCI ARI configuration. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
51eeae91 |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add VF BAR map support for Enhanced Allocation Makes dm_pci_map_bar API available to map BAR for Virtual function PCI devices which support Enhanced Allocation. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
b8852dcf |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add support for Single-Root I/O Virtualization SR-IOV - Single Root I/O Virtualization PF - Physical Function VF - Virtual Function If SR-IOV capability is present, use it to initialize Virtual Function PCI device instances. pci_sriov_init function will read SR-IOV registers to create VF devices under the PF PCI device and also bind driver if available. This function needs to be invoked from Physical function device driver which expects VF device support, creating minimal impact on existing framework. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
e0024741 |
|
23-Jul-2020 |
Stefan Roese <sr@denx.de> |
pci: pci-uclass: Dynamically allocate the PCI regions Instead of using a fixed length pre-allocated array of regions, this patch moves to dynamically allocating the regions based on the number of available regions plus the necessary regions for DRAM banks. Since MAX_PCI_REGIONS is not needed any more, its removed completely with this patch. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Thierry Reding <treding@nvidia.com> Cc: Marek Vasut <marek.vasut+renesas@gmail.com>
|
#
143eb5b1 |
|
12-May-2020 |
Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
drivers: pci: add api to get dma regions Add api to get dma regions. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8b85dfc6 |
|
16-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: Avoid accessing seq directly At present various drivers etc. access the device's 'seq' member directly. This makes it harder to change the meaning of that member. Change access to go through a function instead. The drivers/i2c/lpc32xx_i2c.c file is left unchanged for now. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
caa4daa2 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename 'platdata' variables to just 'plat' We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
284d062e |
|
09-Sep-2020 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
pci: add a few ARI related defines Add a few defines related to PCI ARI configuration. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
51eeae91 |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add VF BAR map support for Enhanced Allocation Makes dm_pci_map_bar API available to map BAR for Virtual function PCI devices which support Enhanced Allocation. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
b8852dcf |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add support for Single-Root I/O Virtualization SR-IOV - Single Root I/O Virtualization PF - Physical Function VF - Virtual Function If SR-IOV capability is present, use it to initialize Virtual Function PCI device instances. pci_sriov_init function will read SR-IOV registers to create VF devices under the PF PCI device and also bind driver if available. This function needs to be invoked from Physical function device driver which expects VF device support, creating minimal impact on existing framework. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
e0024741 |
|
23-Jul-2020 |
Stefan Roese <sr@denx.de> |
pci: pci-uclass: Dynamically allocate the PCI regions Instead of using a fixed length pre-allocated array of regions, this patch moves to dynamically allocating the regions based on the number of available regions plus the necessary regions for DRAM banks. Since MAX_PCI_REGIONS is not needed any more, its removed completely with this patch. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Thierry Reding <treding@nvidia.com> Cc: Marek Vasut <marek.vasut+renesas@gmail.com>
|
#
143eb5b1 |
|
12-May-2020 |
Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
drivers: pci: add api to get dma regions Add api to get dma regions. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8b85dfc6 |
|
16-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: Avoid accessing seq directly At present various drivers etc. access the device's 'seq' member directly. This makes it harder to change the meaning of that member. Change access to go through a function instead. The drivers/i2c/lpc32xx_i2c.c file is left unchanged for now. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
caa4daa2 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename 'platdata' variables to just 'plat' We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
284d062e |
|
09-Sep-2020 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
pci: add a few ARI related defines Add a few defines related to PCI ARI configuration. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
51eeae91 |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add VF BAR map support for Enhanced Allocation Makes dm_pci_map_bar API available to map BAR for Virtual function PCI devices which support Enhanced Allocation. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
b8852dcf |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add support for Single-Root I/O Virtualization SR-IOV - Single Root I/O Virtualization PF - Physical Function VF - Virtual Function If SR-IOV capability is present, use it to initialize Virtual Function PCI device instances. pci_sriov_init function will read SR-IOV registers to create VF devices under the PF PCI device and also bind driver if available. This function needs to be invoked from Physical function device driver which expects VF device support, creating minimal impact on existing framework. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
e0024741 |
|
23-Jul-2020 |
Stefan Roese <sr@denx.de> |
pci: pci-uclass: Dynamically allocate the PCI regions Instead of using a fixed length pre-allocated array of regions, this patch moves to dynamically allocating the regions based on the number of available regions plus the necessary regions for DRAM banks. Since MAX_PCI_REGIONS is not needed any more, its removed completely with this patch. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Thierry Reding <treding@nvidia.com> Cc: Marek Vasut <marek.vasut+renesas@gmail.com>
|
#
143eb5b1 |
|
12-May-2020 |
Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
drivers: pci: add api to get dma regions Add api to get dma regions. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8b85dfc6 |
|
16-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: Avoid accessing seq directly At present various drivers etc. access the device's 'seq' member directly. This makes it harder to change the meaning of that member. Change access to go through a function instead. The drivers/i2c/lpc32xx_i2c.c file is left unchanged for now. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
caa4daa2 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename 'platdata' variables to just 'plat' We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
284d062e |
|
09-Sep-2020 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
pci: add a few ARI related defines Add a few defines related to PCI ARI configuration. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
51eeae91 |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add VF BAR map support for Enhanced Allocation Makes dm_pci_map_bar API available to map BAR for Virtual function PCI devices which support Enhanced Allocation. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
b8852dcf |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add support for Single-Root I/O Virtualization SR-IOV - Single Root I/O Virtualization PF - Physical Function VF - Virtual Function If SR-IOV capability is present, use it to initialize Virtual Function PCI device instances. pci_sriov_init function will read SR-IOV registers to create VF devices under the PF PCI device and also bind driver if available. This function needs to be invoked from Physical function device driver which expects VF device support, creating minimal impact on existing framework. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
e0024741 |
|
23-Jul-2020 |
Stefan Roese <sr@denx.de> |
pci: pci-uclass: Dynamically allocate the PCI regions Instead of using a fixed length pre-allocated array of regions, this patch moves to dynamically allocating the regions based on the number of available regions plus the necessary regions for DRAM banks. Since MAX_PCI_REGIONS is not needed any more, its removed completely with this patch. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Thierry Reding <treding@nvidia.com> Cc: Marek Vasut <marek.vasut+renesas@gmail.com>
|
#
143eb5b1 |
|
12-May-2020 |
Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
drivers: pci: add api to get dma regions Add api to get dma regions. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8b85dfc6 |
|
16-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: Avoid accessing seq directly At present various drivers etc. access the device's 'seq' member directly. This makes it harder to change the meaning of that member. Change access to go through a function instead. The drivers/i2c/lpc32xx_i2c.c file is left unchanged for now. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
caa4daa2 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename 'platdata' variables to just 'plat' We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
284d062e |
|
09-Sep-2020 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
pci: add a few ARI related defines Add a few defines related to PCI ARI configuration. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
51eeae91 |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add VF BAR map support for Enhanced Allocation Makes dm_pci_map_bar API available to map BAR for Virtual function PCI devices which support Enhanced Allocation. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
b8852dcf |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add support for Single-Root I/O Virtualization SR-IOV - Single Root I/O Virtualization PF - Physical Function VF - Virtual Function If SR-IOV capability is present, use it to initialize Virtual Function PCI device instances. pci_sriov_init function will read SR-IOV registers to create VF devices under the PF PCI device and also bind driver if available. This function needs to be invoked from Physical function device driver which expects VF device support, creating minimal impact on existing framework. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
e0024741 |
|
23-Jul-2020 |
Stefan Roese <sr@denx.de> |
pci: pci-uclass: Dynamically allocate the PCI regions Instead of using a fixed length pre-allocated array of regions, this patch moves to dynamically allocating the regions based on the number of available regions plus the necessary regions for DRAM banks. Since MAX_PCI_REGIONS is not needed any more, its removed completely with this patch. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Thierry Reding <treding@nvidia.com> Cc: Marek Vasut <marek.vasut+renesas@gmail.com>
|
#
143eb5b1 |
|
12-May-2020 |
Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
drivers: pci: add api to get dma regions Add api to get dma regions. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8b85dfc6 |
|
16-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: Avoid accessing seq directly At present various drivers etc. access the device's 'seq' member directly. This makes it harder to change the meaning of that member. Change access to go through a function instead. The drivers/i2c/lpc32xx_i2c.c file is left unchanged for now. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
caa4daa2 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename 'platdata' variables to just 'plat' We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
284d062e |
|
09-Sep-2020 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
pci: add a few ARI related defines Add a few defines related to PCI ARI configuration. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
51eeae91 |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add VF BAR map support for Enhanced Allocation Makes dm_pci_map_bar API available to map BAR for Virtual function PCI devices which support Enhanced Allocation. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
b8852dcf |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add support for Single-Root I/O Virtualization SR-IOV - Single Root I/O Virtualization PF - Physical Function VF - Virtual Function If SR-IOV capability is present, use it to initialize Virtual Function PCI device instances. pci_sriov_init function will read SR-IOV registers to create VF devices under the PF PCI device and also bind driver if available. This function needs to be invoked from Physical function device driver which expects VF device support, creating minimal impact on existing framework. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
e0024741 |
|
23-Jul-2020 |
Stefan Roese <sr@denx.de> |
pci: pci-uclass: Dynamically allocate the PCI regions Instead of using a fixed length pre-allocated array of regions, this patch moves to dynamically allocating the regions based on the number of available regions plus the necessary regions for DRAM banks. Since MAX_PCI_REGIONS is not needed any more, its removed completely with this patch. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Thierry Reding <treding@nvidia.com> Cc: Marek Vasut <marek.vasut+renesas@gmail.com>
|
#
143eb5b1 |
|
12-May-2020 |
Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
drivers: pci: add api to get dma regions Add api to get dma regions. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8b85dfc6 |
|
16-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: Avoid accessing seq directly At present various drivers etc. access the device's 'seq' member directly. This makes it harder to change the meaning of that member. Change access to go through a function instead. The drivers/i2c/lpc32xx_i2c.c file is left unchanged for now. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
caa4daa2 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename 'platdata' variables to just 'plat' We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
284d062e |
|
09-Sep-2020 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
pci: add a few ARI related defines Add a few defines related to PCI ARI configuration. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
51eeae91 |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add VF BAR map support for Enhanced Allocation Makes dm_pci_map_bar API available to map BAR for Virtual function PCI devices which support Enhanced Allocation. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
b8852dcf |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add support for Single-Root I/O Virtualization SR-IOV - Single Root I/O Virtualization PF - Physical Function VF - Virtual Function If SR-IOV capability is present, use it to initialize Virtual Function PCI device instances. pci_sriov_init function will read SR-IOV registers to create VF devices under the PF PCI device and also bind driver if available. This function needs to be invoked from Physical function device driver which expects VF device support, creating minimal impact on existing framework. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
e0024741 |
|
23-Jul-2020 |
Stefan Roese <sr@denx.de> |
pci: pci-uclass: Dynamically allocate the PCI regions Instead of using a fixed length pre-allocated array of regions, this patch moves to dynamically allocating the regions based on the number of available regions plus the necessary regions for DRAM banks. Since MAX_PCI_REGIONS is not needed any more, its removed completely with this patch. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Thierry Reding <treding@nvidia.com> Cc: Marek Vasut <marek.vasut+renesas@gmail.com>
|
#
143eb5b1 |
|
12-May-2020 |
Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
drivers: pci: add api to get dma regions Add api to get dma regions. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8b85dfc6 |
|
16-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: Avoid accessing seq directly At present various drivers etc. access the device's 'seq' member directly. This makes it harder to change the meaning of that member. Change access to go through a function instead. The drivers/i2c/lpc32xx_i2c.c file is left unchanged for now. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
caa4daa2 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename 'platdata' variables to just 'plat' We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
284d062e |
|
09-Sep-2020 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
pci: add a few ARI related defines Add a few defines related to PCI ARI configuration. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
51eeae91 |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add VF BAR map support for Enhanced Allocation Makes dm_pci_map_bar API available to map BAR for Virtual function PCI devices which support Enhanced Allocation. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
b8852dcf |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add support for Single-Root I/O Virtualization SR-IOV - Single Root I/O Virtualization PF - Physical Function VF - Virtual Function If SR-IOV capability is present, use it to initialize Virtual Function PCI device instances. pci_sriov_init function will read SR-IOV registers to create VF devices under the PF PCI device and also bind driver if available. This function needs to be invoked from Physical function device driver which expects VF device support, creating minimal impact on existing framework. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
e0024741 |
|
23-Jul-2020 |
Stefan Roese <sr@denx.de> |
pci: pci-uclass: Dynamically allocate the PCI regions Instead of using a fixed length pre-allocated array of regions, this patch moves to dynamically allocating the regions based on the number of available regions plus the necessary regions for DRAM banks. Since MAX_PCI_REGIONS is not needed any more, its removed completely with this patch. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Thierry Reding <treding@nvidia.com> Cc: Marek Vasut <marek.vasut+renesas@gmail.com>
|
#
143eb5b1 |
|
12-May-2020 |
Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
drivers: pci: add api to get dma regions Add api to get dma regions. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8b85dfc6 |
|
16-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: Avoid accessing seq directly At present various drivers etc. access the device's 'seq' member directly. This makes it harder to change the meaning of that member. Change access to go through a function instead. The drivers/i2c/lpc32xx_i2c.c file is left unchanged for now. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
caa4daa2 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename 'platdata' variables to just 'plat' We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
284d062e |
|
09-Sep-2020 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
pci: add a few ARI related defines Add a few defines related to PCI ARI configuration. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
51eeae91 |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add VF BAR map support for Enhanced Allocation Makes dm_pci_map_bar API available to map BAR for Virtual function PCI devices which support Enhanced Allocation. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
b8852dcf |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add support for Single-Root I/O Virtualization SR-IOV - Single Root I/O Virtualization PF - Physical Function VF - Virtual Function If SR-IOV capability is present, use it to initialize Virtual Function PCI device instances. pci_sriov_init function will read SR-IOV registers to create VF devices under the PF PCI device and also bind driver if available. This function needs to be invoked from Physical function device driver which expects VF device support, creating minimal impact on existing framework. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
e0024741 |
|
23-Jul-2020 |
Stefan Roese <sr@denx.de> |
pci: pci-uclass: Dynamically allocate the PCI regions Instead of using a fixed length pre-allocated array of regions, this patch moves to dynamically allocating the regions based on the number of available regions plus the necessary regions for DRAM banks. Since MAX_PCI_REGIONS is not needed any more, its removed completely with this patch. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Thierry Reding <treding@nvidia.com> Cc: Marek Vasut <marek.vasut+renesas@gmail.com>
|
#
143eb5b1 |
|
12-May-2020 |
Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
drivers: pci: add api to get dma regions Add api to get dma regions. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8b85dfc6 |
|
16-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: Avoid accessing seq directly At present various drivers etc. access the device's 'seq' member directly. This makes it harder to change the meaning of that member. Change access to go through a function instead. The drivers/i2c/lpc32xx_i2c.c file is left unchanged for now. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
caa4daa2 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename 'platdata' variables to just 'plat' We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
284d062e |
|
09-Sep-2020 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
pci: add a few ARI related defines Add a few defines related to PCI ARI configuration. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
51eeae91 |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add VF BAR map support for Enhanced Allocation Makes dm_pci_map_bar API available to map BAR for Virtual function PCI devices which support Enhanced Allocation. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
b8852dcf |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add support for Single-Root I/O Virtualization SR-IOV - Single Root I/O Virtualization PF - Physical Function VF - Virtual Function If SR-IOV capability is present, use it to initialize Virtual Function PCI device instances. pci_sriov_init function will read SR-IOV registers to create VF devices under the PF PCI device and also bind driver if available. This function needs to be invoked from Physical function device driver which expects VF device support, creating minimal impact on existing framework. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
e0024741 |
|
23-Jul-2020 |
Stefan Roese <sr@denx.de> |
pci: pci-uclass: Dynamically allocate the PCI regions Instead of using a fixed length pre-allocated array of regions, this patch moves to dynamically allocating the regions based on the number of available regions plus the necessary regions for DRAM banks. Since MAX_PCI_REGIONS is not needed any more, its removed completely with this patch. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Thierry Reding <treding@nvidia.com> Cc: Marek Vasut <marek.vasut+renesas@gmail.com>
|
#
143eb5b1 |
|
12-May-2020 |
Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
drivers: pci: add api to get dma regions Add api to get dma regions. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8b85dfc6 |
|
16-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: Avoid accessing seq directly At present various drivers etc. access the device's 'seq' member directly. This makes it harder to change the meaning of that member. Change access to go through a function instead. The drivers/i2c/lpc32xx_i2c.c file is left unchanged for now. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
caa4daa2 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename 'platdata' variables to just 'plat' We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
284d062e |
|
09-Sep-2020 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
pci: add a few ARI related defines Add a few defines related to PCI ARI configuration. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
51eeae91 |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add VF BAR map support for Enhanced Allocation Makes dm_pci_map_bar API available to map BAR for Virtual function PCI devices which support Enhanced Allocation. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
b8852dcf |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add support for Single-Root I/O Virtualization SR-IOV - Single Root I/O Virtualization PF - Physical Function VF - Virtual Function If SR-IOV capability is present, use it to initialize Virtual Function PCI device instances. pci_sriov_init function will read SR-IOV registers to create VF devices under the PF PCI device and also bind driver if available. This function needs to be invoked from Physical function device driver which expects VF device support, creating minimal impact on existing framework. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
e0024741 |
|
23-Jul-2020 |
Stefan Roese <sr@denx.de> |
pci: pci-uclass: Dynamically allocate the PCI regions Instead of using a fixed length pre-allocated array of regions, this patch moves to dynamically allocating the regions based on the number of available regions plus the necessary regions for DRAM banks. Since MAX_PCI_REGIONS is not needed any more, its removed completely with this patch. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Thierry Reding <treding@nvidia.com> Cc: Marek Vasut <marek.vasut+renesas@gmail.com>
|
#
143eb5b1 |
|
12-May-2020 |
Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
drivers: pci: add api to get dma regions Add api to get dma regions. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8b85dfc6 |
|
16-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: Avoid accessing seq directly At present various drivers etc. access the device's 'seq' member directly. This makes it harder to change the meaning of that member. Change access to go through a function instead. The drivers/i2c/lpc32xx_i2c.c file is left unchanged for now. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
caa4daa2 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename 'platdata' variables to just 'plat' We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
284d062e |
|
09-Sep-2020 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
pci: add a few ARI related defines Add a few defines related to PCI ARI configuration. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
51eeae91 |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add VF BAR map support for Enhanced Allocation Makes dm_pci_map_bar API available to map BAR for Virtual function PCI devices which support Enhanced Allocation. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
b8852dcf |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add support for Single-Root I/O Virtualization SR-IOV - Single Root I/O Virtualization PF - Physical Function VF - Virtual Function If SR-IOV capability is present, use it to initialize Virtual Function PCI device instances. pci_sriov_init function will read SR-IOV registers to create VF devices under the PF PCI device and also bind driver if available. This function needs to be invoked from Physical function device driver which expects VF device support, creating minimal impact on existing framework. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
e0024741 |
|
23-Jul-2020 |
Stefan Roese <sr@denx.de> |
pci: pci-uclass: Dynamically allocate the PCI regions Instead of using a fixed length pre-allocated array of regions, this patch moves to dynamically allocating the regions based on the number of available regions plus the necessary regions for DRAM banks. Since MAX_PCI_REGIONS is not needed any more, its removed completely with this patch. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Thierry Reding <treding@nvidia.com> Cc: Marek Vasut <marek.vasut+renesas@gmail.com>
|
#
143eb5b1 |
|
12-May-2020 |
Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
drivers: pci: add api to get dma regions Add api to get dma regions. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8b85dfc6 |
|
16-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: Avoid accessing seq directly At present various drivers etc. access the device's 'seq' member directly. This makes it harder to change the meaning of that member. Change access to go through a function instead. The drivers/i2c/lpc32xx_i2c.c file is left unchanged for now. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
caa4daa2 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename 'platdata' variables to just 'plat' We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
284d062e |
|
09-Sep-2020 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
pci: add a few ARI related defines Add a few defines related to PCI ARI configuration. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
51eeae91 |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add VF BAR map support for Enhanced Allocation Makes dm_pci_map_bar API available to map BAR for Virtual function PCI devices which support Enhanced Allocation. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
b8852dcf |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add support for Single-Root I/O Virtualization SR-IOV - Single Root I/O Virtualization PF - Physical Function VF - Virtual Function If SR-IOV capability is present, use it to initialize Virtual Function PCI device instances. pci_sriov_init function will read SR-IOV registers to create VF devices under the PF PCI device and also bind driver if available. This function needs to be invoked from Physical function device driver which expects VF device support, creating minimal impact on existing framework. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
e0024741 |
|
23-Jul-2020 |
Stefan Roese <sr@denx.de> |
pci: pci-uclass: Dynamically allocate the PCI regions Instead of using a fixed length pre-allocated array of regions, this patch moves to dynamically allocating the regions based on the number of available regions plus the necessary regions for DRAM banks. Since MAX_PCI_REGIONS is not needed any more, its removed completely with this patch. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Thierry Reding <treding@nvidia.com> Cc: Marek Vasut <marek.vasut+renesas@gmail.com>
|
#
143eb5b1 |
|
12-May-2020 |
Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
drivers: pci: add api to get dma regions Add api to get dma regions. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8b85dfc6 |
|
16-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: Avoid accessing seq directly At present various drivers etc. access the device's 'seq' member directly. This makes it harder to change the meaning of that member. Change access to go through a function instead. The drivers/i2c/lpc32xx_i2c.c file is left unchanged for now. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
caa4daa2 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename 'platdata' variables to just 'plat' We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
284d062e |
|
09-Sep-2020 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
pci: add a few ARI related defines Add a few defines related to PCI ARI configuration. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
51eeae91 |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add VF BAR map support for Enhanced Allocation Makes dm_pci_map_bar API available to map BAR for Virtual function PCI devices which support Enhanced Allocation. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
b8852dcf |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add support for Single-Root I/O Virtualization SR-IOV - Single Root I/O Virtualization PF - Physical Function VF - Virtual Function If SR-IOV capability is present, use it to initialize Virtual Function PCI device instances. pci_sriov_init function will read SR-IOV registers to create VF devices under the PF PCI device and also bind driver if available. This function needs to be invoked from Physical function device driver which expects VF device support, creating minimal impact on existing framework. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
e0024741 |
|
23-Jul-2020 |
Stefan Roese <sr@denx.de> |
pci: pci-uclass: Dynamically allocate the PCI regions Instead of using a fixed length pre-allocated array of regions, this patch moves to dynamically allocating the regions based on the number of available regions plus the necessary regions for DRAM banks. Since MAX_PCI_REGIONS is not needed any more, its removed completely with this patch. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Thierry Reding <treding@nvidia.com> Cc: Marek Vasut <marek.vasut+renesas@gmail.com>
|
#
143eb5b1 |
|
12-May-2020 |
Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
drivers: pci: add api to get dma regions Add api to get dma regions. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8b85dfc6 |
|
16-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: Avoid accessing seq directly At present various drivers etc. access the device's 'seq' member directly. This makes it harder to change the meaning of that member. Change access to go through a function instead. The drivers/i2c/lpc32xx_i2c.c file is left unchanged for now. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
caa4daa2 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename 'platdata' variables to just 'plat' We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
284d062e |
|
09-Sep-2020 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
pci: add a few ARI related defines Add a few defines related to PCI ARI configuration. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
51eeae91 |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add VF BAR map support for Enhanced Allocation Makes dm_pci_map_bar API available to map BAR for Virtual function PCI devices which support Enhanced Allocation. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
b8852dcf |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add support for Single-Root I/O Virtualization SR-IOV - Single Root I/O Virtualization PF - Physical Function VF - Virtual Function If SR-IOV capability is present, use it to initialize Virtual Function PCI device instances. pci_sriov_init function will read SR-IOV registers to create VF devices under the PF PCI device and also bind driver if available. This function needs to be invoked from Physical function device driver which expects VF device support, creating minimal impact on existing framework. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
e0024741 |
|
23-Jul-2020 |
Stefan Roese <sr@denx.de> |
pci: pci-uclass: Dynamically allocate the PCI regions Instead of using a fixed length pre-allocated array of regions, this patch moves to dynamically allocating the regions based on the number of available regions plus the necessary regions for DRAM banks. Since MAX_PCI_REGIONS is not needed any more, its removed completely with this patch. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Thierry Reding <treding@nvidia.com> Cc: Marek Vasut <marek.vasut+renesas@gmail.com>
|
#
143eb5b1 |
|
12-May-2020 |
Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
drivers: pci: add api to get dma regions Add api to get dma regions. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8b85dfc6 |
|
16-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: Avoid accessing seq directly At present various drivers etc. access the device's 'seq' member directly. This makes it harder to change the meaning of that member. Change access to go through a function instead. The drivers/i2c/lpc32xx_i2c.c file is left unchanged for now. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
caa4daa2 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename 'platdata' variables to just 'plat' We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
284d062e |
|
09-Sep-2020 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
pci: add a few ARI related defines Add a few defines related to PCI ARI configuration. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
51eeae91 |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add VF BAR map support for Enhanced Allocation Makes dm_pci_map_bar API available to map BAR for Virtual function PCI devices which support Enhanced Allocation. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
b8852dcf |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add support for Single-Root I/O Virtualization SR-IOV - Single Root I/O Virtualization PF - Physical Function VF - Virtual Function If SR-IOV capability is present, use it to initialize Virtual Function PCI device instances. pci_sriov_init function will read SR-IOV registers to create VF devices under the PF PCI device and also bind driver if available. This function needs to be invoked from Physical function device driver which expects VF device support, creating minimal impact on existing framework. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
e0024741 |
|
23-Jul-2020 |
Stefan Roese <sr@denx.de> |
pci: pci-uclass: Dynamically allocate the PCI regions Instead of using a fixed length pre-allocated array of regions, this patch moves to dynamically allocating the regions based on the number of available regions plus the necessary regions for DRAM banks. Since MAX_PCI_REGIONS is not needed any more, its removed completely with this patch. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Thierry Reding <treding@nvidia.com> Cc: Marek Vasut <marek.vasut+renesas@gmail.com>
|
#
143eb5b1 |
|
12-May-2020 |
Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
drivers: pci: add api to get dma regions Add api to get dma regions. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8b85dfc6 |
|
16-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: Avoid accessing seq directly At present various drivers etc. access the device's 'seq' member directly. This makes it harder to change the meaning of that member. Change access to go through a function instead. The drivers/i2c/lpc32xx_i2c.c file is left unchanged for now. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
caa4daa2 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename 'platdata' variables to just 'plat' We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
284d062e |
|
09-Sep-2020 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
pci: add a few ARI related defines Add a few defines related to PCI ARI configuration. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
51eeae91 |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add VF BAR map support for Enhanced Allocation Makes dm_pci_map_bar API available to map BAR for Virtual function PCI devices which support Enhanced Allocation. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
b8852dcf |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add support for Single-Root I/O Virtualization SR-IOV - Single Root I/O Virtualization PF - Physical Function VF - Virtual Function If SR-IOV capability is present, use it to initialize Virtual Function PCI device instances. pci_sriov_init function will read SR-IOV registers to create VF devices under the PF PCI device and also bind driver if available. This function needs to be invoked from Physical function device driver which expects VF device support, creating minimal impact on existing framework. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
e0024741 |
|
23-Jul-2020 |
Stefan Roese <sr@denx.de> |
pci: pci-uclass: Dynamically allocate the PCI regions Instead of using a fixed length pre-allocated array of regions, this patch moves to dynamically allocating the regions based on the number of available regions plus the necessary regions for DRAM banks. Since MAX_PCI_REGIONS is not needed any more, its removed completely with this patch. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Thierry Reding <treding@nvidia.com> Cc: Marek Vasut <marek.vasut+renesas@gmail.com>
|
#
143eb5b1 |
|
12-May-2020 |
Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
drivers: pci: add api to get dma regions Add api to get dma regions. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8b85dfc6 |
|
16-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: Avoid accessing seq directly At present various drivers etc. access the device's 'seq' member directly. This makes it harder to change the meaning of that member. Change access to go through a function instead. The drivers/i2c/lpc32xx_i2c.c file is left unchanged for now. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
caa4daa2 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename 'platdata' variables to just 'plat' We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
284d062e |
|
09-Sep-2020 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
pci: add a few ARI related defines Add a few defines related to PCI ARI configuration. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
51eeae91 |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add VF BAR map support for Enhanced Allocation Makes dm_pci_map_bar API available to map BAR for Virtual function PCI devices which support Enhanced Allocation. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
b8852dcf |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add support for Single-Root I/O Virtualization SR-IOV - Single Root I/O Virtualization PF - Physical Function VF - Virtual Function If SR-IOV capability is present, use it to initialize Virtual Function PCI device instances. pci_sriov_init function will read SR-IOV registers to create VF devices under the PF PCI device and also bind driver if available. This function needs to be invoked from Physical function device driver which expects VF device support, creating minimal impact on existing framework. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
e0024741 |
|
23-Jul-2020 |
Stefan Roese <sr@denx.de> |
pci: pci-uclass: Dynamically allocate the PCI regions Instead of using a fixed length pre-allocated array of regions, this patch moves to dynamically allocating the regions based on the number of available regions plus the necessary regions for DRAM banks. Since MAX_PCI_REGIONS is not needed any more, its removed completely with this patch. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Thierry Reding <treding@nvidia.com> Cc: Marek Vasut <marek.vasut+renesas@gmail.com>
|
#
143eb5b1 |
|
12-May-2020 |
Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
drivers: pci: add api to get dma regions Add api to get dma regions. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8b85dfc6 |
|
16-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: Avoid accessing seq directly At present various drivers etc. access the device's 'seq' member directly. This makes it harder to change the meaning of that member. Change access to go through a function instead. The drivers/i2c/lpc32xx_i2c.c file is left unchanged for now. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
caa4daa2 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename 'platdata' variables to just 'plat' We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
284d062e |
|
09-Sep-2020 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
pci: add a few ARI related defines Add a few defines related to PCI ARI configuration. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
51eeae91 |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add VF BAR map support for Enhanced Allocation Makes dm_pci_map_bar API available to map BAR for Virtual function PCI devices which support Enhanced Allocation. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
b8852dcf |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add support for Single-Root I/O Virtualization SR-IOV - Single Root I/O Virtualization PF - Physical Function VF - Virtual Function If SR-IOV capability is present, use it to initialize Virtual Function PCI device instances. pci_sriov_init function will read SR-IOV registers to create VF devices under the PF PCI device and also bind driver if available. This function needs to be invoked from Physical function device driver which expects VF device support, creating minimal impact on existing framework. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
e0024741 |
|
23-Jul-2020 |
Stefan Roese <sr@denx.de> |
pci: pci-uclass: Dynamically allocate the PCI regions Instead of using a fixed length pre-allocated array of regions, this patch moves to dynamically allocating the regions based on the number of available regions plus the necessary regions for DRAM banks. Since MAX_PCI_REGIONS is not needed any more, its removed completely with this patch. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Thierry Reding <treding@nvidia.com> Cc: Marek Vasut <marek.vasut+renesas@gmail.com>
|
#
143eb5b1 |
|
12-May-2020 |
Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
drivers: pci: add api to get dma regions Add api to get dma regions. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8b85dfc6 |
|
16-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: Avoid accessing seq directly At present various drivers etc. access the device's 'seq' member directly. This makes it harder to change the meaning of that member. Change access to go through a function instead. The drivers/i2c/lpc32xx_i2c.c file is left unchanged for now. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
caa4daa2 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename 'platdata' variables to just 'plat' We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
284d062e |
|
09-Sep-2020 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
pci: add a few ARI related defines Add a few defines related to PCI ARI configuration. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
51eeae91 |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add VF BAR map support for Enhanced Allocation Makes dm_pci_map_bar API available to map BAR for Virtual function PCI devices which support Enhanced Allocation. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
b8852dcf |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add support for Single-Root I/O Virtualization SR-IOV - Single Root I/O Virtualization PF - Physical Function VF - Virtual Function If SR-IOV capability is present, use it to initialize Virtual Function PCI device instances. pci_sriov_init function will read SR-IOV registers to create VF devices under the PF PCI device and also bind driver if available. This function needs to be invoked from Physical function device driver which expects VF device support, creating minimal impact on existing framework. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
e0024741 |
|
23-Jul-2020 |
Stefan Roese <sr@denx.de> |
pci: pci-uclass: Dynamically allocate the PCI regions Instead of using a fixed length pre-allocated array of regions, this patch moves to dynamically allocating the regions based on the number of available regions plus the necessary regions for DRAM banks. Since MAX_PCI_REGIONS is not needed any more, its removed completely with this patch. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Thierry Reding <treding@nvidia.com> Cc: Marek Vasut <marek.vasut+renesas@gmail.com>
|
#
143eb5b1 |
|
12-May-2020 |
Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
drivers: pci: add api to get dma regions Add api to get dma regions. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8b85dfc6 |
|
16-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: Avoid accessing seq directly At present various drivers etc. access the device's 'seq' member directly. This makes it harder to change the meaning of that member. Change access to go through a function instead. The drivers/i2c/lpc32xx_i2c.c file is left unchanged for now. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
caa4daa2 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename 'platdata' variables to just 'plat' We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
284d062e |
|
09-Sep-2020 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
pci: add a few ARI related defines Add a few defines related to PCI ARI configuration. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
51eeae91 |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add VF BAR map support for Enhanced Allocation Makes dm_pci_map_bar API available to map BAR for Virtual function PCI devices which support Enhanced Allocation. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
b8852dcf |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add support for Single-Root I/O Virtualization SR-IOV - Single Root I/O Virtualization PF - Physical Function VF - Virtual Function If SR-IOV capability is present, use it to initialize Virtual Function PCI device instances. pci_sriov_init function will read SR-IOV registers to create VF devices under the PF PCI device and also bind driver if available. This function needs to be invoked from Physical function device driver which expects VF device support, creating minimal impact on existing framework. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
e0024741 |
|
23-Jul-2020 |
Stefan Roese <sr@denx.de> |
pci: pci-uclass: Dynamically allocate the PCI regions Instead of using a fixed length pre-allocated array of regions, this patch moves to dynamically allocating the regions based on the number of available regions plus the necessary regions for DRAM banks. Since MAX_PCI_REGIONS is not needed any more, its removed completely with this patch. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Thierry Reding <treding@nvidia.com> Cc: Marek Vasut <marek.vasut+renesas@gmail.com>
|
#
143eb5b1 |
|
12-May-2020 |
Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
drivers: pci: add api to get dma regions Add api to get dma regions. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8b85dfc6 |
|
16-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: Avoid accessing seq directly At present various drivers etc. access the device's 'seq' member directly. This makes it harder to change the meaning of that member. Change access to go through a function instead. The drivers/i2c/lpc32xx_i2c.c file is left unchanged for now. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
caa4daa2 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename 'platdata' variables to just 'plat' We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
284d062e |
|
09-Sep-2020 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
pci: add a few ARI related defines Add a few defines related to PCI ARI configuration. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
51eeae91 |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add VF BAR map support for Enhanced Allocation Makes dm_pci_map_bar API available to map BAR for Virtual function PCI devices which support Enhanced Allocation. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
b8852dcf |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add support for Single-Root I/O Virtualization SR-IOV - Single Root I/O Virtualization PF - Physical Function VF - Virtual Function If SR-IOV capability is present, use it to initialize Virtual Function PCI device instances. pci_sriov_init function will read SR-IOV registers to create VF devices under the PF PCI device and also bind driver if available. This function needs to be invoked from Physical function device driver which expects VF device support, creating minimal impact on existing framework. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
e0024741 |
|
23-Jul-2020 |
Stefan Roese <sr@denx.de> |
pci: pci-uclass: Dynamically allocate the PCI regions Instead of using a fixed length pre-allocated array of regions, this patch moves to dynamically allocating the regions based on the number of available regions plus the necessary regions for DRAM banks. Since MAX_PCI_REGIONS is not needed any more, its removed completely with this patch. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Thierry Reding <treding@nvidia.com> Cc: Marek Vasut <marek.vasut+renesas@gmail.com>
|
#
143eb5b1 |
|
12-May-2020 |
Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
drivers: pci: add api to get dma regions Add api to get dma regions. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8b85dfc6 |
|
16-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: Avoid accessing seq directly At present various drivers etc. access the device's 'seq' member directly. This makes it harder to change the meaning of that member. Change access to go through a function instead. The drivers/i2c/lpc32xx_i2c.c file is left unchanged for now. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
caa4daa2 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename 'platdata' variables to just 'plat' We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
284d062e |
|
09-Sep-2020 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
pci: add a few ARI related defines Add a few defines related to PCI ARI configuration. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
51eeae91 |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add VF BAR map support for Enhanced Allocation Makes dm_pci_map_bar API available to map BAR for Virtual function PCI devices which support Enhanced Allocation. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
b8852dcf |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add support for Single-Root I/O Virtualization SR-IOV - Single Root I/O Virtualization PF - Physical Function VF - Virtual Function If SR-IOV capability is present, use it to initialize Virtual Function PCI device instances. pci_sriov_init function will read SR-IOV registers to create VF devices under the PF PCI device and also bind driver if available. This function needs to be invoked from Physical function device driver which expects VF device support, creating minimal impact on existing framework. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
e0024741 |
|
23-Jul-2020 |
Stefan Roese <sr@denx.de> |
pci: pci-uclass: Dynamically allocate the PCI regions Instead of using a fixed length pre-allocated array of regions, this patch moves to dynamically allocating the regions based on the number of available regions plus the necessary regions for DRAM banks. Since MAX_PCI_REGIONS is not needed any more, its removed completely with this patch. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Thierry Reding <treding@nvidia.com> Cc: Marek Vasut <marek.vasut+renesas@gmail.com>
|
#
143eb5b1 |
|
12-May-2020 |
Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
drivers: pci: add api to get dma regions Add api to get dma regions. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8b85dfc6 |
|
16-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: Avoid accessing seq directly At present various drivers etc. access the device's 'seq' member directly. This makes it harder to change the meaning of that member. Change access to go through a function instead. The drivers/i2c/lpc32xx_i2c.c file is left unchanged for now. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
caa4daa2 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename 'platdata' variables to just 'plat' We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
284d062e |
|
09-Sep-2020 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
pci: add a few ARI related defines Add a few defines related to PCI ARI configuration. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
51eeae91 |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add VF BAR map support for Enhanced Allocation Makes dm_pci_map_bar API available to map BAR for Virtual function PCI devices which support Enhanced Allocation. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
b8852dcf |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add support for Single-Root I/O Virtualization SR-IOV - Single Root I/O Virtualization PF - Physical Function VF - Virtual Function If SR-IOV capability is present, use it to initialize Virtual Function PCI device instances. pci_sriov_init function will read SR-IOV registers to create VF devices under the PF PCI device and also bind driver if available. This function needs to be invoked from Physical function device driver which expects VF device support, creating minimal impact on existing framework. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
e0024741 |
|
23-Jul-2020 |
Stefan Roese <sr@denx.de> |
pci: pci-uclass: Dynamically allocate the PCI regions Instead of using a fixed length pre-allocated array of regions, this patch moves to dynamically allocating the regions based on the number of available regions plus the necessary regions for DRAM banks. Since MAX_PCI_REGIONS is not needed any more, its removed completely with this patch. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Thierry Reding <treding@nvidia.com> Cc: Marek Vasut <marek.vasut+renesas@gmail.com>
|
#
143eb5b1 |
|
12-May-2020 |
Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
drivers: pci: add api to get dma regions Add api to get dma regions. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8b85dfc6 |
|
16-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: Avoid accessing seq directly At present various drivers etc. access the device's 'seq' member directly. This makes it harder to change the meaning of that member. Change access to go through a function instead. The drivers/i2c/lpc32xx_i2c.c file is left unchanged for now. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
caa4daa2 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename 'platdata' variables to just 'plat' We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
284d062e |
|
09-Sep-2020 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
pci: add a few ARI related defines Add a few defines related to PCI ARI configuration. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
51eeae91 |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add VF BAR map support for Enhanced Allocation Makes dm_pci_map_bar API available to map BAR for Virtual function PCI devices which support Enhanced Allocation. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
b8852dcf |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add support for Single-Root I/O Virtualization SR-IOV - Single Root I/O Virtualization PF - Physical Function VF - Virtual Function If SR-IOV capability is present, use it to initialize Virtual Function PCI device instances. pci_sriov_init function will read SR-IOV registers to create VF devices under the PF PCI device and also bind driver if available. This function needs to be invoked from Physical function device driver which expects VF device support, creating minimal impact on existing framework. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
e0024741 |
|
23-Jul-2020 |
Stefan Roese <sr@denx.de> |
pci: pci-uclass: Dynamically allocate the PCI regions Instead of using a fixed length pre-allocated array of regions, this patch moves to dynamically allocating the regions based on the number of available regions plus the necessary regions for DRAM banks. Since MAX_PCI_REGIONS is not needed any more, its removed completely with this patch. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Thierry Reding <treding@nvidia.com> Cc: Marek Vasut <marek.vasut+renesas@gmail.com>
|
#
143eb5b1 |
|
12-May-2020 |
Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
drivers: pci: add api to get dma regions Add api to get dma regions. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8b85dfc6 |
|
16-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: Avoid accessing seq directly At present various drivers etc. access the device's 'seq' member directly. This makes it harder to change the meaning of that member. Change access to go through a function instead. The drivers/i2c/lpc32xx_i2c.c file is left unchanged for now. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
caa4daa2 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename 'platdata' variables to just 'plat' We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
284d062e |
|
09-Sep-2020 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
pci: add a few ARI related defines Add a few defines related to PCI ARI configuration. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
51eeae91 |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add VF BAR map support for Enhanced Allocation Makes dm_pci_map_bar API available to map BAR for Virtual function PCI devices which support Enhanced Allocation. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
b8852dcf |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add support for Single-Root I/O Virtualization SR-IOV - Single Root I/O Virtualization PF - Physical Function VF - Virtual Function If SR-IOV capability is present, use it to initialize Virtual Function PCI device instances. pci_sriov_init function will read SR-IOV registers to create VF devices under the PF PCI device and also bind driver if available. This function needs to be invoked from Physical function device driver which expects VF device support, creating minimal impact on existing framework. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
e0024741 |
|
23-Jul-2020 |
Stefan Roese <sr@denx.de> |
pci: pci-uclass: Dynamically allocate the PCI regions Instead of using a fixed length pre-allocated array of regions, this patch moves to dynamically allocating the regions based on the number of available regions plus the necessary regions for DRAM banks. Since MAX_PCI_REGIONS is not needed any more, its removed completely with this patch. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Thierry Reding <treding@nvidia.com> Cc: Marek Vasut <marek.vasut+renesas@gmail.com>
|
#
143eb5b1 |
|
12-May-2020 |
Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
drivers: pci: add api to get dma regions Add api to get dma regions. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8b85dfc6 |
|
16-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: Avoid accessing seq directly At present various drivers etc. access the device's 'seq' member directly. This makes it harder to change the meaning of that member. Change access to go through a function instead. The drivers/i2c/lpc32xx_i2c.c file is left unchanged for now. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
caa4daa2 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename 'platdata' variables to just 'plat' We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
284d062e |
|
09-Sep-2020 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
pci: add a few ARI related defines Add a few defines related to PCI ARI configuration. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
51eeae91 |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add VF BAR map support for Enhanced Allocation Makes dm_pci_map_bar API available to map BAR for Virtual function PCI devices which support Enhanced Allocation. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
b8852dcf |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add support for Single-Root I/O Virtualization SR-IOV - Single Root I/O Virtualization PF - Physical Function VF - Virtual Function If SR-IOV capability is present, use it to initialize Virtual Function PCI device instances. pci_sriov_init function will read SR-IOV registers to create VF devices under the PF PCI device and also bind driver if available. This function needs to be invoked from Physical function device driver which expects VF device support, creating minimal impact on existing framework. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
e0024741 |
|
23-Jul-2020 |
Stefan Roese <sr@denx.de> |
pci: pci-uclass: Dynamically allocate the PCI regions Instead of using a fixed length pre-allocated array of regions, this patch moves to dynamically allocating the regions based on the number of available regions plus the necessary regions for DRAM banks. Since MAX_PCI_REGIONS is not needed any more, its removed completely with this patch. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Thierry Reding <treding@nvidia.com> Cc: Marek Vasut <marek.vasut+renesas@gmail.com>
|
#
143eb5b1 |
|
12-May-2020 |
Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
drivers: pci: add api to get dma regions Add api to get dma regions. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8b85dfc6 |
|
16-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: Avoid accessing seq directly At present various drivers etc. access the device's 'seq' member directly. This makes it harder to change the meaning of that member. Change access to go through a function instead. The drivers/i2c/lpc32xx_i2c.c file is left unchanged for now. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
caa4daa2 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename 'platdata' variables to just 'plat' We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
284d062e |
|
09-Sep-2020 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
pci: add a few ARI related defines Add a few defines related to PCI ARI configuration. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
51eeae91 |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add VF BAR map support for Enhanced Allocation Makes dm_pci_map_bar API available to map BAR for Virtual function PCI devices which support Enhanced Allocation. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
b8852dcf |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add support for Single-Root I/O Virtualization SR-IOV - Single Root I/O Virtualization PF - Physical Function VF - Virtual Function If SR-IOV capability is present, use it to initialize Virtual Function PCI device instances. pci_sriov_init function will read SR-IOV registers to create VF devices under the PF PCI device and also bind driver if available. This function needs to be invoked from Physical function device driver which expects VF device support, creating minimal impact on existing framework. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
e0024741 |
|
23-Jul-2020 |
Stefan Roese <sr@denx.de> |
pci: pci-uclass: Dynamically allocate the PCI regions Instead of using a fixed length pre-allocated array of regions, this patch moves to dynamically allocating the regions based on the number of available regions plus the necessary regions for DRAM banks. Since MAX_PCI_REGIONS is not needed any more, its removed completely with this patch. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Thierry Reding <treding@nvidia.com> Cc: Marek Vasut <marek.vasut+renesas@gmail.com>
|
#
143eb5b1 |
|
12-May-2020 |
Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
drivers: pci: add api to get dma regions Add api to get dma regions. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8b85dfc6 |
|
16-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: Avoid accessing seq directly At present various drivers etc. access the device's 'seq' member directly. This makes it harder to change the meaning of that member. Change access to go through a function instead. The drivers/i2c/lpc32xx_i2c.c file is left unchanged for now. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
caa4daa2 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename 'platdata' variables to just 'plat' We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
284d062e |
|
09-Sep-2020 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
pci: add a few ARI related defines Add a few defines related to PCI ARI configuration. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
51eeae91 |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add VF BAR map support for Enhanced Allocation Makes dm_pci_map_bar API available to map BAR for Virtual function PCI devices which support Enhanced Allocation. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
b8852dcf |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add support for Single-Root I/O Virtualization SR-IOV - Single Root I/O Virtualization PF - Physical Function VF - Virtual Function If SR-IOV capability is present, use it to initialize Virtual Function PCI device instances. pci_sriov_init function will read SR-IOV registers to create VF devices under the PF PCI device and also bind driver if available. This function needs to be invoked from Physical function device driver which expects VF device support, creating minimal impact on existing framework. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
e0024741 |
|
23-Jul-2020 |
Stefan Roese <sr@denx.de> |
pci: pci-uclass: Dynamically allocate the PCI regions Instead of using a fixed length pre-allocated array of regions, this patch moves to dynamically allocating the regions based on the number of available regions plus the necessary regions for DRAM banks. Since MAX_PCI_REGIONS is not needed any more, its removed completely with this patch. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Thierry Reding <treding@nvidia.com> Cc: Marek Vasut <marek.vasut+renesas@gmail.com>
|
#
143eb5b1 |
|
12-May-2020 |
Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
drivers: pci: add api to get dma regions Add api to get dma regions. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8b85dfc6 |
|
16-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: Avoid accessing seq directly At present various drivers etc. access the device's 'seq' member directly. This makes it harder to change the meaning of that member. Change access to go through a function instead. The drivers/i2c/lpc32xx_i2c.c file is left unchanged for now. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
caa4daa2 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename 'platdata' variables to just 'plat' We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
284d062e |
|
09-Sep-2020 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
pci: add a few ARI related defines Add a few defines related to PCI ARI configuration. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
51eeae91 |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add VF BAR map support for Enhanced Allocation Makes dm_pci_map_bar API available to map BAR for Virtual function PCI devices which support Enhanced Allocation. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
b8852dcf |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add support for Single-Root I/O Virtualization SR-IOV - Single Root I/O Virtualization PF - Physical Function VF - Virtual Function If SR-IOV capability is present, use it to initialize Virtual Function PCI device instances. pci_sriov_init function will read SR-IOV registers to create VF devices under the PF PCI device and also bind driver if available. This function needs to be invoked from Physical function device driver which expects VF device support, creating minimal impact on existing framework. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
e0024741 |
|
23-Jul-2020 |
Stefan Roese <sr@denx.de> |
pci: pci-uclass: Dynamically allocate the PCI regions Instead of using a fixed length pre-allocated array of regions, this patch moves to dynamically allocating the regions based on the number of available regions plus the necessary regions for DRAM banks. Since MAX_PCI_REGIONS is not needed any more, its removed completely with this patch. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Thierry Reding <treding@nvidia.com> Cc: Marek Vasut <marek.vasut+renesas@gmail.com>
|
#
143eb5b1 |
|
12-May-2020 |
Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
drivers: pci: add api to get dma regions Add api to get dma regions. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8b85dfc6 |
|
16-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: Avoid accessing seq directly At present various drivers etc. access the device's 'seq' member directly. This makes it harder to change the meaning of that member. Change access to go through a function instead. The drivers/i2c/lpc32xx_i2c.c file is left unchanged for now. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
caa4daa2 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename 'platdata' variables to just 'plat' We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
284d062e |
|
09-Sep-2020 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
pci: add a few ARI related defines Add a few defines related to PCI ARI configuration. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
51eeae91 |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add VF BAR map support for Enhanced Allocation Makes dm_pci_map_bar API available to map BAR for Virtual function PCI devices which support Enhanced Allocation. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
b8852dcf |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add support for Single-Root I/O Virtualization SR-IOV - Single Root I/O Virtualization PF - Physical Function VF - Virtual Function If SR-IOV capability is present, use it to initialize Virtual Function PCI device instances. pci_sriov_init function will read SR-IOV registers to create VF devices under the PF PCI device and also bind driver if available. This function needs to be invoked from Physical function device driver which expects VF device support, creating minimal impact on existing framework. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
e0024741 |
|
23-Jul-2020 |
Stefan Roese <sr@denx.de> |
pci: pci-uclass: Dynamically allocate the PCI regions Instead of using a fixed length pre-allocated array of regions, this patch moves to dynamically allocating the regions based on the number of available regions plus the necessary regions for DRAM banks. Since MAX_PCI_REGIONS is not needed any more, its removed completely with this patch. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Thierry Reding <treding@nvidia.com> Cc: Marek Vasut <marek.vasut+renesas@gmail.com>
|
#
143eb5b1 |
|
12-May-2020 |
Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
drivers: pci: add api to get dma regions Add api to get dma regions. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8b85dfc6 |
|
16-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: Avoid accessing seq directly At present various drivers etc. access the device's 'seq' member directly. This makes it harder to change the meaning of that member. Change access to go through a function instead. The drivers/i2c/lpc32xx_i2c.c file is left unchanged for now. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
caa4daa2 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename 'platdata' variables to just 'plat' We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
284d062e |
|
09-Sep-2020 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
pci: add a few ARI related defines Add a few defines related to PCI ARI configuration. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
51eeae91 |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add VF BAR map support for Enhanced Allocation Makes dm_pci_map_bar API available to map BAR for Virtual function PCI devices which support Enhanced Allocation. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
b8852dcf |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add support for Single-Root I/O Virtualization SR-IOV - Single Root I/O Virtualization PF - Physical Function VF - Virtual Function If SR-IOV capability is present, use it to initialize Virtual Function PCI device instances. pci_sriov_init function will read SR-IOV registers to create VF devices under the PF PCI device and also bind driver if available. This function needs to be invoked from Physical function device driver which expects VF device support, creating minimal impact on existing framework. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
e0024741 |
|
23-Jul-2020 |
Stefan Roese <sr@denx.de> |
pci: pci-uclass: Dynamically allocate the PCI regions Instead of using a fixed length pre-allocated array of regions, this patch moves to dynamically allocating the regions based on the number of available regions plus the necessary regions for DRAM banks. Since MAX_PCI_REGIONS is not needed any more, its removed completely with this patch. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Thierry Reding <treding@nvidia.com> Cc: Marek Vasut <marek.vasut+renesas@gmail.com>
|
#
143eb5b1 |
|
12-May-2020 |
Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
drivers: pci: add api to get dma regions Add api to get dma regions. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8b85dfc6 |
|
16-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: Avoid accessing seq directly At present various drivers etc. access the device's 'seq' member directly. This makes it harder to change the meaning of that member. Change access to go through a function instead. The drivers/i2c/lpc32xx_i2c.c file is left unchanged for now. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
caa4daa2 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename 'platdata' variables to just 'plat' We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
284d062e |
|
09-Sep-2020 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
pci: add a few ARI related defines Add a few defines related to PCI ARI configuration. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
51eeae91 |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add VF BAR map support for Enhanced Allocation Makes dm_pci_map_bar API available to map BAR for Virtual function PCI devices which support Enhanced Allocation. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
b8852dcf |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add support for Single-Root I/O Virtualization SR-IOV - Single Root I/O Virtualization PF - Physical Function VF - Virtual Function If SR-IOV capability is present, use it to initialize Virtual Function PCI device instances. pci_sriov_init function will read SR-IOV registers to create VF devices under the PF PCI device and also bind driver if available. This function needs to be invoked from Physical function device driver which expects VF device support, creating minimal impact on existing framework. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
e0024741 |
|
23-Jul-2020 |
Stefan Roese <sr@denx.de> |
pci: pci-uclass: Dynamically allocate the PCI regions Instead of using a fixed length pre-allocated array of regions, this patch moves to dynamically allocating the regions based on the number of available regions plus the necessary regions for DRAM banks. Since MAX_PCI_REGIONS is not needed any more, its removed completely with this patch. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Thierry Reding <treding@nvidia.com> Cc: Marek Vasut <marek.vasut+renesas@gmail.com>
|
#
143eb5b1 |
|
12-May-2020 |
Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
drivers: pci: add api to get dma regions Add api to get dma regions. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8b85dfc6 |
|
16-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: Avoid accessing seq directly At present various drivers etc. access the device's 'seq' member directly. This makes it harder to change the meaning of that member. Change access to go through a function instead. The drivers/i2c/lpc32xx_i2c.c file is left unchanged for now. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
caa4daa2 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename 'platdata' variables to just 'plat' We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
284d062e |
|
09-Sep-2020 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
pci: add a few ARI related defines Add a few defines related to PCI ARI configuration. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
51eeae91 |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add VF BAR map support for Enhanced Allocation Makes dm_pci_map_bar API available to map BAR for Virtual function PCI devices which support Enhanced Allocation. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
b8852dcf |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add support for Single-Root I/O Virtualization SR-IOV - Single Root I/O Virtualization PF - Physical Function VF - Virtual Function If SR-IOV capability is present, use it to initialize Virtual Function PCI device instances. pci_sriov_init function will read SR-IOV registers to create VF devices under the PF PCI device and also bind driver if available. This function needs to be invoked from Physical function device driver which expects VF device support, creating minimal impact on existing framework. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
e0024741 |
|
23-Jul-2020 |
Stefan Roese <sr@denx.de> |
pci: pci-uclass: Dynamically allocate the PCI regions Instead of using a fixed length pre-allocated array of regions, this patch moves to dynamically allocating the regions based on the number of available regions plus the necessary regions for DRAM banks. Since MAX_PCI_REGIONS is not needed any more, its removed completely with this patch. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Thierry Reding <treding@nvidia.com> Cc: Marek Vasut <marek.vasut+renesas@gmail.com>
|
#
143eb5b1 |
|
12-May-2020 |
Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
drivers: pci: add api to get dma regions Add api to get dma regions. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8b85dfc6 |
|
16-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: Avoid accessing seq directly At present various drivers etc. access the device's 'seq' member directly. This makes it harder to change the meaning of that member. Change access to go through a function instead. The drivers/i2c/lpc32xx_i2c.c file is left unchanged for now. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
caa4daa2 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename 'platdata' variables to just 'plat' We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
284d062e |
|
09-Sep-2020 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
pci: add a few ARI related defines Add a few defines related to PCI ARI configuration. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
51eeae91 |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add VF BAR map support for Enhanced Allocation Makes dm_pci_map_bar API available to map BAR for Virtual function PCI devices which support Enhanced Allocation. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
b8852dcf |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add support for Single-Root I/O Virtualization SR-IOV - Single Root I/O Virtualization PF - Physical Function VF - Virtual Function If SR-IOV capability is present, use it to initialize Virtual Function PCI device instances. pci_sriov_init function will read SR-IOV registers to create VF devices under the PF PCI device and also bind driver if available. This function needs to be invoked from Physical function device driver which expects VF device support, creating minimal impact on existing framework. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
e0024741 |
|
23-Jul-2020 |
Stefan Roese <sr@denx.de> |
pci: pci-uclass: Dynamically allocate the PCI regions Instead of using a fixed length pre-allocated array of regions, this patch moves to dynamically allocating the regions based on the number of available regions plus the necessary regions for DRAM banks. Since MAX_PCI_REGIONS is not needed any more, its removed completely with this patch. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Thierry Reding <treding@nvidia.com> Cc: Marek Vasut <marek.vasut+renesas@gmail.com>
|
#
143eb5b1 |
|
12-May-2020 |
Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
drivers: pci: add api to get dma regions Add api to get dma regions. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8b85dfc6 |
|
16-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: Avoid accessing seq directly At present various drivers etc. access the device's 'seq' member directly. This makes it harder to change the meaning of that member. Change access to go through a function instead. The drivers/i2c/lpc32xx_i2c.c file is left unchanged for now. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
caa4daa2 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename 'platdata' variables to just 'plat' We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
284d062e |
|
09-Sep-2020 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
pci: add a few ARI related defines Add a few defines related to PCI ARI configuration. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
51eeae91 |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add VF BAR map support for Enhanced Allocation Makes dm_pci_map_bar API available to map BAR for Virtual function PCI devices which support Enhanced Allocation. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
b8852dcf |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add support for Single-Root I/O Virtualization SR-IOV - Single Root I/O Virtualization PF - Physical Function VF - Virtual Function If SR-IOV capability is present, use it to initialize Virtual Function PCI device instances. pci_sriov_init function will read SR-IOV registers to create VF devices under the PF PCI device and also bind driver if available. This function needs to be invoked from Physical function device driver which expects VF device support, creating minimal impact on existing framework. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
e0024741 |
|
23-Jul-2020 |
Stefan Roese <sr@denx.de> |
pci: pci-uclass: Dynamically allocate the PCI regions Instead of using a fixed length pre-allocated array of regions, this patch moves to dynamically allocating the regions based on the number of available regions plus the necessary regions for DRAM banks. Since MAX_PCI_REGIONS is not needed any more, its removed completely with this patch. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Thierry Reding <treding@nvidia.com> Cc: Marek Vasut <marek.vasut+renesas@gmail.com>
|
#
143eb5b1 |
|
12-May-2020 |
Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
drivers: pci: add api to get dma regions Add api to get dma regions. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8b85dfc6 |
|
16-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: Avoid accessing seq directly At present various drivers etc. access the device's 'seq' member directly. This makes it harder to change the meaning of that member. Change access to go through a function instead. The drivers/i2c/lpc32xx_i2c.c file is left unchanged for now. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
caa4daa2 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename 'platdata' variables to just 'plat' We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
284d062e |
|
09-Sep-2020 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
pci: add a few ARI related defines Add a few defines related to PCI ARI configuration. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
51eeae91 |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add VF BAR map support for Enhanced Allocation Makes dm_pci_map_bar API available to map BAR for Virtual function PCI devices which support Enhanced Allocation. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
b8852dcf |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add support for Single-Root I/O Virtualization SR-IOV - Single Root I/O Virtualization PF - Physical Function VF - Virtual Function If SR-IOV capability is present, use it to initialize Virtual Function PCI device instances. pci_sriov_init function will read SR-IOV registers to create VF devices under the PF PCI device and also bind driver if available. This function needs to be invoked from Physical function device driver which expects VF device support, creating minimal impact on existing framework. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
e0024741 |
|
23-Jul-2020 |
Stefan Roese <sr@denx.de> |
pci: pci-uclass: Dynamically allocate the PCI regions Instead of using a fixed length pre-allocated array of regions, this patch moves to dynamically allocating the regions based on the number of available regions plus the necessary regions for DRAM banks. Since MAX_PCI_REGIONS is not needed any more, its removed completely with this patch. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Thierry Reding <treding@nvidia.com> Cc: Marek Vasut <marek.vasut+renesas@gmail.com>
|
#
143eb5b1 |
|
12-May-2020 |
Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
drivers: pci: add api to get dma regions Add api to get dma regions. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8b85dfc6 |
|
16-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: Avoid accessing seq directly At present various drivers etc. access the device's 'seq' member directly. This makes it harder to change the meaning of that member. Change access to go through a function instead. The drivers/i2c/lpc32xx_i2c.c file is left unchanged for now. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
caa4daa2 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename 'platdata' variables to just 'plat' We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
284d062e |
|
09-Sep-2020 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
pci: add a few ARI related defines Add a few defines related to PCI ARI configuration. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
51eeae91 |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add VF BAR map support for Enhanced Allocation Makes dm_pci_map_bar API available to map BAR for Virtual function PCI devices which support Enhanced Allocation. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
b8852dcf |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add support for Single-Root I/O Virtualization SR-IOV - Single Root I/O Virtualization PF - Physical Function VF - Virtual Function If SR-IOV capability is present, use it to initialize Virtual Function PCI device instances. pci_sriov_init function will read SR-IOV registers to create VF devices under the PF PCI device and also bind driver if available. This function needs to be invoked from Physical function device driver which expects VF device support, creating minimal impact on existing framework. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
e0024741 |
|
23-Jul-2020 |
Stefan Roese <sr@denx.de> |
pci: pci-uclass: Dynamically allocate the PCI regions Instead of using a fixed length pre-allocated array of regions, this patch moves to dynamically allocating the regions based on the number of available regions plus the necessary regions for DRAM banks. Since MAX_PCI_REGIONS is not needed any more, its removed completely with this patch. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Thierry Reding <treding@nvidia.com> Cc: Marek Vasut <marek.vasut+renesas@gmail.com>
|
#
143eb5b1 |
|
12-May-2020 |
Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
drivers: pci: add api to get dma regions Add api to get dma regions. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8b85dfc6 |
|
16-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: Avoid accessing seq directly At present various drivers etc. access the device's 'seq' member directly. This makes it harder to change the meaning of that member. Change access to go through a function instead. The drivers/i2c/lpc32xx_i2c.c file is left unchanged for now. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
caa4daa2 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename 'platdata' variables to just 'plat' We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
284d062e |
|
09-Sep-2020 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
pci: add a few ARI related defines Add a few defines related to PCI ARI configuration. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
51eeae91 |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add VF BAR map support for Enhanced Allocation Makes dm_pci_map_bar API available to map BAR for Virtual function PCI devices which support Enhanced Allocation. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
b8852dcf |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add support for Single-Root I/O Virtualization SR-IOV - Single Root I/O Virtualization PF - Physical Function VF - Virtual Function If SR-IOV capability is present, use it to initialize Virtual Function PCI device instances. pci_sriov_init function will read SR-IOV registers to create VF devices under the PF PCI device and also bind driver if available. This function needs to be invoked from Physical function device driver which expects VF device support, creating minimal impact on existing framework. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
e0024741 |
|
23-Jul-2020 |
Stefan Roese <sr@denx.de> |
pci: pci-uclass: Dynamically allocate the PCI regions Instead of using a fixed length pre-allocated array of regions, this patch moves to dynamically allocating the regions based on the number of available regions plus the necessary regions for DRAM banks. Since MAX_PCI_REGIONS is not needed any more, its removed completely with this patch. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Thierry Reding <treding@nvidia.com> Cc: Marek Vasut <marek.vasut+renesas@gmail.com>
|
#
143eb5b1 |
|
12-May-2020 |
Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
drivers: pci: add api to get dma regions Add api to get dma regions. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8b85dfc6 |
|
16-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: Avoid accessing seq directly At present various drivers etc. access the device's 'seq' member directly. This makes it harder to change the meaning of that member. Change access to go through a function instead. The drivers/i2c/lpc32xx_i2c.c file is left unchanged for now. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
caa4daa2 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename 'platdata' variables to just 'plat' We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
284d062e |
|
09-Sep-2020 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
pci: add a few ARI related defines Add a few defines related to PCI ARI configuration. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
51eeae91 |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add VF BAR map support for Enhanced Allocation Makes dm_pci_map_bar API available to map BAR for Virtual function PCI devices which support Enhanced Allocation. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
b8852dcf |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add support for Single-Root I/O Virtualization SR-IOV - Single Root I/O Virtualization PF - Physical Function VF - Virtual Function If SR-IOV capability is present, use it to initialize Virtual Function PCI device instances. pci_sriov_init function will read SR-IOV registers to create VF devices under the PF PCI device and also bind driver if available. This function needs to be invoked from Physical function device driver which expects VF device support, creating minimal impact on existing framework. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
e0024741 |
|
23-Jul-2020 |
Stefan Roese <sr@denx.de> |
pci: pci-uclass: Dynamically allocate the PCI regions Instead of using a fixed length pre-allocated array of regions, this patch moves to dynamically allocating the regions based on the number of available regions plus the necessary regions for DRAM banks. Since MAX_PCI_REGIONS is not needed any more, its removed completely with this patch. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Thierry Reding <treding@nvidia.com> Cc: Marek Vasut <marek.vasut+renesas@gmail.com>
|
#
143eb5b1 |
|
12-May-2020 |
Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
drivers: pci: add api to get dma regions Add api to get dma regions. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8b85dfc6 |
|
16-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: Avoid accessing seq directly At present various drivers etc. access the device's 'seq' member directly. This makes it harder to change the meaning of that member. Change access to go through a function instead. The drivers/i2c/lpc32xx_i2c.c file is left unchanged for now. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
caa4daa2 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename 'platdata' variables to just 'plat' We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
284d062e |
|
09-Sep-2020 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
pci: add a few ARI related defines Add a few defines related to PCI ARI configuration. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
51eeae91 |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add VF BAR map support for Enhanced Allocation Makes dm_pci_map_bar API available to map BAR for Virtual function PCI devices which support Enhanced Allocation. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
b8852dcf |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add support for Single-Root I/O Virtualization SR-IOV - Single Root I/O Virtualization PF - Physical Function VF - Virtual Function If SR-IOV capability is present, use it to initialize Virtual Function PCI device instances. pci_sriov_init function will read SR-IOV registers to create VF devices under the PF PCI device and also bind driver if available. This function needs to be invoked from Physical function device driver which expects VF device support, creating minimal impact on existing framework. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
e0024741 |
|
23-Jul-2020 |
Stefan Roese <sr@denx.de> |
pci: pci-uclass: Dynamically allocate the PCI regions Instead of using a fixed length pre-allocated array of regions, this patch moves to dynamically allocating the regions based on the number of available regions plus the necessary regions for DRAM banks. Since MAX_PCI_REGIONS is not needed any more, its removed completely with this patch. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Thierry Reding <treding@nvidia.com> Cc: Marek Vasut <marek.vasut+renesas@gmail.com>
|
#
143eb5b1 |
|
12-May-2020 |
Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
drivers: pci: add api to get dma regions Add api to get dma regions. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8b85dfc6 |
|
16-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: Avoid accessing seq directly At present various drivers etc. access the device's 'seq' member directly. This makes it harder to change the meaning of that member. Change access to go through a function instead. The drivers/i2c/lpc32xx_i2c.c file is left unchanged for now. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
caa4daa2 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename 'platdata' variables to just 'plat' We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
284d062e |
|
09-Sep-2020 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
pci: add a few ARI related defines Add a few defines related to PCI ARI configuration. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
51eeae91 |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add VF BAR map support for Enhanced Allocation Makes dm_pci_map_bar API available to map BAR for Virtual function PCI devices which support Enhanced Allocation. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
b8852dcf |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add support for Single-Root I/O Virtualization SR-IOV - Single Root I/O Virtualization PF - Physical Function VF - Virtual Function If SR-IOV capability is present, use it to initialize Virtual Function PCI device instances. pci_sriov_init function will read SR-IOV registers to create VF devices under the PF PCI device and also bind driver if available. This function needs to be invoked from Physical function device driver which expects VF device support, creating minimal impact on existing framework. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
e0024741 |
|
23-Jul-2020 |
Stefan Roese <sr@denx.de> |
pci: pci-uclass: Dynamically allocate the PCI regions Instead of using a fixed length pre-allocated array of regions, this patch moves to dynamically allocating the regions based on the number of available regions plus the necessary regions for DRAM banks. Since MAX_PCI_REGIONS is not needed any more, its removed completely with this patch. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Thierry Reding <treding@nvidia.com> Cc: Marek Vasut <marek.vasut+renesas@gmail.com>
|
#
143eb5b1 |
|
12-May-2020 |
Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
drivers: pci: add api to get dma regions Add api to get dma regions. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8b85dfc6 |
|
16-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: Avoid accessing seq directly At present various drivers etc. access the device's 'seq' member directly. This makes it harder to change the meaning of that member. Change access to go through a function instead. The drivers/i2c/lpc32xx_i2c.c file is left unchanged for now. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
caa4daa2 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename 'platdata' variables to just 'plat' We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
284d062e |
|
09-Sep-2020 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
pci: add a few ARI related defines Add a few defines related to PCI ARI configuration. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
51eeae91 |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add VF BAR map support for Enhanced Allocation Makes dm_pci_map_bar API available to map BAR for Virtual function PCI devices which support Enhanced Allocation. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
b8852dcf |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add support for Single-Root I/O Virtualization SR-IOV - Single Root I/O Virtualization PF - Physical Function VF - Virtual Function If SR-IOV capability is present, use it to initialize Virtual Function PCI device instances. pci_sriov_init function will read SR-IOV registers to create VF devices under the PF PCI device and also bind driver if available. This function needs to be invoked from Physical function device driver which expects VF device support, creating minimal impact on existing framework. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
e0024741 |
|
23-Jul-2020 |
Stefan Roese <sr@denx.de> |
pci: pci-uclass: Dynamically allocate the PCI regions Instead of using a fixed length pre-allocated array of regions, this patch moves to dynamically allocating the regions based on the number of available regions plus the necessary regions for DRAM banks. Since MAX_PCI_REGIONS is not needed any more, its removed completely with this patch. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Thierry Reding <treding@nvidia.com> Cc: Marek Vasut <marek.vasut+renesas@gmail.com>
|
#
143eb5b1 |
|
12-May-2020 |
Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
drivers: pci: add api to get dma regions Add api to get dma regions. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8b85dfc6 |
|
16-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: Avoid accessing seq directly At present various drivers etc. access the device's 'seq' member directly. This makes it harder to change the meaning of that member. Change access to go through a function instead. The drivers/i2c/lpc32xx_i2c.c file is left unchanged for now. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
caa4daa2 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename 'platdata' variables to just 'plat' We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
284d062e |
|
09-Sep-2020 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
pci: add a few ARI related defines Add a few defines related to PCI ARI configuration. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
51eeae91 |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add VF BAR map support for Enhanced Allocation Makes dm_pci_map_bar API available to map BAR for Virtual function PCI devices which support Enhanced Allocation. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
b8852dcf |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add support for Single-Root I/O Virtualization SR-IOV - Single Root I/O Virtualization PF - Physical Function VF - Virtual Function If SR-IOV capability is present, use it to initialize Virtual Function PCI device instances. pci_sriov_init function will read SR-IOV registers to create VF devices under the PF PCI device and also bind driver if available. This function needs to be invoked from Physical function device driver which expects VF device support, creating minimal impact on existing framework. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
e0024741 |
|
23-Jul-2020 |
Stefan Roese <sr@denx.de> |
pci: pci-uclass: Dynamically allocate the PCI regions Instead of using a fixed length pre-allocated array of regions, this patch moves to dynamically allocating the regions based on the number of available regions plus the necessary regions for DRAM banks. Since MAX_PCI_REGIONS is not needed any more, its removed completely with this patch. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Thierry Reding <treding@nvidia.com> Cc: Marek Vasut <marek.vasut+renesas@gmail.com>
|
#
143eb5b1 |
|
12-May-2020 |
Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
drivers: pci: add api to get dma regions Add api to get dma regions. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8b85dfc6 |
|
16-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: Avoid accessing seq directly At present various drivers etc. access the device's 'seq' member directly. This makes it harder to change the meaning of that member. Change access to go through a function instead. The drivers/i2c/lpc32xx_i2c.c file is left unchanged for now. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
caa4daa2 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename 'platdata' variables to just 'plat' We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
284d062e |
|
09-Sep-2020 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
pci: add a few ARI related defines Add a few defines related to PCI ARI configuration. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
51eeae91 |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add VF BAR map support for Enhanced Allocation Makes dm_pci_map_bar API available to map BAR for Virtual function PCI devices which support Enhanced Allocation. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
b8852dcf |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add support for Single-Root I/O Virtualization SR-IOV - Single Root I/O Virtualization PF - Physical Function VF - Virtual Function If SR-IOV capability is present, use it to initialize Virtual Function PCI device instances. pci_sriov_init function will read SR-IOV registers to create VF devices under the PF PCI device and also bind driver if available. This function needs to be invoked from Physical function device driver which expects VF device support, creating minimal impact on existing framework. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
e0024741 |
|
23-Jul-2020 |
Stefan Roese <sr@denx.de> |
pci: pci-uclass: Dynamically allocate the PCI regions Instead of using a fixed length pre-allocated array of regions, this patch moves to dynamically allocating the regions based on the number of available regions plus the necessary regions for DRAM banks. Since MAX_PCI_REGIONS is not needed any more, its removed completely with this patch. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Thierry Reding <treding@nvidia.com> Cc: Marek Vasut <marek.vasut+renesas@gmail.com>
|
#
143eb5b1 |
|
12-May-2020 |
Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
drivers: pci: add api to get dma regions Add api to get dma regions. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8b85dfc6 |
|
16-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: Avoid accessing seq directly At present various drivers etc. access the device's 'seq' member directly. This makes it harder to change the meaning of that member. Change access to go through a function instead. The drivers/i2c/lpc32xx_i2c.c file is left unchanged for now. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
caa4daa2 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename 'platdata' variables to just 'plat' We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
284d062e |
|
09-Sep-2020 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
pci: add a few ARI related defines Add a few defines related to PCI ARI configuration. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
51eeae91 |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add VF BAR map support for Enhanced Allocation Makes dm_pci_map_bar API available to map BAR for Virtual function PCI devices which support Enhanced Allocation. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
b8852dcf |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add support for Single-Root I/O Virtualization SR-IOV - Single Root I/O Virtualization PF - Physical Function VF - Virtual Function If SR-IOV capability is present, use it to initialize Virtual Function PCI device instances. pci_sriov_init function will read SR-IOV registers to create VF devices under the PF PCI device and also bind driver if available. This function needs to be invoked from Physical function device driver which expects VF device support, creating minimal impact on existing framework. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
e0024741 |
|
23-Jul-2020 |
Stefan Roese <sr@denx.de> |
pci: pci-uclass: Dynamically allocate the PCI regions Instead of using a fixed length pre-allocated array of regions, this patch moves to dynamically allocating the regions based on the number of available regions plus the necessary regions for DRAM banks. Since MAX_PCI_REGIONS is not needed any more, its removed completely with this patch. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Thierry Reding <treding@nvidia.com> Cc: Marek Vasut <marek.vasut+renesas@gmail.com>
|
#
143eb5b1 |
|
12-May-2020 |
Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
drivers: pci: add api to get dma regions Add api to get dma regions. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8b85dfc6 |
|
16-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: Avoid accessing seq directly At present various drivers etc. access the device's 'seq' member directly. This makes it harder to change the meaning of that member. Change access to go through a function instead. The drivers/i2c/lpc32xx_i2c.c file is left unchanged for now. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
caa4daa2 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename 'platdata' variables to just 'plat' We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
284d062e |
|
09-Sep-2020 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
pci: add a few ARI related defines Add a few defines related to PCI ARI configuration. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
51eeae91 |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add VF BAR map support for Enhanced Allocation Makes dm_pci_map_bar API available to map BAR for Virtual function PCI devices which support Enhanced Allocation. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
b8852dcf |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add support for Single-Root I/O Virtualization SR-IOV - Single Root I/O Virtualization PF - Physical Function VF - Virtual Function If SR-IOV capability is present, use it to initialize Virtual Function PCI device instances. pci_sriov_init function will read SR-IOV registers to create VF devices under the PF PCI device and also bind driver if available. This function needs to be invoked from Physical function device driver which expects VF device support, creating minimal impact on existing framework. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
e0024741 |
|
23-Jul-2020 |
Stefan Roese <sr@denx.de> |
pci: pci-uclass: Dynamically allocate the PCI regions Instead of using a fixed length pre-allocated array of regions, this patch moves to dynamically allocating the regions based on the number of available regions plus the necessary regions for DRAM banks. Since MAX_PCI_REGIONS is not needed any more, its removed completely with this patch. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Thierry Reding <treding@nvidia.com> Cc: Marek Vasut <marek.vasut+renesas@gmail.com>
|
#
143eb5b1 |
|
12-May-2020 |
Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
drivers: pci: add api to get dma regions Add api to get dma regions. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8b85dfc6 |
|
16-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: Avoid accessing seq directly At present various drivers etc. access the device's 'seq' member directly. This makes it harder to change the meaning of that member. Change access to go through a function instead. The drivers/i2c/lpc32xx_i2c.c file is left unchanged for now. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
caa4daa2 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename 'platdata' variables to just 'plat' We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
284d062e |
|
09-Sep-2020 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
pci: add a few ARI related defines Add a few defines related to PCI ARI configuration. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
51eeae91 |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add VF BAR map support for Enhanced Allocation Makes dm_pci_map_bar API available to map BAR for Virtual function PCI devices which support Enhanced Allocation. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
b8852dcf |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add support for Single-Root I/O Virtualization SR-IOV - Single Root I/O Virtualization PF - Physical Function VF - Virtual Function If SR-IOV capability is present, use it to initialize Virtual Function PCI device instances. pci_sriov_init function will read SR-IOV registers to create VF devices under the PF PCI device and also bind driver if available. This function needs to be invoked from Physical function device driver which expects VF device support, creating minimal impact on existing framework. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
e0024741 |
|
23-Jul-2020 |
Stefan Roese <sr@denx.de> |
pci: pci-uclass: Dynamically allocate the PCI regions Instead of using a fixed length pre-allocated array of regions, this patch moves to dynamically allocating the regions based on the number of available regions plus the necessary regions for DRAM banks. Since MAX_PCI_REGIONS is not needed any more, its removed completely with this patch. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Thierry Reding <treding@nvidia.com> Cc: Marek Vasut <marek.vasut+renesas@gmail.com>
|
#
143eb5b1 |
|
12-May-2020 |
Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
drivers: pci: add api to get dma regions Add api to get dma regions. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8b85dfc6 |
|
16-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: Avoid accessing seq directly At present various drivers etc. access the device's 'seq' member directly. This makes it harder to change the meaning of that member. Change access to go through a function instead. The drivers/i2c/lpc32xx_i2c.c file is left unchanged for now. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
caa4daa2 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename 'platdata' variables to just 'plat' We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
284d062e |
|
09-Sep-2020 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
pci: add a few ARI related defines Add a few defines related to PCI ARI configuration. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
51eeae91 |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add VF BAR map support for Enhanced Allocation Makes dm_pci_map_bar API available to map BAR for Virtual function PCI devices which support Enhanced Allocation. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
b8852dcf |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add support for Single-Root I/O Virtualization SR-IOV - Single Root I/O Virtualization PF - Physical Function VF - Virtual Function If SR-IOV capability is present, use it to initialize Virtual Function PCI device instances. pci_sriov_init function will read SR-IOV registers to create VF devices under the PF PCI device and also bind driver if available. This function needs to be invoked from Physical function device driver which expects VF device support, creating minimal impact on existing framework. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
e0024741 |
|
23-Jul-2020 |
Stefan Roese <sr@denx.de> |
pci: pci-uclass: Dynamically allocate the PCI regions Instead of using a fixed length pre-allocated array of regions, this patch moves to dynamically allocating the regions based on the number of available regions plus the necessary regions for DRAM banks. Since MAX_PCI_REGIONS is not needed any more, its removed completely with this patch. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Thierry Reding <treding@nvidia.com> Cc: Marek Vasut <marek.vasut+renesas@gmail.com>
|
#
143eb5b1 |
|
12-May-2020 |
Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
drivers: pci: add api to get dma regions Add api to get dma regions. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8b85dfc6 |
|
16-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: Avoid accessing seq directly At present various drivers etc. access the device's 'seq' member directly. This makes it harder to change the meaning of that member. Change access to go through a function instead. The drivers/i2c/lpc32xx_i2c.c file is left unchanged for now. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
caa4daa2 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename 'platdata' variables to just 'plat' We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
284d062e |
|
09-Sep-2020 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
pci: add a few ARI related defines Add a few defines related to PCI ARI configuration. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
51eeae91 |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add VF BAR map support for Enhanced Allocation Makes dm_pci_map_bar API available to map BAR for Virtual function PCI devices which support Enhanced Allocation. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
b8852dcf |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add support for Single-Root I/O Virtualization SR-IOV - Single Root I/O Virtualization PF - Physical Function VF - Virtual Function If SR-IOV capability is present, use it to initialize Virtual Function PCI device instances. pci_sriov_init function will read SR-IOV registers to create VF devices under the PF PCI device and also bind driver if available. This function needs to be invoked from Physical function device driver which expects VF device support, creating minimal impact on existing framework. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
e0024741 |
|
23-Jul-2020 |
Stefan Roese <sr@denx.de> |
pci: pci-uclass: Dynamically allocate the PCI regions Instead of using a fixed length pre-allocated array of regions, this patch moves to dynamically allocating the regions based on the number of available regions plus the necessary regions for DRAM banks. Since MAX_PCI_REGIONS is not needed any more, its removed completely with this patch. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Thierry Reding <treding@nvidia.com> Cc: Marek Vasut <marek.vasut+renesas@gmail.com>
|
#
143eb5b1 |
|
12-May-2020 |
Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
drivers: pci: add api to get dma regions Add api to get dma regions. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8b85dfc6 |
|
16-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: Avoid accessing seq directly At present various drivers etc. access the device's 'seq' member directly. This makes it harder to change the meaning of that member. Change access to go through a function instead. The drivers/i2c/lpc32xx_i2c.c file is left unchanged for now. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
caa4daa2 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename 'platdata' variables to just 'plat' We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
284d062e |
|
09-Sep-2020 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
pci: add a few ARI related defines Add a few defines related to PCI ARI configuration. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
51eeae91 |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add VF BAR map support for Enhanced Allocation Makes dm_pci_map_bar API available to map BAR for Virtual function PCI devices which support Enhanced Allocation. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
b8852dcf |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add support for Single-Root I/O Virtualization SR-IOV - Single Root I/O Virtualization PF - Physical Function VF - Virtual Function If SR-IOV capability is present, use it to initialize Virtual Function PCI device instances. pci_sriov_init function will read SR-IOV registers to create VF devices under the PF PCI device and also bind driver if available. This function needs to be invoked from Physical function device driver which expects VF device support, creating minimal impact on existing framework. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
e0024741 |
|
23-Jul-2020 |
Stefan Roese <sr@denx.de> |
pci: pci-uclass: Dynamically allocate the PCI regions Instead of using a fixed length pre-allocated array of regions, this patch moves to dynamically allocating the regions based on the number of available regions plus the necessary regions for DRAM banks. Since MAX_PCI_REGIONS is not needed any more, its removed completely with this patch. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Thierry Reding <treding@nvidia.com> Cc: Marek Vasut <marek.vasut+renesas@gmail.com>
|
#
143eb5b1 |
|
12-May-2020 |
Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
drivers: pci: add api to get dma regions Add api to get dma regions. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8b85dfc6 |
|
16-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: Avoid accessing seq directly At present various drivers etc. access the device's 'seq' member directly. This makes it harder to change the meaning of that member. Change access to go through a function instead. The drivers/i2c/lpc32xx_i2c.c file is left unchanged for now. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
8a8d24bd |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
caa4daa2 |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename 'platdata' variables to just 'plat' We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
284d062e |
|
09-Sep-2020 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
pci: add a few ARI related defines Add a few defines related to PCI ARI configuration. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
51eeae91 |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add VF BAR map support for Enhanced Allocation Makes dm_pci_map_bar API available to map BAR for Virtual function PCI devices which support Enhanced Allocation. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
b8852dcf |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add support for Single-Root I/O Virtualization SR-IOV - Single Root I/O Virtualization PF - Physical Function VF - Virtual Function If SR-IOV capability is present, use it to initialize Virtual Function PCI device instances. pci_sriov_init function will read SR-IOV registers to create VF devices under the PF PCI device and also bind driver if available. This function needs to be invoked from Physical function device driver which expects VF device support, creating minimal impact on existing framework. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
e0024741 |
|
23-Jul-2020 |
Stefan Roese <sr@denx.de> |
pci: pci-uclass: Dynamically allocate the PCI regions Instead of using a fixed length pre-allocated array of regions, this patch moves to dynamically allocating the regions based on the number of available regions plus the necessary regions for DRAM banks. Since MAX_PCI_REGIONS is not needed any more, its removed completely with this patch. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Thierry Reding <treding@nvidia.com> Cc: Marek Vasut <marek.vasut+renesas@gmail.com>
|
#
143eb5b1 |
|
12-May-2020 |
Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
drivers: pci: add api to get dma regions Add api to get dma regions. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
284d062e |
|
09-Sep-2020 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
pci: add a few ARI related defines Add a few defines related to PCI ARI configuration. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
51eeae91 |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add VF BAR map support for Enhanced Allocation Makes dm_pci_map_bar API available to map BAR for Virtual function PCI devices which support Enhanced Allocation. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
b8852dcf |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add support for Single-Root I/O Virtualization SR-IOV - Single Root I/O Virtualization PF - Physical Function VF - Virtual Function If SR-IOV capability is present, use it to initialize Virtual Function PCI device instances. pci_sriov_init function will read SR-IOV registers to create VF devices under the PF PCI device and also bind driver if available. This function needs to be invoked from Physical function device driver which expects VF device support, creating minimal impact on existing framework. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
e0024741 |
|
23-Jul-2020 |
Stefan Roese <sr@denx.de> |
pci: pci-uclass: Dynamically allocate the PCI regions Instead of using a fixed length pre-allocated array of regions, this patch moves to dynamically allocating the regions based on the number of available regions plus the necessary regions for DRAM banks. Since MAX_PCI_REGIONS is not needed any more, its removed completely with this patch. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Thierry Reding <treding@nvidia.com> Cc: Marek Vasut <marek.vasut+renesas@gmail.com>
|
#
143eb5b1 |
|
12-May-2020 |
Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
drivers: pci: add api to get dma regions Add api to get dma regions. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
284d062e |
|
09-Sep-2020 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
pci: add a few ARI related defines Add a few defines related to PCI ARI configuration. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
51eeae91 |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add VF BAR map support for Enhanced Allocation Makes dm_pci_map_bar API available to map BAR for Virtual function PCI devices which support Enhanced Allocation. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
b8852dcf |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add support for Single-Root I/O Virtualization SR-IOV - Single Root I/O Virtualization PF - Physical Function VF - Virtual Function If SR-IOV capability is present, use it to initialize Virtual Function PCI device instances. pci_sriov_init function will read SR-IOV registers to create VF devices under the PF PCI device and also bind driver if available. This function needs to be invoked from Physical function device driver which expects VF device support, creating minimal impact on existing framework. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
e0024741 |
|
23-Jul-2020 |
Stefan Roese <sr@denx.de> |
pci: pci-uclass: Dynamically allocate the PCI regions Instead of using a fixed length pre-allocated array of regions, this patch moves to dynamically allocating the regions based on the number of available regions plus the necessary regions for DRAM banks. Since MAX_PCI_REGIONS is not needed any more, its removed completely with this patch. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Thierry Reding <treding@nvidia.com> Cc: Marek Vasut <marek.vasut+renesas@gmail.com>
|
#
143eb5b1 |
|
12-May-2020 |
Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
drivers: pci: add api to get dma regions Add api to get dma regions. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
284d062e |
|
09-Sep-2020 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
pci: add a few ARI related defines Add a few defines related to PCI ARI configuration. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
51eeae91 |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add VF BAR map support for Enhanced Allocation Makes dm_pci_map_bar API available to map BAR for Virtual function PCI devices which support Enhanced Allocation. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
b8852dcf |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add support for Single-Root I/O Virtualization SR-IOV - Single Root I/O Virtualization PF - Physical Function VF - Virtual Function If SR-IOV capability is present, use it to initialize Virtual Function PCI device instances. pci_sriov_init function will read SR-IOV registers to create VF devices under the PF PCI device and also bind driver if available. This function needs to be invoked from Physical function device driver which expects VF device support, creating minimal impact on existing framework. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
e0024741 |
|
23-Jul-2020 |
Stefan Roese <sr@denx.de> |
pci: pci-uclass: Dynamically allocate the PCI regions Instead of using a fixed length pre-allocated array of regions, this patch moves to dynamically allocating the regions based on the number of available regions plus the necessary regions for DRAM banks. Since MAX_PCI_REGIONS is not needed any more, its removed completely with this patch. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Thierry Reding <treding@nvidia.com> Cc: Marek Vasut <marek.vasut+renesas@gmail.com>
|
#
143eb5b1 |
|
12-May-2020 |
Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
drivers: pci: add api to get dma regions Add api to get dma regions. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
284d062e |
|
09-Sep-2020 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
pci: add a few ARI related defines Add a few defines related to PCI ARI configuration. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
51eeae91 |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add VF BAR map support for Enhanced Allocation Makes dm_pci_map_bar API available to map BAR for Virtual function PCI devices which support Enhanced Allocation. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
b8852dcf |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add support for Single-Root I/O Virtualization SR-IOV - Single Root I/O Virtualization PF - Physical Function VF - Virtual Function If SR-IOV capability is present, use it to initialize Virtual Function PCI device instances. pci_sriov_init function will read SR-IOV registers to create VF devices under the PF PCI device and also bind driver if available. This function needs to be invoked from Physical function device driver which expects VF device support, creating minimal impact on existing framework. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
e0024741 |
|
23-Jul-2020 |
Stefan Roese <sr@denx.de> |
pci: pci-uclass: Dynamically allocate the PCI regions Instead of using a fixed length pre-allocated array of regions, this patch moves to dynamically allocating the regions based on the number of available regions plus the necessary regions for DRAM banks. Since MAX_PCI_REGIONS is not needed any more, its removed completely with this patch. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Thierry Reding <treding@nvidia.com> Cc: Marek Vasut <marek.vasut+renesas@gmail.com>
|
#
143eb5b1 |
|
12-May-2020 |
Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
drivers: pci: add api to get dma regions Add api to get dma regions. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
284d062e |
|
09-Sep-2020 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
pci: add a few ARI related defines Add a few defines related to PCI ARI configuration. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
51eeae91 |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add VF BAR map support for Enhanced Allocation Makes dm_pci_map_bar API available to map BAR for Virtual function PCI devices which support Enhanced Allocation. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
b8852dcf |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add support for Single-Root I/O Virtualization SR-IOV - Single Root I/O Virtualization PF - Physical Function VF - Virtual Function If SR-IOV capability is present, use it to initialize Virtual Function PCI device instances. pci_sriov_init function will read SR-IOV registers to create VF devices under the PF PCI device and also bind driver if available. This function needs to be invoked from Physical function device driver which expects VF device support, creating minimal impact on existing framework. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
e0024741 |
|
23-Jul-2020 |
Stefan Roese <sr@denx.de> |
pci: pci-uclass: Dynamically allocate the PCI regions Instead of using a fixed length pre-allocated array of regions, this patch moves to dynamically allocating the regions based on the number of available regions plus the necessary regions for DRAM banks. Since MAX_PCI_REGIONS is not needed any more, its removed completely with this patch. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Thierry Reding <treding@nvidia.com> Cc: Marek Vasut <marek.vasut+renesas@gmail.com>
|
#
143eb5b1 |
|
12-May-2020 |
Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
drivers: pci: add api to get dma regions Add api to get dma regions. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
284d062e |
|
09-Sep-2020 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
pci: add a few ARI related defines Add a few defines related to PCI ARI configuration. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
51eeae91 |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add VF BAR map support for Enhanced Allocation Makes dm_pci_map_bar API available to map BAR for Virtual function PCI devices which support Enhanced Allocation. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
b8852dcf |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add support for Single-Root I/O Virtualization SR-IOV - Single Root I/O Virtualization PF - Physical Function VF - Virtual Function If SR-IOV capability is present, use it to initialize Virtual Function PCI device instances. pci_sriov_init function will read SR-IOV registers to create VF devices under the PF PCI device and also bind driver if available. This function needs to be invoked from Physical function device driver which expects VF device support, creating minimal impact on existing framework. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
e0024741 |
|
23-Jul-2020 |
Stefan Roese <sr@denx.de> |
pci: pci-uclass: Dynamically allocate the PCI regions Instead of using a fixed length pre-allocated array of regions, this patch moves to dynamically allocating the regions based on the number of available regions plus the necessary regions for DRAM banks. Since MAX_PCI_REGIONS is not needed any more, its removed completely with this patch. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Thierry Reding <treding@nvidia.com> Cc: Marek Vasut <marek.vasut+renesas@gmail.com>
|
#
143eb5b1 |
|
12-May-2020 |
Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
drivers: pci: add api to get dma regions Add api to get dma regions. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
284d062e |
|
09-Sep-2020 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
pci: add a few ARI related defines Add a few defines related to PCI ARI configuration. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
51eeae91 |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add VF BAR map support for Enhanced Allocation Makes dm_pci_map_bar API available to map BAR for Virtual function PCI devices which support Enhanced Allocation. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
b8852dcf |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add support for Single-Root I/O Virtualization SR-IOV - Single Root I/O Virtualization PF - Physical Function VF - Virtual Function If SR-IOV capability is present, use it to initialize Virtual Function PCI device instances. pci_sriov_init function will read SR-IOV registers to create VF devices under the PF PCI device and also bind driver if available. This function needs to be invoked from Physical function device driver which expects VF device support, creating minimal impact on existing framework. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
e0024741 |
|
23-Jul-2020 |
Stefan Roese <sr@denx.de> |
pci: pci-uclass: Dynamically allocate the PCI regions Instead of using a fixed length pre-allocated array of regions, this patch moves to dynamically allocating the regions based on the number of available regions plus the necessary regions for DRAM banks. Since MAX_PCI_REGIONS is not needed any more, its removed completely with this patch. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Thierry Reding <treding@nvidia.com> Cc: Marek Vasut <marek.vasut+renesas@gmail.com>
|
#
143eb5b1 |
|
12-May-2020 |
Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
drivers: pci: add api to get dma regions Add api to get dma regions. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
284d062e |
|
09-Sep-2020 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
pci: add a few ARI related defines Add a few defines related to PCI ARI configuration. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
51eeae91 |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add VF BAR map support for Enhanced Allocation Makes dm_pci_map_bar API available to map BAR for Virtual function PCI devices which support Enhanced Allocation. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
b8852dcf |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add support for Single-Root I/O Virtualization SR-IOV - Single Root I/O Virtualization PF - Physical Function VF - Virtual Function If SR-IOV capability is present, use it to initialize Virtual Function PCI device instances. pci_sriov_init function will read SR-IOV registers to create VF devices under the PF PCI device and also bind driver if available. This function needs to be invoked from Physical function device driver which expects VF device support, creating minimal impact on existing framework. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
e0024741 |
|
23-Jul-2020 |
Stefan Roese <sr@denx.de> |
pci: pci-uclass: Dynamically allocate the PCI regions Instead of using a fixed length pre-allocated array of regions, this patch moves to dynamically allocating the regions based on the number of available regions plus the necessary regions for DRAM banks. Since MAX_PCI_REGIONS is not needed any more, its removed completely with this patch. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Thierry Reding <treding@nvidia.com> Cc: Marek Vasut <marek.vasut+renesas@gmail.com>
|
#
143eb5b1 |
|
12-May-2020 |
Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
drivers: pci: add api to get dma regions Add api to get dma regions. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
284d062e |
|
09-Sep-2020 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
pci: add a few ARI related defines Add a few defines related to PCI ARI configuration. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
51eeae91 |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add VF BAR map support for Enhanced Allocation Makes dm_pci_map_bar API available to map BAR for Virtual function PCI devices which support Enhanced Allocation. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
b8852dcf |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add support for Single-Root I/O Virtualization SR-IOV - Single Root I/O Virtualization PF - Physical Function VF - Virtual Function If SR-IOV capability is present, use it to initialize Virtual Function PCI device instances. pci_sriov_init function will read SR-IOV registers to create VF devices under the PF PCI device and also bind driver if available. This function needs to be invoked from Physical function device driver which expects VF device support, creating minimal impact on existing framework. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
e0024741 |
|
23-Jul-2020 |
Stefan Roese <sr@denx.de> |
pci: pci-uclass: Dynamically allocate the PCI regions Instead of using a fixed length pre-allocated array of regions, this patch moves to dynamically allocating the regions based on the number of available regions plus the necessary regions for DRAM banks. Since MAX_PCI_REGIONS is not needed any more, its removed completely with this patch. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Thierry Reding <treding@nvidia.com> Cc: Marek Vasut <marek.vasut+renesas@gmail.com>
|
#
143eb5b1 |
|
12-May-2020 |
Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
drivers: pci: add api to get dma regions Add api to get dma regions. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
284d062e |
|
09-Sep-2020 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
pci: add a few ARI related defines Add a few defines related to PCI ARI configuration. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
51eeae91 |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add VF BAR map support for Enhanced Allocation Makes dm_pci_map_bar API available to map BAR for Virtual function PCI devices which support Enhanced Allocation. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
b8852dcf |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add support for Single-Root I/O Virtualization SR-IOV - Single Root I/O Virtualization PF - Physical Function VF - Virtual Function If SR-IOV capability is present, use it to initialize Virtual Function PCI device instances. pci_sriov_init function will read SR-IOV registers to create VF devices under the PF PCI device and also bind driver if available. This function needs to be invoked from Physical function device driver which expects VF device support, creating minimal impact on existing framework. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
e0024741 |
|
23-Jul-2020 |
Stefan Roese <sr@denx.de> |
pci: pci-uclass: Dynamically allocate the PCI regions Instead of using a fixed length pre-allocated array of regions, this patch moves to dynamically allocating the regions based on the number of available regions plus the necessary regions for DRAM banks. Since MAX_PCI_REGIONS is not needed any more, its removed completely with this patch. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Thierry Reding <treding@nvidia.com> Cc: Marek Vasut <marek.vasut+renesas@gmail.com>
|
#
143eb5b1 |
|
12-May-2020 |
Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
drivers: pci: add api to get dma regions Add api to get dma regions. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
284d062e |
|
09-Sep-2020 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
pci: add a few ARI related defines Add a few defines related to PCI ARI configuration. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
51eeae91 |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add VF BAR map support for Enhanced Allocation Makes dm_pci_map_bar API available to map BAR for Virtual function PCI devices which support Enhanced Allocation. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
b8852dcf |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add support for Single-Root I/O Virtualization SR-IOV - Single Root I/O Virtualization PF - Physical Function VF - Virtual Function If SR-IOV capability is present, use it to initialize Virtual Function PCI device instances. pci_sriov_init function will read SR-IOV registers to create VF devices under the PF PCI device and also bind driver if available. This function needs to be invoked from Physical function device driver which expects VF device support, creating minimal impact on existing framework. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
e0024741 |
|
23-Jul-2020 |
Stefan Roese <sr@denx.de> |
pci: pci-uclass: Dynamically allocate the PCI regions Instead of using a fixed length pre-allocated array of regions, this patch moves to dynamically allocating the regions based on the number of available regions plus the necessary regions for DRAM banks. Since MAX_PCI_REGIONS is not needed any more, its removed completely with this patch. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Thierry Reding <treding@nvidia.com> Cc: Marek Vasut <marek.vasut+renesas@gmail.com>
|
#
143eb5b1 |
|
12-May-2020 |
Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
drivers: pci: add api to get dma regions Add api to get dma regions. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
284d062e |
|
09-Sep-2020 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
pci: add a few ARI related defines Add a few defines related to PCI ARI configuration. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
51eeae91 |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add VF BAR map support for Enhanced Allocation Makes dm_pci_map_bar API available to map BAR for Virtual function PCI devices which support Enhanced Allocation. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
b8852dcf |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add support for Single-Root I/O Virtualization SR-IOV - Single Root I/O Virtualization PF - Physical Function VF - Virtual Function If SR-IOV capability is present, use it to initialize Virtual Function PCI device instances. pci_sriov_init function will read SR-IOV registers to create VF devices under the PF PCI device and also bind driver if available. This function needs to be invoked from Physical function device driver which expects VF device support, creating minimal impact on existing framework. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
e0024741 |
|
23-Jul-2020 |
Stefan Roese <sr@denx.de> |
pci: pci-uclass: Dynamically allocate the PCI regions Instead of using a fixed length pre-allocated array of regions, this patch moves to dynamically allocating the regions based on the number of available regions plus the necessary regions for DRAM banks. Since MAX_PCI_REGIONS is not needed any more, its removed completely with this patch. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Thierry Reding <treding@nvidia.com> Cc: Marek Vasut <marek.vasut+renesas@gmail.com>
|
#
143eb5b1 |
|
12-May-2020 |
Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
drivers: pci: add api to get dma regions Add api to get dma regions. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
284d062e |
|
09-Sep-2020 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
pci: add a few ARI related defines Add a few defines related to PCI ARI configuration. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
51eeae91 |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add VF BAR map support for Enhanced Allocation Makes dm_pci_map_bar API available to map BAR for Virtual function PCI devices which support Enhanced Allocation. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
b8852dcf |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add support for Single-Root I/O Virtualization SR-IOV - Single Root I/O Virtualization PF - Physical Function VF - Virtual Function If SR-IOV capability is present, use it to initialize Virtual Function PCI device instances. pci_sriov_init function will read SR-IOV registers to create VF devices under the PF PCI device and also bind driver if available. This function needs to be invoked from Physical function device driver which expects VF device support, creating minimal impact on existing framework. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
e0024741 |
|
23-Jul-2020 |
Stefan Roese <sr@denx.de> |
pci: pci-uclass: Dynamically allocate the PCI regions Instead of using a fixed length pre-allocated array of regions, this patch moves to dynamically allocating the regions based on the number of available regions plus the necessary regions for DRAM banks. Since MAX_PCI_REGIONS is not needed any more, its removed completely with this patch. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Thierry Reding <treding@nvidia.com> Cc: Marek Vasut <marek.vasut+renesas@gmail.com>
|
#
143eb5b1 |
|
12-May-2020 |
Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
drivers: pci: add api to get dma regions Add api to get dma regions. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
284d062e |
|
09-Sep-2020 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
pci: add a few ARI related defines Add a few defines related to PCI ARI configuration. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
51eeae91 |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add VF BAR map support for Enhanced Allocation Makes dm_pci_map_bar API available to map BAR for Virtual function PCI devices which support Enhanced Allocation. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
b8852dcf |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add support for Single-Root I/O Virtualization SR-IOV - Single Root I/O Virtualization PF - Physical Function VF - Virtual Function If SR-IOV capability is present, use it to initialize Virtual Function PCI device instances. pci_sriov_init function will read SR-IOV registers to create VF devices under the PF PCI device and also bind driver if available. This function needs to be invoked from Physical function device driver which expects VF device support, creating minimal impact on existing framework. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
e0024741 |
|
23-Jul-2020 |
Stefan Roese <sr@denx.de> |
pci: pci-uclass: Dynamically allocate the PCI regions Instead of using a fixed length pre-allocated array of regions, this patch moves to dynamically allocating the regions based on the number of available regions plus the necessary regions for DRAM banks. Since MAX_PCI_REGIONS is not needed any more, its removed completely with this patch. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Thierry Reding <treding@nvidia.com> Cc: Marek Vasut <marek.vasut+renesas@gmail.com>
|
#
143eb5b1 |
|
12-May-2020 |
Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
drivers: pci: add api to get dma regions Add api to get dma regions. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
284d062e |
|
09-Sep-2020 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
pci: add a few ARI related defines Add a few defines related to PCI ARI configuration. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
51eeae91 |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add VF BAR map support for Enhanced Allocation Makes dm_pci_map_bar API available to map BAR for Virtual function PCI devices which support Enhanced Allocation. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
b8852dcf |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add support for Single-Root I/O Virtualization SR-IOV - Single Root I/O Virtualization PF - Physical Function VF - Virtual Function If SR-IOV capability is present, use it to initialize Virtual Function PCI device instances. pci_sriov_init function will read SR-IOV registers to create VF devices under the PF PCI device and also bind driver if available. This function needs to be invoked from Physical function device driver which expects VF device support, creating minimal impact on existing framework. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
e0024741 |
|
23-Jul-2020 |
Stefan Roese <sr@denx.de> |
pci: pci-uclass: Dynamically allocate the PCI regions Instead of using a fixed length pre-allocated array of regions, this patch moves to dynamically allocating the regions based on the number of available regions plus the necessary regions for DRAM banks. Since MAX_PCI_REGIONS is not needed any more, its removed completely with this patch. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Thierry Reding <treding@nvidia.com> Cc: Marek Vasut <marek.vasut+renesas@gmail.com>
|
#
143eb5b1 |
|
12-May-2020 |
Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
drivers: pci: add api to get dma regions Add api to get dma regions. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
284d062e |
|
09-Sep-2020 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
pci: add a few ARI related defines Add a few defines related to PCI ARI configuration. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
51eeae91 |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add VF BAR map support for Enhanced Allocation Makes dm_pci_map_bar API available to map BAR for Virtual function PCI devices which support Enhanced Allocation. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
b8852dcf |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add support for Single-Root I/O Virtualization SR-IOV - Single Root I/O Virtualization PF - Physical Function VF - Virtual Function If SR-IOV capability is present, use it to initialize Virtual Function PCI device instances. pci_sriov_init function will read SR-IOV registers to create VF devices under the PF PCI device and also bind driver if available. This function needs to be invoked from Physical function device driver which expects VF device support, creating minimal impact on existing framework. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
e0024741 |
|
23-Jul-2020 |
Stefan Roese <sr@denx.de> |
pci: pci-uclass: Dynamically allocate the PCI regions Instead of using a fixed length pre-allocated array of regions, this patch moves to dynamically allocating the regions based on the number of available regions plus the necessary regions for DRAM banks. Since MAX_PCI_REGIONS is not needed any more, its removed completely with this patch. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Thierry Reding <treding@nvidia.com> Cc: Marek Vasut <marek.vasut+renesas@gmail.com>
|
#
143eb5b1 |
|
12-May-2020 |
Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
drivers: pci: add api to get dma regions Add api to get dma regions. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
284d062e |
|
09-Sep-2020 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
pci: add a few ARI related defines Add a few defines related to PCI ARI configuration. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
51eeae91 |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add VF BAR map support for Enhanced Allocation Makes dm_pci_map_bar API available to map BAR for Virtual function PCI devices which support Enhanced Allocation. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
b8852dcf |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add support for Single-Root I/O Virtualization SR-IOV - Single Root I/O Virtualization PF - Physical Function VF - Virtual Function If SR-IOV capability is present, use it to initialize Virtual Function PCI device instances. pci_sriov_init function will read SR-IOV registers to create VF devices under the PF PCI device and also bind driver if available. This function needs to be invoked from Physical function device driver which expects VF device support, creating minimal impact on existing framework. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
e0024741 |
|
23-Jul-2020 |
Stefan Roese <sr@denx.de> |
pci: pci-uclass: Dynamically allocate the PCI regions Instead of using a fixed length pre-allocated array of regions, this patch moves to dynamically allocating the regions based on the number of available regions plus the necessary regions for DRAM banks. Since MAX_PCI_REGIONS is not needed any more, its removed completely with this patch. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Thierry Reding <treding@nvidia.com> Cc: Marek Vasut <marek.vasut+renesas@gmail.com>
|
#
143eb5b1 |
|
12-May-2020 |
Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
drivers: pci: add api to get dma regions Add api to get dma regions. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
284d062e |
|
09-Sep-2020 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
pci: add a few ARI related defines Add a few defines related to PCI ARI configuration. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
51eeae91 |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add VF BAR map support for Enhanced Allocation Makes dm_pci_map_bar API available to map BAR for Virtual function PCI devices which support Enhanced Allocation. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
b8852dcf |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add support for Single-Root I/O Virtualization SR-IOV - Single Root I/O Virtualization PF - Physical Function VF - Virtual Function If SR-IOV capability is present, use it to initialize Virtual Function PCI device instances. pci_sriov_init function will read SR-IOV registers to create VF devices under the PF PCI device and also bind driver if available. This function needs to be invoked from Physical function device driver which expects VF device support, creating minimal impact on existing framework. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
e0024741 |
|
23-Jul-2020 |
Stefan Roese <sr@denx.de> |
pci: pci-uclass: Dynamically allocate the PCI regions Instead of using a fixed length pre-allocated array of regions, this patch moves to dynamically allocating the regions based on the number of available regions plus the necessary regions for DRAM banks. Since MAX_PCI_REGIONS is not needed any more, its removed completely with this patch. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Thierry Reding <treding@nvidia.com> Cc: Marek Vasut <marek.vasut+renesas@gmail.com>
|
#
143eb5b1 |
|
12-May-2020 |
Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
drivers: pci: add api to get dma regions Add api to get dma regions. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
284d062e |
|
09-Sep-2020 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
pci: add a few ARI related defines Add a few defines related to PCI ARI configuration. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
51eeae91 |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add VF BAR map support for Enhanced Allocation Makes dm_pci_map_bar API available to map BAR for Virtual function PCI devices which support Enhanced Allocation. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
b8852dcf |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add support for Single-Root I/O Virtualization SR-IOV - Single Root I/O Virtualization PF - Physical Function VF - Virtual Function If SR-IOV capability is present, use it to initialize Virtual Function PCI device instances. pci_sriov_init function will read SR-IOV registers to create VF devices under the PF PCI device and also bind driver if available. This function needs to be invoked from Physical function device driver which expects VF device support, creating minimal impact on existing framework. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
e0024741 |
|
23-Jul-2020 |
Stefan Roese <sr@denx.de> |
pci: pci-uclass: Dynamically allocate the PCI regions Instead of using a fixed length pre-allocated array of regions, this patch moves to dynamically allocating the regions based on the number of available regions plus the necessary regions for DRAM banks. Since MAX_PCI_REGIONS is not needed any more, its removed completely with this patch. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Thierry Reding <treding@nvidia.com> Cc: Marek Vasut <marek.vasut+renesas@gmail.com>
|
#
143eb5b1 |
|
12-May-2020 |
Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
drivers: pci: add api to get dma regions Add api to get dma regions. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
284d062e |
|
09-Sep-2020 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
pci: add a few ARI related defines Add a few defines related to PCI ARI configuration. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
51eeae91 |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add VF BAR map support for Enhanced Allocation Makes dm_pci_map_bar API available to map BAR for Virtual function PCI devices which support Enhanced Allocation. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
b8852dcf |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add support for Single-Root I/O Virtualization SR-IOV - Single Root I/O Virtualization PF - Physical Function VF - Virtual Function If SR-IOV capability is present, use it to initialize Virtual Function PCI device instances. pci_sriov_init function will read SR-IOV registers to create VF devices under the PF PCI device and also bind driver if available. This function needs to be invoked from Physical function device driver which expects VF device support, creating minimal impact on existing framework. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
e0024741 |
|
23-Jul-2020 |
Stefan Roese <sr@denx.de> |
pci: pci-uclass: Dynamically allocate the PCI regions Instead of using a fixed length pre-allocated array of regions, this patch moves to dynamically allocating the regions based on the number of available regions plus the necessary regions for DRAM banks. Since MAX_PCI_REGIONS is not needed any more, its removed completely with this patch. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Thierry Reding <treding@nvidia.com> Cc: Marek Vasut <marek.vasut+renesas@gmail.com>
|
#
143eb5b1 |
|
12-May-2020 |
Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
drivers: pci: add api to get dma regions Add api to get dma regions. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
284d062e |
|
09-Sep-2020 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
pci: add a few ARI related defines Add a few defines related to PCI ARI configuration. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
51eeae91 |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add VF BAR map support for Enhanced Allocation Makes dm_pci_map_bar API available to map BAR for Virtual function PCI devices which support Enhanced Allocation. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
b8852dcf |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add support for Single-Root I/O Virtualization SR-IOV - Single Root I/O Virtualization PF - Physical Function VF - Virtual Function If SR-IOV capability is present, use it to initialize Virtual Function PCI device instances. pci_sriov_init function will read SR-IOV registers to create VF devices under the PF PCI device and also bind driver if available. This function needs to be invoked from Physical function device driver which expects VF device support, creating minimal impact on existing framework. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
e0024741 |
|
23-Jul-2020 |
Stefan Roese <sr@denx.de> |
pci: pci-uclass: Dynamically allocate the PCI regions Instead of using a fixed length pre-allocated array of regions, this patch moves to dynamically allocating the regions based on the number of available regions plus the necessary regions for DRAM banks. Since MAX_PCI_REGIONS is not needed any more, its removed completely with this patch. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Thierry Reding <treding@nvidia.com> Cc: Marek Vasut <marek.vasut+renesas@gmail.com>
|
#
143eb5b1 |
|
12-May-2020 |
Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
drivers: pci: add api to get dma regions Add api to get dma regions. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
284d062e |
|
09-Sep-2020 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
pci: add a few ARI related defines Add a few defines related to PCI ARI configuration. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
51eeae91 |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add VF BAR map support for Enhanced Allocation Makes dm_pci_map_bar API available to map BAR for Virtual function PCI devices which support Enhanced Allocation. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
b8852dcf |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add support for Single-Root I/O Virtualization SR-IOV - Single Root I/O Virtualization PF - Physical Function VF - Virtual Function If SR-IOV capability is present, use it to initialize Virtual Function PCI device instances. pci_sriov_init function will read SR-IOV registers to create VF devices under the PF PCI device and also bind driver if available. This function needs to be invoked from Physical function device driver which expects VF device support, creating minimal impact on existing framework. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
e0024741 |
|
23-Jul-2020 |
Stefan Roese <sr@denx.de> |
pci: pci-uclass: Dynamically allocate the PCI regions Instead of using a fixed length pre-allocated array of regions, this patch moves to dynamically allocating the regions based on the number of available regions plus the necessary regions for DRAM banks. Since MAX_PCI_REGIONS is not needed any more, its removed completely with this patch. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Thierry Reding <treding@nvidia.com> Cc: Marek Vasut <marek.vasut+renesas@gmail.com>
|
#
143eb5b1 |
|
12-May-2020 |
Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
drivers: pci: add api to get dma regions Add api to get dma regions. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
284d062e |
|
09-Sep-2020 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
pci: add a few ARI related defines Add a few defines related to PCI ARI configuration. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
51eeae91 |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add VF BAR map support for Enhanced Allocation Makes dm_pci_map_bar API available to map BAR for Virtual function PCI devices which support Enhanced Allocation. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
b8852dcf |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add support for Single-Root I/O Virtualization SR-IOV - Single Root I/O Virtualization PF - Physical Function VF - Virtual Function If SR-IOV capability is present, use it to initialize Virtual Function PCI device instances. pci_sriov_init function will read SR-IOV registers to create VF devices under the PF PCI device and also bind driver if available. This function needs to be invoked from Physical function device driver which expects VF device support, creating minimal impact on existing framework. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
e0024741 |
|
23-Jul-2020 |
Stefan Roese <sr@denx.de> |
pci: pci-uclass: Dynamically allocate the PCI regions Instead of using a fixed length pre-allocated array of regions, this patch moves to dynamically allocating the regions based on the number of available regions plus the necessary regions for DRAM banks. Since MAX_PCI_REGIONS is not needed any more, its removed completely with this patch. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Thierry Reding <treding@nvidia.com> Cc: Marek Vasut <marek.vasut+renesas@gmail.com>
|
#
143eb5b1 |
|
12-May-2020 |
Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
drivers: pci: add api to get dma regions Add api to get dma regions. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
284d062e |
|
09-Sep-2020 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
pci: add a few ARI related defines Add a few defines related to PCI ARI configuration. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
51eeae91 |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add VF BAR map support for Enhanced Allocation Makes dm_pci_map_bar API available to map BAR for Virtual function PCI devices which support Enhanced Allocation. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
b8852dcf |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add support for Single-Root I/O Virtualization SR-IOV - Single Root I/O Virtualization PF - Physical Function VF - Virtual Function If SR-IOV capability is present, use it to initialize Virtual Function PCI device instances. pci_sriov_init function will read SR-IOV registers to create VF devices under the PF PCI device and also bind driver if available. This function needs to be invoked from Physical function device driver which expects VF device support, creating minimal impact on existing framework. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
e0024741 |
|
23-Jul-2020 |
Stefan Roese <sr@denx.de> |
pci: pci-uclass: Dynamically allocate the PCI regions Instead of using a fixed length pre-allocated array of regions, this patch moves to dynamically allocating the regions based on the number of available regions plus the necessary regions for DRAM banks. Since MAX_PCI_REGIONS is not needed any more, its removed completely with this patch. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Thierry Reding <treding@nvidia.com> Cc: Marek Vasut <marek.vasut+renesas@gmail.com>
|
#
143eb5b1 |
|
12-May-2020 |
Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
drivers: pci: add api to get dma regions Add api to get dma regions. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
284d062e |
|
09-Sep-2020 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
pci: add a few ARI related defines Add a few defines related to PCI ARI configuration. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
51eeae91 |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add VF BAR map support for Enhanced Allocation Makes dm_pci_map_bar API available to map BAR for Virtual function PCI devices which support Enhanced Allocation. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
b8852dcf |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add support for Single-Root I/O Virtualization SR-IOV - Single Root I/O Virtualization PF - Physical Function VF - Virtual Function If SR-IOV capability is present, use it to initialize Virtual Function PCI device instances. pci_sriov_init function will read SR-IOV registers to create VF devices under the PF PCI device and also bind driver if available. This function needs to be invoked from Physical function device driver which expects VF device support, creating minimal impact on existing framework. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
e0024741 |
|
23-Jul-2020 |
Stefan Roese <sr@denx.de> |
pci: pci-uclass: Dynamically allocate the PCI regions Instead of using a fixed length pre-allocated array of regions, this patch moves to dynamically allocating the regions based on the number of available regions plus the necessary regions for DRAM banks. Since MAX_PCI_REGIONS is not needed any more, its removed completely with this patch. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Thierry Reding <treding@nvidia.com> Cc: Marek Vasut <marek.vasut+renesas@gmail.com>
|
#
143eb5b1 |
|
12-May-2020 |
Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
drivers: pci: add api to get dma regions Add api to get dma regions. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
284d062e |
|
09-Sep-2020 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
pci: add a few ARI related defines Add a few defines related to PCI ARI configuration. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
51eeae91 |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add VF BAR map support for Enhanced Allocation Makes dm_pci_map_bar API available to map BAR for Virtual function PCI devices which support Enhanced Allocation. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
b8852dcf |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add support for Single-Root I/O Virtualization SR-IOV - Single Root I/O Virtualization PF - Physical Function VF - Virtual Function If SR-IOV capability is present, use it to initialize Virtual Function PCI device instances. pci_sriov_init function will read SR-IOV registers to create VF devices under the PF PCI device and also bind driver if available. This function needs to be invoked from Physical function device driver which expects VF device support, creating minimal impact on existing framework. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
e0024741 |
|
23-Jul-2020 |
Stefan Roese <sr@denx.de> |
pci: pci-uclass: Dynamically allocate the PCI regions Instead of using a fixed length pre-allocated array of regions, this patch moves to dynamically allocating the regions based on the number of available regions plus the necessary regions for DRAM banks. Since MAX_PCI_REGIONS is not needed any more, its removed completely with this patch. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Thierry Reding <treding@nvidia.com> Cc: Marek Vasut <marek.vasut+renesas@gmail.com>
|
#
143eb5b1 |
|
12-May-2020 |
Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
drivers: pci: add api to get dma regions Add api to get dma regions. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
284d062e |
|
09-Sep-2020 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
pci: add a few ARI related defines Add a few defines related to PCI ARI configuration. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
51eeae91 |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add VF BAR map support for Enhanced Allocation Makes dm_pci_map_bar API available to map BAR for Virtual function PCI devices which support Enhanced Allocation. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
b8852dcf |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add support for Single-Root I/O Virtualization SR-IOV - Single Root I/O Virtualization PF - Physical Function VF - Virtual Function If SR-IOV capability is present, use it to initialize Virtual Function PCI device instances. pci_sriov_init function will read SR-IOV registers to create VF devices under the PF PCI device and also bind driver if available. This function needs to be invoked from Physical function device driver which expects VF device support, creating minimal impact on existing framework. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
e0024741 |
|
23-Jul-2020 |
Stefan Roese <sr@denx.de> |
pci: pci-uclass: Dynamically allocate the PCI regions Instead of using a fixed length pre-allocated array of regions, this patch moves to dynamically allocating the regions based on the number of available regions plus the necessary regions for DRAM banks. Since MAX_PCI_REGIONS is not needed any more, its removed completely with this patch. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Thierry Reding <treding@nvidia.com> Cc: Marek Vasut <marek.vasut+renesas@gmail.com>
|
#
143eb5b1 |
|
12-May-2020 |
Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
drivers: pci: add api to get dma regions Add api to get dma regions. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
284d062e |
|
09-Sep-2020 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
pci: add a few ARI related defines Add a few defines related to PCI ARI configuration. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
51eeae91 |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add VF BAR map support for Enhanced Allocation Makes dm_pci_map_bar API available to map BAR for Virtual function PCI devices which support Enhanced Allocation. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
b8852dcf |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add support for Single-Root I/O Virtualization SR-IOV - Single Root I/O Virtualization PF - Physical Function VF - Virtual Function If SR-IOV capability is present, use it to initialize Virtual Function PCI device instances. pci_sriov_init function will read SR-IOV registers to create VF devices under the PF PCI device and also bind driver if available. This function needs to be invoked from Physical function device driver which expects VF device support, creating minimal impact on existing framework. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
e0024741 |
|
23-Jul-2020 |
Stefan Roese <sr@denx.de> |
pci: pci-uclass: Dynamically allocate the PCI regions Instead of using a fixed length pre-allocated array of regions, this patch moves to dynamically allocating the regions based on the number of available regions plus the necessary regions for DRAM banks. Since MAX_PCI_REGIONS is not needed any more, its removed completely with this patch. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Thierry Reding <treding@nvidia.com> Cc: Marek Vasut <marek.vasut+renesas@gmail.com>
|
#
143eb5b1 |
|
12-May-2020 |
Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
drivers: pci: add api to get dma regions Add api to get dma regions. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
284d062e |
|
09-Sep-2020 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
pci: add a few ARI related defines Add a few defines related to PCI ARI configuration. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
51eeae91 |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add VF BAR map support for Enhanced Allocation Makes dm_pci_map_bar API available to map BAR for Virtual function PCI devices which support Enhanced Allocation. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
b8852dcf |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add support for Single-Root I/O Virtualization SR-IOV - Single Root I/O Virtualization PF - Physical Function VF - Virtual Function If SR-IOV capability is present, use it to initialize Virtual Function PCI device instances. pci_sriov_init function will read SR-IOV registers to create VF devices under the PF PCI device and also bind driver if available. This function needs to be invoked from Physical function device driver which expects VF device support, creating minimal impact on existing framework. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
e0024741 |
|
23-Jul-2020 |
Stefan Roese <sr@denx.de> |
pci: pci-uclass: Dynamically allocate the PCI regions Instead of using a fixed length pre-allocated array of regions, this patch moves to dynamically allocating the regions based on the number of available regions plus the necessary regions for DRAM banks. Since MAX_PCI_REGIONS is not needed any more, its removed completely with this patch. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Thierry Reding <treding@nvidia.com> Cc: Marek Vasut <marek.vasut+renesas@gmail.com>
|
#
143eb5b1 |
|
12-May-2020 |
Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
drivers: pci: add api to get dma regions Add api to get dma regions. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
284d062e |
|
09-Sep-2020 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
pci: add a few ARI related defines Add a few defines related to PCI ARI configuration. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
51eeae91 |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add VF BAR map support for Enhanced Allocation Makes dm_pci_map_bar API available to map BAR for Virtual function PCI devices which support Enhanced Allocation. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
b8852dcf |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add support for Single-Root I/O Virtualization SR-IOV - Single Root I/O Virtualization PF - Physical Function VF - Virtual Function If SR-IOV capability is present, use it to initialize Virtual Function PCI device instances. pci_sriov_init function will read SR-IOV registers to create VF devices under the PF PCI device and also bind driver if available. This function needs to be invoked from Physical function device driver which expects VF device support, creating minimal impact on existing framework. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
e0024741 |
|
23-Jul-2020 |
Stefan Roese <sr@denx.de> |
pci: pci-uclass: Dynamically allocate the PCI regions Instead of using a fixed length pre-allocated array of regions, this patch moves to dynamically allocating the regions based on the number of available regions plus the necessary regions for DRAM banks. Since MAX_PCI_REGIONS is not needed any more, its removed completely with this patch. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Thierry Reding <treding@nvidia.com> Cc: Marek Vasut <marek.vasut+renesas@gmail.com>
|
#
143eb5b1 |
|
12-May-2020 |
Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
drivers: pci: add api to get dma regions Add api to get dma regions. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
284d062e |
|
09-Sep-2020 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
pci: add a few ARI related defines Add a few defines related to PCI ARI configuration. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
51eeae91 |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add VF BAR map support for Enhanced Allocation Makes dm_pci_map_bar API available to map BAR for Virtual function PCI devices which support Enhanced Allocation. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
b8852dcf |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add support for Single-Root I/O Virtualization SR-IOV - Single Root I/O Virtualization PF - Physical Function VF - Virtual Function If SR-IOV capability is present, use it to initialize Virtual Function PCI device instances. pci_sriov_init function will read SR-IOV registers to create VF devices under the PF PCI device and also bind driver if available. This function needs to be invoked from Physical function device driver which expects VF device support, creating minimal impact on existing framework. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
e0024741 |
|
23-Jul-2020 |
Stefan Roese <sr@denx.de> |
pci: pci-uclass: Dynamically allocate the PCI regions Instead of using a fixed length pre-allocated array of regions, this patch moves to dynamically allocating the regions based on the number of available regions plus the necessary regions for DRAM banks. Since MAX_PCI_REGIONS is not needed any more, its removed completely with this patch. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Thierry Reding <treding@nvidia.com> Cc: Marek Vasut <marek.vasut+renesas@gmail.com>
|
#
143eb5b1 |
|
12-May-2020 |
Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
drivers: pci: add api to get dma regions Add api to get dma regions. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
284d062e |
|
09-Sep-2020 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
pci: add a few ARI related defines Add a few defines related to PCI ARI configuration. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
51eeae91 |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add VF BAR map support for Enhanced Allocation Makes dm_pci_map_bar API available to map BAR for Virtual function PCI devices which support Enhanced Allocation. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
b8852dcf |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add support for Single-Root I/O Virtualization SR-IOV - Single Root I/O Virtualization PF - Physical Function VF - Virtual Function If SR-IOV capability is present, use it to initialize Virtual Function PCI device instances. pci_sriov_init function will read SR-IOV registers to create VF devices under the PF PCI device and also bind driver if available. This function needs to be invoked from Physical function device driver which expects VF device support, creating minimal impact on existing framework. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
e0024741 |
|
23-Jul-2020 |
Stefan Roese <sr@denx.de> |
pci: pci-uclass: Dynamically allocate the PCI regions Instead of using a fixed length pre-allocated array of regions, this patch moves to dynamically allocating the regions based on the number of available regions plus the necessary regions for DRAM banks. Since MAX_PCI_REGIONS is not needed any more, its removed completely with this patch. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Thierry Reding <treding@nvidia.com> Cc: Marek Vasut <marek.vasut+renesas@gmail.com>
|
#
143eb5b1 |
|
12-May-2020 |
Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
drivers: pci: add api to get dma regions Add api to get dma regions. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
284d062e |
|
09-Sep-2020 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
pci: add a few ARI related defines Add a few defines related to PCI ARI configuration. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
51eeae91 |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add VF BAR map support for Enhanced Allocation Makes dm_pci_map_bar API available to map BAR for Virtual function PCI devices which support Enhanced Allocation. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
b8852dcf |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add support for Single-Root I/O Virtualization SR-IOV - Single Root I/O Virtualization PF - Physical Function VF - Virtual Function If SR-IOV capability is present, use it to initialize Virtual Function PCI device instances. pci_sriov_init function will read SR-IOV registers to create VF devices under the PF PCI device and also bind driver if available. This function needs to be invoked from Physical function device driver which expects VF device support, creating minimal impact on existing framework. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
e0024741 |
|
23-Jul-2020 |
Stefan Roese <sr@denx.de> |
pci: pci-uclass: Dynamically allocate the PCI regions Instead of using a fixed length pre-allocated array of regions, this patch moves to dynamically allocating the regions based on the number of available regions plus the necessary regions for DRAM banks. Since MAX_PCI_REGIONS is not needed any more, its removed completely with this patch. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Thierry Reding <treding@nvidia.com> Cc: Marek Vasut <marek.vasut+renesas@gmail.com>
|
#
143eb5b1 |
|
12-May-2020 |
Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
drivers: pci: add api to get dma regions Add api to get dma regions. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
284d062e |
|
09-Sep-2020 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
pci: add a few ARI related defines Add a few defines related to PCI ARI configuration. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
51eeae91 |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add VF BAR map support for Enhanced Allocation Makes dm_pci_map_bar API available to map BAR for Virtual function PCI devices which support Enhanced Allocation. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
b8852dcf |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add support for Single-Root I/O Virtualization SR-IOV - Single Root I/O Virtualization PF - Physical Function VF - Virtual Function If SR-IOV capability is present, use it to initialize Virtual Function PCI device instances. pci_sriov_init function will read SR-IOV registers to create VF devices under the PF PCI device and also bind driver if available. This function needs to be invoked from Physical function device driver which expects VF device support, creating minimal impact on existing framework. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
e0024741 |
|
23-Jul-2020 |
Stefan Roese <sr@denx.de> |
pci: pci-uclass: Dynamically allocate the PCI regions Instead of using a fixed length pre-allocated array of regions, this patch moves to dynamically allocating the regions based on the number of available regions plus the necessary regions for DRAM banks. Since MAX_PCI_REGIONS is not needed any more, its removed completely with this patch. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Thierry Reding <treding@nvidia.com> Cc: Marek Vasut <marek.vasut+renesas@gmail.com>
|
#
143eb5b1 |
|
12-May-2020 |
Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
drivers: pci: add api to get dma regions Add api to get dma regions. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
284d062e |
|
09-Sep-2020 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
pci: add a few ARI related defines Add a few defines related to PCI ARI configuration. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
51eeae91 |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add VF BAR map support for Enhanced Allocation Makes dm_pci_map_bar API available to map BAR for Virtual function PCI devices which support Enhanced Allocation. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
b8852dcf |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add support for Single-Root I/O Virtualization SR-IOV - Single Root I/O Virtualization PF - Physical Function VF - Virtual Function If SR-IOV capability is present, use it to initialize Virtual Function PCI device instances. pci_sriov_init function will read SR-IOV registers to create VF devices under the PF PCI device and also bind driver if available. This function needs to be invoked from Physical function device driver which expects VF device support, creating minimal impact on existing framework. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
e0024741 |
|
23-Jul-2020 |
Stefan Roese <sr@denx.de> |
pci: pci-uclass: Dynamically allocate the PCI regions Instead of using a fixed length pre-allocated array of regions, this patch moves to dynamically allocating the regions based on the number of available regions plus the necessary regions for DRAM banks. Since MAX_PCI_REGIONS is not needed any more, its removed completely with this patch. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Thierry Reding <treding@nvidia.com> Cc: Marek Vasut <marek.vasut+renesas@gmail.com>
|
#
143eb5b1 |
|
12-May-2020 |
Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
drivers: pci: add api to get dma regions Add api to get dma regions. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
284d062e |
|
09-Sep-2020 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
pci: add a few ARI related defines Add a few defines related to PCI ARI configuration. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
51eeae91 |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add VF BAR map support for Enhanced Allocation Makes dm_pci_map_bar API available to map BAR for Virtual function PCI devices which support Enhanced Allocation. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
b8852dcf |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add support for Single-Root I/O Virtualization SR-IOV - Single Root I/O Virtualization PF - Physical Function VF - Virtual Function If SR-IOV capability is present, use it to initialize Virtual Function PCI device instances. pci_sriov_init function will read SR-IOV registers to create VF devices under the PF PCI device and also bind driver if available. This function needs to be invoked from Physical function device driver which expects VF device support, creating minimal impact on existing framework. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
e0024741 |
|
23-Jul-2020 |
Stefan Roese <sr@denx.de> |
pci: pci-uclass: Dynamically allocate the PCI regions Instead of using a fixed length pre-allocated array of regions, this patch moves to dynamically allocating the regions based on the number of available regions plus the necessary regions for DRAM banks. Since MAX_PCI_REGIONS is not needed any more, its removed completely with this patch. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Thierry Reding <treding@nvidia.com> Cc: Marek Vasut <marek.vasut+renesas@gmail.com>
|
#
143eb5b1 |
|
12-May-2020 |
Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
drivers: pci: add api to get dma regions Add api to get dma regions. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
284d062e |
|
09-Sep-2020 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
pci: add a few ARI related defines Add a few defines related to PCI ARI configuration. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
51eeae91 |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add VF BAR map support for Enhanced Allocation Makes dm_pci_map_bar API available to map BAR for Virtual function PCI devices which support Enhanced Allocation. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
b8852dcf |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add support for Single-Root I/O Virtualization SR-IOV - Single Root I/O Virtualization PF - Physical Function VF - Virtual Function If SR-IOV capability is present, use it to initialize Virtual Function PCI device instances. pci_sriov_init function will read SR-IOV registers to create VF devices under the PF PCI device and also bind driver if available. This function needs to be invoked from Physical function device driver which expects VF device support, creating minimal impact on existing framework. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
e0024741 |
|
23-Jul-2020 |
Stefan Roese <sr@denx.de> |
pci: pci-uclass: Dynamically allocate the PCI regions Instead of using a fixed length pre-allocated array of regions, this patch moves to dynamically allocating the regions based on the number of available regions plus the necessary regions for DRAM banks. Since MAX_PCI_REGIONS is not needed any more, its removed completely with this patch. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Thierry Reding <treding@nvidia.com> Cc: Marek Vasut <marek.vasut+renesas@gmail.com>
|
#
143eb5b1 |
|
12-May-2020 |
Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
drivers: pci: add api to get dma regions Add api to get dma regions. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
284d062e |
|
09-Sep-2020 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
pci: add a few ARI related defines Add a few defines related to PCI ARI configuration. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
51eeae91 |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add VF BAR map support for Enhanced Allocation Makes dm_pci_map_bar API available to map BAR for Virtual function PCI devices which support Enhanced Allocation. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
b8852dcf |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add support for Single-Root I/O Virtualization SR-IOV - Single Root I/O Virtualization PF - Physical Function VF - Virtual Function If SR-IOV capability is present, use it to initialize Virtual Function PCI device instances. pci_sriov_init function will read SR-IOV registers to create VF devices under the PF PCI device and also bind driver if available. This function needs to be invoked from Physical function device driver which expects VF device support, creating minimal impact on existing framework. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
e0024741 |
|
23-Jul-2020 |
Stefan Roese <sr@denx.de> |
pci: pci-uclass: Dynamically allocate the PCI regions Instead of using a fixed length pre-allocated array of regions, this patch moves to dynamically allocating the regions based on the number of available regions plus the necessary regions for DRAM banks. Since MAX_PCI_REGIONS is not needed any more, its removed completely with this patch. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Thierry Reding <treding@nvidia.com> Cc: Marek Vasut <marek.vasut+renesas@gmail.com>
|
#
143eb5b1 |
|
12-May-2020 |
Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
drivers: pci: add api to get dma regions Add api to get dma regions. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
284d062e |
|
09-Sep-2020 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
pci: add a few ARI related defines Add a few defines related to PCI ARI configuration. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
51eeae91 |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add VF BAR map support for Enhanced Allocation Makes dm_pci_map_bar API available to map BAR for Virtual function PCI devices which support Enhanced Allocation. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
b8852dcf |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add support for Single-Root I/O Virtualization SR-IOV - Single Root I/O Virtualization PF - Physical Function VF - Virtual Function If SR-IOV capability is present, use it to initialize Virtual Function PCI device instances. pci_sriov_init function will read SR-IOV registers to create VF devices under the PF PCI device and also bind driver if available. This function needs to be invoked from Physical function device driver which expects VF device support, creating minimal impact on existing framework. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
e0024741 |
|
23-Jul-2020 |
Stefan Roese <sr@denx.de> |
pci: pci-uclass: Dynamically allocate the PCI regions Instead of using a fixed length pre-allocated array of regions, this patch moves to dynamically allocating the regions based on the number of available regions plus the necessary regions for DRAM banks. Since MAX_PCI_REGIONS is not needed any more, its removed completely with this patch. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Thierry Reding <treding@nvidia.com> Cc: Marek Vasut <marek.vasut+renesas@gmail.com>
|
#
143eb5b1 |
|
12-May-2020 |
Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
drivers: pci: add api to get dma regions Add api to get dma regions. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
284d062e |
|
09-Sep-2020 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
pci: add a few ARI related defines Add a few defines related to PCI ARI configuration. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
51eeae91 |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add VF BAR map support for Enhanced Allocation Makes dm_pci_map_bar API available to map BAR for Virtual function PCI devices which support Enhanced Allocation. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
b8852dcf |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add support for Single-Root I/O Virtualization SR-IOV - Single Root I/O Virtualization PF - Physical Function VF - Virtual Function If SR-IOV capability is present, use it to initialize Virtual Function PCI device instances. pci_sriov_init function will read SR-IOV registers to create VF devices under the PF PCI device and also bind driver if available. This function needs to be invoked from Physical function device driver which expects VF device support, creating minimal impact on existing framework. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
e0024741 |
|
23-Jul-2020 |
Stefan Roese <sr@denx.de> |
pci: pci-uclass: Dynamically allocate the PCI regions Instead of using a fixed length pre-allocated array of regions, this patch moves to dynamically allocating the regions based on the number of available regions plus the necessary regions for DRAM banks. Since MAX_PCI_REGIONS is not needed any more, its removed completely with this patch. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Thierry Reding <treding@nvidia.com> Cc: Marek Vasut <marek.vasut+renesas@gmail.com>
|
#
143eb5b1 |
|
12-May-2020 |
Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
drivers: pci: add api to get dma regions Add api to get dma regions. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
284d062e |
|
09-Sep-2020 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
pci: add a few ARI related defines Add a few defines related to PCI ARI configuration. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
51eeae91 |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add VF BAR map support for Enhanced Allocation Makes dm_pci_map_bar API available to map BAR for Virtual function PCI devices which support Enhanced Allocation. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
b8852dcf |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add support for Single-Root I/O Virtualization SR-IOV - Single Root I/O Virtualization PF - Physical Function VF - Virtual Function If SR-IOV capability is present, use it to initialize Virtual Function PCI device instances. pci_sriov_init function will read SR-IOV registers to create VF devices under the PF PCI device and also bind driver if available. This function needs to be invoked from Physical function device driver which expects VF device support, creating minimal impact on existing framework. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
e0024741 |
|
23-Jul-2020 |
Stefan Roese <sr@denx.de> |
pci: pci-uclass: Dynamically allocate the PCI regions Instead of using a fixed length pre-allocated array of regions, this patch moves to dynamically allocating the regions based on the number of available regions plus the necessary regions for DRAM banks. Since MAX_PCI_REGIONS is not needed any more, its removed completely with this patch. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Thierry Reding <treding@nvidia.com> Cc: Marek Vasut <marek.vasut+renesas@gmail.com>
|
#
143eb5b1 |
|
12-May-2020 |
Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
drivers: pci: add api to get dma regions Add api to get dma regions. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
284d062e |
|
09-Sep-2020 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
pci: add a few ARI related defines Add a few defines related to PCI ARI configuration. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
51eeae91 |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add VF BAR map support for Enhanced Allocation Makes dm_pci_map_bar API available to map BAR for Virtual function PCI devices which support Enhanced Allocation. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
b8852dcf |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add support for Single-Root I/O Virtualization SR-IOV - Single Root I/O Virtualization PF - Physical Function VF - Virtual Function If SR-IOV capability is present, use it to initialize Virtual Function PCI device instances. pci_sriov_init function will read SR-IOV registers to create VF devices under the PF PCI device and also bind driver if available. This function needs to be invoked from Physical function device driver which expects VF device support, creating minimal impact on existing framework. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
e0024741 |
|
23-Jul-2020 |
Stefan Roese <sr@denx.de> |
pci: pci-uclass: Dynamically allocate the PCI regions Instead of using a fixed length pre-allocated array of regions, this patch moves to dynamically allocating the regions based on the number of available regions plus the necessary regions for DRAM banks. Since MAX_PCI_REGIONS is not needed any more, its removed completely with this patch. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Thierry Reding <treding@nvidia.com> Cc: Marek Vasut <marek.vasut+renesas@gmail.com>
|
#
143eb5b1 |
|
12-May-2020 |
Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
drivers: pci: add api to get dma regions Add api to get dma regions. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
284d062e |
|
09-Sep-2020 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
pci: add a few ARI related defines Add a few defines related to PCI ARI configuration. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
51eeae91 |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add VF BAR map support for Enhanced Allocation Makes dm_pci_map_bar API available to map BAR for Virtual function PCI devices which support Enhanced Allocation. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
b8852dcf |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add support for Single-Root I/O Virtualization SR-IOV - Single Root I/O Virtualization PF - Physical Function VF - Virtual Function If SR-IOV capability is present, use it to initialize Virtual Function PCI device instances. pci_sriov_init function will read SR-IOV registers to create VF devices under the PF PCI device and also bind driver if available. This function needs to be invoked from Physical function device driver which expects VF device support, creating minimal impact on existing framework. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
e0024741 |
|
23-Jul-2020 |
Stefan Roese <sr@denx.de> |
pci: pci-uclass: Dynamically allocate the PCI regions Instead of using a fixed length pre-allocated array of regions, this patch moves to dynamically allocating the regions based on the number of available regions plus the necessary regions for DRAM banks. Since MAX_PCI_REGIONS is not needed any more, its removed completely with this patch. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Thierry Reding <treding@nvidia.com> Cc: Marek Vasut <marek.vasut+renesas@gmail.com>
|
#
143eb5b1 |
|
12-May-2020 |
Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
drivers: pci: add api to get dma regions Add api to get dma regions. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
284d062e |
|
09-Sep-2020 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
pci: add a few ARI related defines Add a few defines related to PCI ARI configuration. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
51eeae91 |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add VF BAR map support for Enhanced Allocation Makes dm_pci_map_bar API available to map BAR for Virtual function PCI devices which support Enhanced Allocation. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
b8852dcf |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add support for Single-Root I/O Virtualization SR-IOV - Single Root I/O Virtualization PF - Physical Function VF - Virtual Function If SR-IOV capability is present, use it to initialize Virtual Function PCI device instances. pci_sriov_init function will read SR-IOV registers to create VF devices under the PF PCI device and also bind driver if available. This function needs to be invoked from Physical function device driver which expects VF device support, creating minimal impact on existing framework. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
e0024741 |
|
23-Jul-2020 |
Stefan Roese <sr@denx.de> |
pci: pci-uclass: Dynamically allocate the PCI regions Instead of using a fixed length pre-allocated array of regions, this patch moves to dynamically allocating the regions based on the number of available regions plus the necessary regions for DRAM banks. Since MAX_PCI_REGIONS is not needed any more, its removed completely with this patch. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Thierry Reding <treding@nvidia.com> Cc: Marek Vasut <marek.vasut+renesas@gmail.com>
|
#
143eb5b1 |
|
12-May-2020 |
Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
drivers: pci: add api to get dma regions Add api to get dma regions. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
284d062e |
|
09-Sep-2020 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
pci: add a few ARI related defines Add a few defines related to PCI ARI configuration. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
51eeae91 |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add VF BAR map support for Enhanced Allocation Makes dm_pci_map_bar API available to map BAR for Virtual function PCI devices which support Enhanced Allocation. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
b8852dcf |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add support for Single-Root I/O Virtualization SR-IOV - Single Root I/O Virtualization PF - Physical Function VF - Virtual Function If SR-IOV capability is present, use it to initialize Virtual Function PCI device instances. pci_sriov_init function will read SR-IOV registers to create VF devices under the PF PCI device and also bind driver if available. This function needs to be invoked from Physical function device driver which expects VF device support, creating minimal impact on existing framework. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
e0024741 |
|
23-Jul-2020 |
Stefan Roese <sr@denx.de> |
pci: pci-uclass: Dynamically allocate the PCI regions Instead of using a fixed length pre-allocated array of regions, this patch moves to dynamically allocating the regions based on the number of available regions plus the necessary regions for DRAM banks. Since MAX_PCI_REGIONS is not needed any more, its removed completely with this patch. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Thierry Reding <treding@nvidia.com> Cc: Marek Vasut <marek.vasut+renesas@gmail.com>
|
#
143eb5b1 |
|
12-May-2020 |
Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
drivers: pci: add api to get dma regions Add api to get dma regions. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
284d062e |
|
09-Sep-2020 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
pci: add a few ARI related defines Add a few defines related to PCI ARI configuration. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
51eeae91 |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add VF BAR map support for Enhanced Allocation Makes dm_pci_map_bar API available to map BAR for Virtual function PCI devices which support Enhanced Allocation. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
b8852dcf |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add support for Single-Root I/O Virtualization SR-IOV - Single Root I/O Virtualization PF - Physical Function VF - Virtual Function If SR-IOV capability is present, use it to initialize Virtual Function PCI device instances. pci_sriov_init function will read SR-IOV registers to create VF devices under the PF PCI device and also bind driver if available. This function needs to be invoked from Physical function device driver which expects VF device support, creating minimal impact on existing framework. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
e0024741 |
|
23-Jul-2020 |
Stefan Roese <sr@denx.de> |
pci: pci-uclass: Dynamically allocate the PCI regions Instead of using a fixed length pre-allocated array of regions, this patch moves to dynamically allocating the regions based on the number of available regions plus the necessary regions for DRAM banks. Since MAX_PCI_REGIONS is not needed any more, its removed completely with this patch. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Thierry Reding <treding@nvidia.com> Cc: Marek Vasut <marek.vasut+renesas@gmail.com>
|
#
143eb5b1 |
|
12-May-2020 |
Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
drivers: pci: add api to get dma regions Add api to get dma regions. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
284d062e |
|
09-Sep-2020 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
pci: add a few ARI related defines Add a few defines related to PCI ARI configuration. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
51eeae91 |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add VF BAR map support for Enhanced Allocation Makes dm_pci_map_bar API available to map BAR for Virtual function PCI devices which support Enhanced Allocation. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
b8852dcf |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add support for Single-Root I/O Virtualization SR-IOV - Single Root I/O Virtualization PF - Physical Function VF - Virtual Function If SR-IOV capability is present, use it to initialize Virtual Function PCI device instances. pci_sriov_init function will read SR-IOV registers to create VF devices under the PF PCI device and also bind driver if available. This function needs to be invoked from Physical function device driver which expects VF device support, creating minimal impact on existing framework. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
e0024741 |
|
23-Jul-2020 |
Stefan Roese <sr@denx.de> |
pci: pci-uclass: Dynamically allocate the PCI regions Instead of using a fixed length pre-allocated array of regions, this patch moves to dynamically allocating the regions based on the number of available regions plus the necessary regions for DRAM banks. Since MAX_PCI_REGIONS is not needed any more, its removed completely with this patch. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Thierry Reding <treding@nvidia.com> Cc: Marek Vasut <marek.vasut+renesas@gmail.com>
|
#
143eb5b1 |
|
12-May-2020 |
Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
drivers: pci: add api to get dma regions Add api to get dma regions. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
284d062e |
|
09-Sep-2020 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
pci: add a few ARI related defines Add a few defines related to PCI ARI configuration. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
51eeae91 |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add VF BAR map support for Enhanced Allocation Makes dm_pci_map_bar API available to map BAR for Virtual function PCI devices which support Enhanced Allocation. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
b8852dcf |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add support for Single-Root I/O Virtualization SR-IOV - Single Root I/O Virtualization PF - Physical Function VF - Virtual Function If SR-IOV capability is present, use it to initialize Virtual Function PCI device instances. pci_sriov_init function will read SR-IOV registers to create VF devices under the PF PCI device and also bind driver if available. This function needs to be invoked from Physical function device driver which expects VF device support, creating minimal impact on existing framework. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
e0024741 |
|
23-Jul-2020 |
Stefan Roese <sr@denx.de> |
pci: pci-uclass: Dynamically allocate the PCI regions Instead of using a fixed length pre-allocated array of regions, this patch moves to dynamically allocating the regions based on the number of available regions plus the necessary regions for DRAM banks. Since MAX_PCI_REGIONS is not needed any more, its removed completely with this patch. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Thierry Reding <treding@nvidia.com> Cc: Marek Vasut <marek.vasut+renesas@gmail.com>
|
#
143eb5b1 |
|
12-May-2020 |
Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
drivers: pci: add api to get dma regions Add api to get dma regions. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
284d062e |
|
09-Sep-2020 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
pci: add a few ARI related defines Add a few defines related to PCI ARI configuration. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
51eeae91 |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add VF BAR map support for Enhanced Allocation Makes dm_pci_map_bar API available to map BAR for Virtual function PCI devices which support Enhanced Allocation. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
b8852dcf |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add support for Single-Root I/O Virtualization SR-IOV - Single Root I/O Virtualization PF - Physical Function VF - Virtual Function If SR-IOV capability is present, use it to initialize Virtual Function PCI device instances. pci_sriov_init function will read SR-IOV registers to create VF devices under the PF PCI device and also bind driver if available. This function needs to be invoked from Physical function device driver which expects VF device support, creating minimal impact on existing framework. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
e0024741 |
|
23-Jul-2020 |
Stefan Roese <sr@denx.de> |
pci: pci-uclass: Dynamically allocate the PCI regions Instead of using a fixed length pre-allocated array of regions, this patch moves to dynamically allocating the regions based on the number of available regions plus the necessary regions for DRAM banks. Since MAX_PCI_REGIONS is not needed any more, its removed completely with this patch. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Thierry Reding <treding@nvidia.com> Cc: Marek Vasut <marek.vasut+renesas@gmail.com>
|
#
143eb5b1 |
|
12-May-2020 |
Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
drivers: pci: add api to get dma regions Add api to get dma regions. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
284d062e |
|
09-Sep-2020 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
pci: add a few ARI related defines Add a few defines related to PCI ARI configuration. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
51eeae91 |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add VF BAR map support for Enhanced Allocation Makes dm_pci_map_bar API available to map BAR for Virtual function PCI devices which support Enhanced Allocation. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
b8852dcf |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add support for Single-Root I/O Virtualization SR-IOV - Single Root I/O Virtualization PF - Physical Function VF - Virtual Function If SR-IOV capability is present, use it to initialize Virtual Function PCI device instances. pci_sriov_init function will read SR-IOV registers to create VF devices under the PF PCI device and also bind driver if available. This function needs to be invoked from Physical function device driver which expects VF device support, creating minimal impact on existing framework. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
e0024741 |
|
23-Jul-2020 |
Stefan Roese <sr@denx.de> |
pci: pci-uclass: Dynamically allocate the PCI regions Instead of using a fixed length pre-allocated array of regions, this patch moves to dynamically allocating the regions based on the number of available regions plus the necessary regions for DRAM banks. Since MAX_PCI_REGIONS is not needed any more, its removed completely with this patch. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Thierry Reding <treding@nvidia.com> Cc: Marek Vasut <marek.vasut+renesas@gmail.com>
|
#
143eb5b1 |
|
12-May-2020 |
Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
drivers: pci: add api to get dma regions Add api to get dma regions. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
284d062e |
|
09-Sep-2020 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
pci: add a few ARI related defines Add a few defines related to PCI ARI configuration. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
51eeae91 |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add VF BAR map support for Enhanced Allocation Makes dm_pci_map_bar API available to map BAR for Virtual function PCI devices which support Enhanced Allocation. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
b8852dcf |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add support for Single-Root I/O Virtualization SR-IOV - Single Root I/O Virtualization PF - Physical Function VF - Virtual Function If SR-IOV capability is present, use it to initialize Virtual Function PCI device instances. pci_sriov_init function will read SR-IOV registers to create VF devices under the PF PCI device and also bind driver if available. This function needs to be invoked from Physical function device driver which expects VF device support, creating minimal impact on existing framework. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
e0024741 |
|
23-Jul-2020 |
Stefan Roese <sr@denx.de> |
pci: pci-uclass: Dynamically allocate the PCI regions Instead of using a fixed length pre-allocated array of regions, this patch moves to dynamically allocating the regions based on the number of available regions plus the necessary regions for DRAM banks. Since MAX_PCI_REGIONS is not needed any more, its removed completely with this patch. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Thierry Reding <treding@nvidia.com> Cc: Marek Vasut <marek.vasut+renesas@gmail.com>
|
#
143eb5b1 |
|
12-May-2020 |
Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
drivers: pci: add api to get dma regions Add api to get dma regions. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
284d062e |
|
09-Sep-2020 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
pci: add a few ARI related defines Add a few defines related to PCI ARI configuration. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
51eeae91 |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add VF BAR map support for Enhanced Allocation Makes dm_pci_map_bar API available to map BAR for Virtual function PCI devices which support Enhanced Allocation. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
b8852dcf |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add support for Single-Root I/O Virtualization SR-IOV - Single Root I/O Virtualization PF - Physical Function VF - Virtual Function If SR-IOV capability is present, use it to initialize Virtual Function PCI device instances. pci_sriov_init function will read SR-IOV registers to create VF devices under the PF PCI device and also bind driver if available. This function needs to be invoked from Physical function device driver which expects VF device support, creating minimal impact on existing framework. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
e0024741 |
|
23-Jul-2020 |
Stefan Roese <sr@denx.de> |
pci: pci-uclass: Dynamically allocate the PCI regions Instead of using a fixed length pre-allocated array of regions, this patch moves to dynamically allocating the regions based on the number of available regions plus the necessary regions for DRAM banks. Since MAX_PCI_REGIONS is not needed any more, its removed completely with this patch. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Thierry Reding <treding@nvidia.com> Cc: Marek Vasut <marek.vasut+renesas@gmail.com>
|
#
143eb5b1 |
|
12-May-2020 |
Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
drivers: pci: add api to get dma regions Add api to get dma regions. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
284d062e |
|
09-Sep-2020 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
pci: add a few ARI related defines Add a few defines related to PCI ARI configuration. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
51eeae91 |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add VF BAR map support for Enhanced Allocation Makes dm_pci_map_bar API available to map BAR for Virtual function PCI devices which support Enhanced Allocation. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
b8852dcf |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add support for Single-Root I/O Virtualization SR-IOV - Single Root I/O Virtualization PF - Physical Function VF - Virtual Function If SR-IOV capability is present, use it to initialize Virtual Function PCI device instances. pci_sriov_init function will read SR-IOV registers to create VF devices under the PF PCI device and also bind driver if available. This function needs to be invoked from Physical function device driver which expects VF device support, creating minimal impact on existing framework. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
e0024741 |
|
23-Jul-2020 |
Stefan Roese <sr@denx.de> |
pci: pci-uclass: Dynamically allocate the PCI regions Instead of using a fixed length pre-allocated array of regions, this patch moves to dynamically allocating the regions based on the number of available regions plus the necessary regions for DRAM banks. Since MAX_PCI_REGIONS is not needed any more, its removed completely with this patch. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Thierry Reding <treding@nvidia.com> Cc: Marek Vasut <marek.vasut+renesas@gmail.com>
|
#
143eb5b1 |
|
12-May-2020 |
Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
drivers: pci: add api to get dma regions Add api to get dma regions. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
284d062e |
|
09-Sep-2020 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
pci: add a few ARI related defines Add a few defines related to PCI ARI configuration. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
51eeae91 |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add VF BAR map support for Enhanced Allocation Makes dm_pci_map_bar API available to map BAR for Virtual function PCI devices which support Enhanced Allocation. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
b8852dcf |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add support for Single-Root I/O Virtualization SR-IOV - Single Root I/O Virtualization PF - Physical Function VF - Virtual Function If SR-IOV capability is present, use it to initialize Virtual Function PCI device instances. pci_sriov_init function will read SR-IOV registers to create VF devices under the PF PCI device and also bind driver if available. This function needs to be invoked from Physical function device driver which expects VF device support, creating minimal impact on existing framework. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
e0024741 |
|
23-Jul-2020 |
Stefan Roese <sr@denx.de> |
pci: pci-uclass: Dynamically allocate the PCI regions Instead of using a fixed length pre-allocated array of regions, this patch moves to dynamically allocating the regions based on the number of available regions plus the necessary regions for DRAM banks. Since MAX_PCI_REGIONS is not needed any more, its removed completely with this patch. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Thierry Reding <treding@nvidia.com> Cc: Marek Vasut <marek.vasut+renesas@gmail.com>
|
#
143eb5b1 |
|
12-May-2020 |
Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
drivers: pci: add api to get dma regions Add api to get dma regions. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
284d062e |
|
09-Sep-2020 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
pci: add a few ARI related defines Add a few defines related to PCI ARI configuration. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
51eeae91 |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add VF BAR map support for Enhanced Allocation Makes dm_pci_map_bar API available to map BAR for Virtual function PCI devices which support Enhanced Allocation. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
b8852dcf |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add support for Single-Root I/O Virtualization SR-IOV - Single Root I/O Virtualization PF - Physical Function VF - Virtual Function If SR-IOV capability is present, use it to initialize Virtual Function PCI device instances. pci_sriov_init function will read SR-IOV registers to create VF devices under the PF PCI device and also bind driver if available. This function needs to be invoked from Physical function device driver which expects VF device support, creating minimal impact on existing framework. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
e0024741 |
|
23-Jul-2020 |
Stefan Roese <sr@denx.de> |
pci: pci-uclass: Dynamically allocate the PCI regions Instead of using a fixed length pre-allocated array of regions, this patch moves to dynamically allocating the regions based on the number of available regions plus the necessary regions for DRAM banks. Since MAX_PCI_REGIONS is not needed any more, its removed completely with this patch. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Thierry Reding <treding@nvidia.com> Cc: Marek Vasut <marek.vasut+renesas@gmail.com>
|
#
143eb5b1 |
|
12-May-2020 |
Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
drivers: pci: add api to get dma regions Add api to get dma regions. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
284d062e |
|
09-Sep-2020 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
pci: add a few ARI related defines Add a few defines related to PCI ARI configuration. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
51eeae91 |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add VF BAR map support for Enhanced Allocation Makes dm_pci_map_bar API available to map BAR for Virtual function PCI devices which support Enhanced Allocation. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
b8852dcf |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add support for Single-Root I/O Virtualization SR-IOV - Single Root I/O Virtualization PF - Physical Function VF - Virtual Function If SR-IOV capability is present, use it to initialize Virtual Function PCI device instances. pci_sriov_init function will read SR-IOV registers to create VF devices under the PF PCI device and also bind driver if available. This function needs to be invoked from Physical function device driver which expects VF device support, creating minimal impact on existing framework. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
e0024741 |
|
23-Jul-2020 |
Stefan Roese <sr@denx.de> |
pci: pci-uclass: Dynamically allocate the PCI regions Instead of using a fixed length pre-allocated array of regions, this patch moves to dynamically allocating the regions based on the number of available regions plus the necessary regions for DRAM banks. Since MAX_PCI_REGIONS is not needed any more, its removed completely with this patch. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Thierry Reding <treding@nvidia.com> Cc: Marek Vasut <marek.vasut+renesas@gmail.com>
|
#
143eb5b1 |
|
12-May-2020 |
Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
drivers: pci: add api to get dma regions Add api to get dma regions. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
284d062e |
|
09-Sep-2020 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
pci: add a few ARI related defines Add a few defines related to PCI ARI configuration. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
51eeae91 |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add VF BAR map support for Enhanced Allocation Makes dm_pci_map_bar API available to map BAR for Virtual function PCI devices which support Enhanced Allocation. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
b8852dcf |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add support for Single-Root I/O Virtualization SR-IOV - Single Root I/O Virtualization PF - Physical Function VF - Virtual Function If SR-IOV capability is present, use it to initialize Virtual Function PCI device instances. pci_sriov_init function will read SR-IOV registers to create VF devices under the PF PCI device and also bind driver if available. This function needs to be invoked from Physical function device driver which expects VF device support, creating minimal impact on existing framework. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
e0024741 |
|
23-Jul-2020 |
Stefan Roese <sr@denx.de> |
pci: pci-uclass: Dynamically allocate the PCI regions Instead of using a fixed length pre-allocated array of regions, this patch moves to dynamically allocating the regions based on the number of available regions plus the necessary regions for DRAM banks. Since MAX_PCI_REGIONS is not needed any more, its removed completely with this patch. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Thierry Reding <treding@nvidia.com> Cc: Marek Vasut <marek.vasut+renesas@gmail.com>
|
#
143eb5b1 |
|
12-May-2020 |
Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
drivers: pci: add api to get dma regions Add api to get dma regions. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
284d062e |
|
09-Sep-2020 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
pci: add a few ARI related defines Add a few defines related to PCI ARI configuration. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
51eeae91 |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add VF BAR map support for Enhanced Allocation Makes dm_pci_map_bar API available to map BAR for Virtual function PCI devices which support Enhanced Allocation. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
b8852dcf |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add support for Single-Root I/O Virtualization SR-IOV - Single Root I/O Virtualization PF - Physical Function VF - Virtual Function If SR-IOV capability is present, use it to initialize Virtual Function PCI device instances. pci_sriov_init function will read SR-IOV registers to create VF devices under the PF PCI device and also bind driver if available. This function needs to be invoked from Physical function device driver which expects VF device support, creating minimal impact on existing framework. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
e0024741 |
|
23-Jul-2020 |
Stefan Roese <sr@denx.de> |
pci: pci-uclass: Dynamically allocate the PCI regions Instead of using a fixed length pre-allocated array of regions, this patch moves to dynamically allocating the regions based on the number of available regions plus the necessary regions for DRAM banks. Since MAX_PCI_REGIONS is not needed any more, its removed completely with this patch. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Thierry Reding <treding@nvidia.com> Cc: Marek Vasut <marek.vasut+renesas@gmail.com>
|
#
143eb5b1 |
|
12-May-2020 |
Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
drivers: pci: add api to get dma regions Add api to get dma regions. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
284d062e |
|
09-Sep-2020 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
pci: add a few ARI related defines Add a few defines related to PCI ARI configuration. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
51eeae91 |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add VF BAR map support for Enhanced Allocation Makes dm_pci_map_bar API available to map BAR for Virtual function PCI devices which support Enhanced Allocation. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
b8852dcf |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add support for Single-Root I/O Virtualization SR-IOV - Single Root I/O Virtualization PF - Physical Function VF - Virtual Function If SR-IOV capability is present, use it to initialize Virtual Function PCI device instances. pci_sriov_init function will read SR-IOV registers to create VF devices under the PF PCI device and also bind driver if available. This function needs to be invoked from Physical function device driver which expects VF device support, creating minimal impact on existing framework. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
e0024741 |
|
23-Jul-2020 |
Stefan Roese <sr@denx.de> |
pci: pci-uclass: Dynamically allocate the PCI regions Instead of using a fixed length pre-allocated array of regions, this patch moves to dynamically allocating the regions based on the number of available regions plus the necessary regions for DRAM banks. Since MAX_PCI_REGIONS is not needed any more, its removed completely with this patch. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Thierry Reding <treding@nvidia.com> Cc: Marek Vasut <marek.vasut+renesas@gmail.com>
|
#
143eb5b1 |
|
12-May-2020 |
Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
drivers: pci: add api to get dma regions Add api to get dma regions. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
284d062e |
|
09-Sep-2020 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
pci: add a few ARI related defines Add a few defines related to PCI ARI configuration. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
51eeae91 |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add VF BAR map support for Enhanced Allocation Makes dm_pci_map_bar API available to map BAR for Virtual function PCI devices which support Enhanced Allocation. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
b8852dcf |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add support for Single-Root I/O Virtualization SR-IOV - Single Root I/O Virtualization PF - Physical Function VF - Virtual Function If SR-IOV capability is present, use it to initialize Virtual Function PCI device instances. pci_sriov_init function will read SR-IOV registers to create VF devices under the PF PCI device and also bind driver if available. This function needs to be invoked from Physical function device driver which expects VF device support, creating minimal impact on existing framework. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
e0024741 |
|
23-Jul-2020 |
Stefan Roese <sr@denx.de> |
pci: pci-uclass: Dynamically allocate the PCI regions Instead of using a fixed length pre-allocated array of regions, this patch moves to dynamically allocating the regions based on the number of available regions plus the necessary regions for DRAM banks. Since MAX_PCI_REGIONS is not needed any more, its removed completely with this patch. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Thierry Reding <treding@nvidia.com> Cc: Marek Vasut <marek.vasut+renesas@gmail.com>
|
#
143eb5b1 |
|
12-May-2020 |
Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
drivers: pci: add api to get dma regions Add api to get dma regions. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
284d062e |
|
09-Sep-2020 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
pci: add a few ARI related defines Add a few defines related to PCI ARI configuration. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
51eeae91 |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add VF BAR map support for Enhanced Allocation Makes dm_pci_map_bar API available to map BAR for Virtual function PCI devices which support Enhanced Allocation. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
b8852dcf |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add support for Single-Root I/O Virtualization SR-IOV - Single Root I/O Virtualization PF - Physical Function VF - Virtual Function If SR-IOV capability is present, use it to initialize Virtual Function PCI device instances. pci_sriov_init function will read SR-IOV registers to create VF devices under the PF PCI device and also bind driver if available. This function needs to be invoked from Physical function device driver which expects VF device support, creating minimal impact on existing framework. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
e0024741 |
|
23-Jul-2020 |
Stefan Roese <sr@denx.de> |
pci: pci-uclass: Dynamically allocate the PCI regions Instead of using a fixed length pre-allocated array of regions, this patch moves to dynamically allocating the regions based on the number of available regions plus the necessary regions for DRAM banks. Since MAX_PCI_REGIONS is not needed any more, its removed completely with this patch. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Thierry Reding <treding@nvidia.com> Cc: Marek Vasut <marek.vasut+renesas@gmail.com>
|
#
143eb5b1 |
|
12-May-2020 |
Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
drivers: pci: add api to get dma regions Add api to get dma regions. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
284d062e |
|
09-Sep-2020 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
pci: add a few ARI related defines Add a few defines related to PCI ARI configuration. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
51eeae91 |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add VF BAR map support for Enhanced Allocation Makes dm_pci_map_bar API available to map BAR for Virtual function PCI devices which support Enhanced Allocation. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
b8852dcf |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add support for Single-Root I/O Virtualization SR-IOV - Single Root I/O Virtualization PF - Physical Function VF - Virtual Function If SR-IOV capability is present, use it to initialize Virtual Function PCI device instances. pci_sriov_init function will read SR-IOV registers to create VF devices under the PF PCI device and also bind driver if available. This function needs to be invoked from Physical function device driver which expects VF device support, creating minimal impact on existing framework. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
e0024741 |
|
23-Jul-2020 |
Stefan Roese <sr@denx.de> |
pci: pci-uclass: Dynamically allocate the PCI regions Instead of using a fixed length pre-allocated array of regions, this patch moves to dynamically allocating the regions based on the number of available regions plus the necessary regions for DRAM banks. Since MAX_PCI_REGIONS is not needed any more, its removed completely with this patch. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Thierry Reding <treding@nvidia.com> Cc: Marek Vasut <marek.vasut+renesas@gmail.com>
|
#
143eb5b1 |
|
12-May-2020 |
Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
drivers: pci: add api to get dma regions Add api to get dma regions. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
284d062e |
|
09-Sep-2020 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
pci: add a few ARI related defines Add a few defines related to PCI ARI configuration. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
51eeae91 |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add VF BAR map support for Enhanced Allocation Makes dm_pci_map_bar API available to map BAR for Virtual function PCI devices which support Enhanced Allocation. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
b8852dcf |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add support for Single-Root I/O Virtualization SR-IOV - Single Root I/O Virtualization PF - Physical Function VF - Virtual Function If SR-IOV capability is present, use it to initialize Virtual Function PCI device instances. pci_sriov_init function will read SR-IOV registers to create VF devices under the PF PCI device and also bind driver if available. This function needs to be invoked from Physical function device driver which expects VF device support, creating minimal impact on existing framework. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
e0024741 |
|
23-Jul-2020 |
Stefan Roese <sr@denx.de> |
pci: pci-uclass: Dynamically allocate the PCI regions Instead of using a fixed length pre-allocated array of regions, this patch moves to dynamically allocating the regions based on the number of available regions plus the necessary regions for DRAM banks. Since MAX_PCI_REGIONS is not needed any more, its removed completely with this patch. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Thierry Reding <treding@nvidia.com> Cc: Marek Vasut <marek.vasut+renesas@gmail.com>
|
#
143eb5b1 |
|
12-May-2020 |
Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
drivers: pci: add api to get dma regions Add api to get dma regions. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
284d062e |
|
09-Sep-2020 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
pci: add a few ARI related defines Add a few defines related to PCI ARI configuration. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
51eeae91 |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add VF BAR map support for Enhanced Allocation Makes dm_pci_map_bar API available to map BAR for Virtual function PCI devices which support Enhanced Allocation. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
b8852dcf |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add support for Single-Root I/O Virtualization SR-IOV - Single Root I/O Virtualization PF - Physical Function VF - Virtual Function If SR-IOV capability is present, use it to initialize Virtual Function PCI device instances. pci_sriov_init function will read SR-IOV registers to create VF devices under the PF PCI device and also bind driver if available. This function needs to be invoked from Physical function device driver which expects VF device support, creating minimal impact on existing framework. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
e0024741 |
|
23-Jul-2020 |
Stefan Roese <sr@denx.de> |
pci: pci-uclass: Dynamically allocate the PCI regions Instead of using a fixed length pre-allocated array of regions, this patch moves to dynamically allocating the regions based on the number of available regions plus the necessary regions for DRAM banks. Since MAX_PCI_REGIONS is not needed any more, its removed completely with this patch. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Thierry Reding <treding@nvidia.com> Cc: Marek Vasut <marek.vasut+renesas@gmail.com>
|
#
143eb5b1 |
|
12-May-2020 |
Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
drivers: pci: add api to get dma regions Add api to get dma regions. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
284d062e |
|
09-Sep-2020 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
pci: add a few ARI related defines Add a few defines related to PCI ARI configuration. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
51eeae91 |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add VF BAR map support for Enhanced Allocation Makes dm_pci_map_bar API available to map BAR for Virtual function PCI devices which support Enhanced Allocation. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
b8852dcf |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add support for Single-Root I/O Virtualization SR-IOV - Single Root I/O Virtualization PF - Physical Function VF - Virtual Function If SR-IOV capability is present, use it to initialize Virtual Function PCI device instances. pci_sriov_init function will read SR-IOV registers to create VF devices under the PF PCI device and also bind driver if available. This function needs to be invoked from Physical function device driver which expects VF device support, creating minimal impact on existing framework. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
e0024741 |
|
23-Jul-2020 |
Stefan Roese <sr@denx.de> |
pci: pci-uclass: Dynamically allocate the PCI regions Instead of using a fixed length pre-allocated array of regions, this patch moves to dynamically allocating the regions based on the number of available regions plus the necessary regions for DRAM banks. Since MAX_PCI_REGIONS is not needed any more, its removed completely with this patch. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Thierry Reding <treding@nvidia.com> Cc: Marek Vasut <marek.vasut+renesas@gmail.com>
|
#
143eb5b1 |
|
12-May-2020 |
Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
drivers: pci: add api to get dma regions Add api to get dma regions. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
284d062e |
|
09-Sep-2020 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
pci: add a few ARI related defines Add a few defines related to PCI ARI configuration. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
51eeae91 |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add VF BAR map support for Enhanced Allocation Makes dm_pci_map_bar API available to map BAR for Virtual function PCI devices which support Enhanced Allocation. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
b8852dcf |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add support for Single-Root I/O Virtualization SR-IOV - Single Root I/O Virtualization PF - Physical Function VF - Virtual Function If SR-IOV capability is present, use it to initialize Virtual Function PCI device instances. pci_sriov_init function will read SR-IOV registers to create VF devices under the PF PCI device and also bind driver if available. This function needs to be invoked from Physical function device driver which expects VF device support, creating minimal impact on existing framework. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
e0024741 |
|
23-Jul-2020 |
Stefan Roese <sr@denx.de> |
pci: pci-uclass: Dynamically allocate the PCI regions Instead of using a fixed length pre-allocated array of regions, this patch moves to dynamically allocating the regions based on the number of available regions plus the necessary regions for DRAM banks. Since MAX_PCI_REGIONS is not needed any more, its removed completely with this patch. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Thierry Reding <treding@nvidia.com> Cc: Marek Vasut <marek.vasut+renesas@gmail.com>
|
#
143eb5b1 |
|
12-May-2020 |
Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
drivers: pci: add api to get dma regions Add api to get dma regions. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
284d062e |
|
09-Sep-2020 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
pci: add a few ARI related defines Add a few defines related to PCI ARI configuration. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
51eeae91 |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add VF BAR map support for Enhanced Allocation Makes dm_pci_map_bar API available to map BAR for Virtual function PCI devices which support Enhanced Allocation. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
b8852dcf |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add support for Single-Root I/O Virtualization SR-IOV - Single Root I/O Virtualization PF - Physical Function VF - Virtual Function If SR-IOV capability is present, use it to initialize Virtual Function PCI device instances. pci_sriov_init function will read SR-IOV registers to create VF devices under the PF PCI device and also bind driver if available. This function needs to be invoked from Physical function device driver which expects VF device support, creating minimal impact on existing framework. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
e0024741 |
|
23-Jul-2020 |
Stefan Roese <sr@denx.de> |
pci: pci-uclass: Dynamically allocate the PCI regions Instead of using a fixed length pre-allocated array of regions, this patch moves to dynamically allocating the regions based on the number of available regions plus the necessary regions for DRAM banks. Since MAX_PCI_REGIONS is not needed any more, its removed completely with this patch. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Thierry Reding <treding@nvidia.com> Cc: Marek Vasut <marek.vasut+renesas@gmail.com>
|
#
143eb5b1 |
|
12-May-2020 |
Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
drivers: pci: add api to get dma regions Add api to get dma regions. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
284d062e |
|
09-Sep-2020 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
pci: add a few ARI related defines Add a few defines related to PCI ARI configuration. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
51eeae91 |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add VF BAR map support for Enhanced Allocation Makes dm_pci_map_bar API available to map BAR for Virtual function PCI devices which support Enhanced Allocation. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
b8852dcf |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add support for Single-Root I/O Virtualization SR-IOV - Single Root I/O Virtualization PF - Physical Function VF - Virtual Function If SR-IOV capability is present, use it to initialize Virtual Function PCI device instances. pci_sriov_init function will read SR-IOV registers to create VF devices under the PF PCI device and also bind driver if available. This function needs to be invoked from Physical function device driver which expects VF device support, creating minimal impact on existing framework. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
e0024741 |
|
23-Jul-2020 |
Stefan Roese <sr@denx.de> |
pci: pci-uclass: Dynamically allocate the PCI regions Instead of using a fixed length pre-allocated array of regions, this patch moves to dynamically allocating the regions based on the number of available regions plus the necessary regions for DRAM banks. Since MAX_PCI_REGIONS is not needed any more, its removed completely with this patch. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Thierry Reding <treding@nvidia.com> Cc: Marek Vasut <marek.vasut+renesas@gmail.com>
|
#
143eb5b1 |
|
12-May-2020 |
Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
drivers: pci: add api to get dma regions Add api to get dma regions. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
284d062e |
|
09-Sep-2020 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
pci: add a few ARI related defines Add a few defines related to PCI ARI configuration. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
51eeae91 |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add VF BAR map support for Enhanced Allocation Makes dm_pci_map_bar API available to map BAR for Virtual function PCI devices which support Enhanced Allocation. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
b8852dcf |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add support for Single-Root I/O Virtualization SR-IOV - Single Root I/O Virtualization PF - Physical Function VF - Virtual Function If SR-IOV capability is present, use it to initialize Virtual Function PCI device instances. pci_sriov_init function will read SR-IOV registers to create VF devices under the PF PCI device and also bind driver if available. This function needs to be invoked from Physical function device driver which expects VF device support, creating minimal impact on existing framework. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
e0024741 |
|
23-Jul-2020 |
Stefan Roese <sr@denx.de> |
pci: pci-uclass: Dynamically allocate the PCI regions Instead of using a fixed length pre-allocated array of regions, this patch moves to dynamically allocating the regions based on the number of available regions plus the necessary regions for DRAM banks. Since MAX_PCI_REGIONS is not needed any more, its removed completely with this patch. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Thierry Reding <treding@nvidia.com> Cc: Marek Vasut <marek.vasut+renesas@gmail.com>
|
#
143eb5b1 |
|
12-May-2020 |
Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
drivers: pci: add api to get dma regions Add api to get dma regions. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
284d062e |
|
09-Sep-2020 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
pci: add a few ARI related defines Add a few defines related to PCI ARI configuration. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
51eeae91 |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add VF BAR map support for Enhanced Allocation Makes dm_pci_map_bar API available to map BAR for Virtual function PCI devices which support Enhanced Allocation. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
b8852dcf |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add support for Single-Root I/O Virtualization SR-IOV - Single Root I/O Virtualization PF - Physical Function VF - Virtual Function If SR-IOV capability is present, use it to initialize Virtual Function PCI device instances. pci_sriov_init function will read SR-IOV registers to create VF devices under the PF PCI device and also bind driver if available. This function needs to be invoked from Physical function device driver which expects VF device support, creating minimal impact on existing framework. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
e0024741 |
|
23-Jul-2020 |
Stefan Roese <sr@denx.de> |
pci: pci-uclass: Dynamically allocate the PCI regions Instead of using a fixed length pre-allocated array of regions, this patch moves to dynamically allocating the regions based on the number of available regions plus the necessary regions for DRAM banks. Since MAX_PCI_REGIONS is not needed any more, its removed completely with this patch. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Thierry Reding <treding@nvidia.com> Cc: Marek Vasut <marek.vasut+renesas@gmail.com>
|
#
143eb5b1 |
|
12-May-2020 |
Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
drivers: pci: add api to get dma regions Add api to get dma regions. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
284d062e |
|
09-Sep-2020 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
pci: add a few ARI related defines Add a few defines related to PCI ARI configuration. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
51eeae91 |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add VF BAR map support for Enhanced Allocation Makes dm_pci_map_bar API available to map BAR for Virtual function PCI devices which support Enhanced Allocation. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
b8852dcf |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add support for Single-Root I/O Virtualization SR-IOV - Single Root I/O Virtualization PF - Physical Function VF - Virtual Function If SR-IOV capability is present, use it to initialize Virtual Function PCI device instances. pci_sriov_init function will read SR-IOV registers to create VF devices under the PF PCI device and also bind driver if available. This function needs to be invoked from Physical function device driver which expects VF device support, creating minimal impact on existing framework. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
e0024741 |
|
23-Jul-2020 |
Stefan Roese <sr@denx.de> |
pci: pci-uclass: Dynamically allocate the PCI regions Instead of using a fixed length pre-allocated array of regions, this patch moves to dynamically allocating the regions based on the number of available regions plus the necessary regions for DRAM banks. Since MAX_PCI_REGIONS is not needed any more, its removed completely with this patch. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Thierry Reding <treding@nvidia.com> Cc: Marek Vasut <marek.vasut+renesas@gmail.com>
|
#
143eb5b1 |
|
12-May-2020 |
Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
drivers: pci: add api to get dma regions Add api to get dma regions. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
284d062e |
|
09-Sep-2020 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
pci: add a few ARI related defines Add a few defines related to PCI ARI configuration. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
51eeae91 |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add VF BAR map support for Enhanced Allocation Makes dm_pci_map_bar API available to map BAR for Virtual function PCI devices which support Enhanced Allocation. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
b8852dcf |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add support for Single-Root I/O Virtualization SR-IOV - Single Root I/O Virtualization PF - Physical Function VF - Virtual Function If SR-IOV capability is present, use it to initialize Virtual Function PCI device instances. pci_sriov_init function will read SR-IOV registers to create VF devices under the PF PCI device and also bind driver if available. This function needs to be invoked from Physical function device driver which expects VF device support, creating minimal impact on existing framework. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
e0024741 |
|
23-Jul-2020 |
Stefan Roese <sr@denx.de> |
pci: pci-uclass: Dynamically allocate the PCI regions Instead of using a fixed length pre-allocated array of regions, this patch moves to dynamically allocating the regions based on the number of available regions plus the necessary regions for DRAM banks. Since MAX_PCI_REGIONS is not needed any more, its removed completely with this patch. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Thierry Reding <treding@nvidia.com> Cc: Marek Vasut <marek.vasut+renesas@gmail.com>
|
#
143eb5b1 |
|
12-May-2020 |
Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
drivers: pci: add api to get dma regions Add api to get dma regions. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
284d062e |
|
09-Sep-2020 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
pci: add a few ARI related defines Add a few defines related to PCI ARI configuration. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
51eeae91 |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add VF BAR map support for Enhanced Allocation Makes dm_pci_map_bar API available to map BAR for Virtual function PCI devices which support Enhanced Allocation. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
b8852dcf |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add support for Single-Root I/O Virtualization SR-IOV - Single Root I/O Virtualization PF - Physical Function VF - Virtual Function If SR-IOV capability is present, use it to initialize Virtual Function PCI device instances. pci_sriov_init function will read SR-IOV registers to create VF devices under the PF PCI device and also bind driver if available. This function needs to be invoked from Physical function device driver which expects VF device support, creating minimal impact on existing framework. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
e0024741 |
|
23-Jul-2020 |
Stefan Roese <sr@denx.de> |
pci: pci-uclass: Dynamically allocate the PCI regions Instead of using a fixed length pre-allocated array of regions, this patch moves to dynamically allocating the regions based on the number of available regions plus the necessary regions for DRAM banks. Since MAX_PCI_REGIONS is not needed any more, its removed completely with this patch. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Thierry Reding <treding@nvidia.com> Cc: Marek Vasut <marek.vasut+renesas@gmail.com>
|
#
143eb5b1 |
|
12-May-2020 |
Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
drivers: pci: add api to get dma regions Add api to get dma regions. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
284d062e |
|
09-Sep-2020 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
pci: add a few ARI related defines Add a few defines related to PCI ARI configuration. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
51eeae91 |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add VF BAR map support for Enhanced Allocation Makes dm_pci_map_bar API available to map BAR for Virtual function PCI devices which support Enhanced Allocation. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
b8852dcf |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add support for Single-Root I/O Virtualization SR-IOV - Single Root I/O Virtualization PF - Physical Function VF - Virtual Function If SR-IOV capability is present, use it to initialize Virtual Function PCI device instances. pci_sriov_init function will read SR-IOV registers to create VF devices under the PF PCI device and also bind driver if available. This function needs to be invoked from Physical function device driver which expects VF device support, creating minimal impact on existing framework. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
e0024741 |
|
23-Jul-2020 |
Stefan Roese <sr@denx.de> |
pci: pci-uclass: Dynamically allocate the PCI regions Instead of using a fixed length pre-allocated array of regions, this patch moves to dynamically allocating the regions based on the number of available regions plus the necessary regions for DRAM banks. Since MAX_PCI_REGIONS is not needed any more, its removed completely with this patch. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Thierry Reding <treding@nvidia.com> Cc: Marek Vasut <marek.vasut+renesas@gmail.com>
|
#
143eb5b1 |
|
12-May-2020 |
Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
drivers: pci: add api to get dma regions Add api to get dma regions. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
284d062e |
|
09-Sep-2020 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
pci: add a few ARI related defines Add a few defines related to PCI ARI configuration. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
51eeae91 |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add VF BAR map support for Enhanced Allocation Makes dm_pci_map_bar API available to map BAR for Virtual function PCI devices which support Enhanced Allocation. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
b8852dcf |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add support for Single-Root I/O Virtualization SR-IOV - Single Root I/O Virtualization PF - Physical Function VF - Virtual Function If SR-IOV capability is present, use it to initialize Virtual Function PCI device instances. pci_sriov_init function will read SR-IOV registers to create VF devices under the PF PCI device and also bind driver if available. This function needs to be invoked from Physical function device driver which expects VF device support, creating minimal impact on existing framework. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
e0024741 |
|
23-Jul-2020 |
Stefan Roese <sr@denx.de> |
pci: pci-uclass: Dynamically allocate the PCI regions Instead of using a fixed length pre-allocated array of regions, this patch moves to dynamically allocating the regions based on the number of available regions plus the necessary regions for DRAM banks. Since MAX_PCI_REGIONS is not needed any more, its removed completely with this patch. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Thierry Reding <treding@nvidia.com> Cc: Marek Vasut <marek.vasut+renesas@gmail.com>
|
#
143eb5b1 |
|
12-May-2020 |
Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
drivers: pci: add api to get dma regions Add api to get dma regions. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
284d062e |
|
09-Sep-2020 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
pci: add a few ARI related defines Add a few defines related to PCI ARI configuration. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
51eeae91 |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add VF BAR map support for Enhanced Allocation Makes dm_pci_map_bar API available to map BAR for Virtual function PCI devices which support Enhanced Allocation. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
b8852dcf |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add support for Single-Root I/O Virtualization SR-IOV - Single Root I/O Virtualization PF - Physical Function VF - Virtual Function If SR-IOV capability is present, use it to initialize Virtual Function PCI device instances. pci_sriov_init function will read SR-IOV registers to create VF devices under the PF PCI device and also bind driver if available. This function needs to be invoked from Physical function device driver which expects VF device support, creating minimal impact on existing framework. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
e0024741 |
|
23-Jul-2020 |
Stefan Roese <sr@denx.de> |
pci: pci-uclass: Dynamically allocate the PCI regions Instead of using a fixed length pre-allocated array of regions, this patch moves to dynamically allocating the regions based on the number of available regions plus the necessary regions for DRAM banks. Since MAX_PCI_REGIONS is not needed any more, its removed completely with this patch. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Thierry Reding <treding@nvidia.com> Cc: Marek Vasut <marek.vasut+renesas@gmail.com>
|
#
143eb5b1 |
|
12-May-2020 |
Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
drivers: pci: add api to get dma regions Add api to get dma regions. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
284d062e |
|
09-Sep-2020 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
pci: add a few ARI related defines Add a few defines related to PCI ARI configuration. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
51eeae91 |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add VF BAR map support for Enhanced Allocation Makes dm_pci_map_bar API available to map BAR for Virtual function PCI devices which support Enhanced Allocation. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
b8852dcf |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add support for Single-Root I/O Virtualization SR-IOV - Single Root I/O Virtualization PF - Physical Function VF - Virtual Function If SR-IOV capability is present, use it to initialize Virtual Function PCI device instances. pci_sriov_init function will read SR-IOV registers to create VF devices under the PF PCI device and also bind driver if available. This function needs to be invoked from Physical function device driver which expects VF device support, creating minimal impact on existing framework. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
e0024741 |
|
23-Jul-2020 |
Stefan Roese <sr@denx.de> |
pci: pci-uclass: Dynamically allocate the PCI regions Instead of using a fixed length pre-allocated array of regions, this patch moves to dynamically allocating the regions based on the number of available regions plus the necessary regions for DRAM banks. Since MAX_PCI_REGIONS is not needed any more, its removed completely with this patch. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Thierry Reding <treding@nvidia.com> Cc: Marek Vasut <marek.vasut+renesas@gmail.com>
|
#
143eb5b1 |
|
12-May-2020 |
Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
drivers: pci: add api to get dma regions Add api to get dma regions. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
284d062e |
|
09-Sep-2020 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
pci: add a few ARI related defines Add a few defines related to PCI ARI configuration. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
51eeae91 |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add VF BAR map support for Enhanced Allocation Makes dm_pci_map_bar API available to map BAR for Virtual function PCI devices which support Enhanced Allocation. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
b8852dcf |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add support for Single-Root I/O Virtualization SR-IOV - Single Root I/O Virtualization PF - Physical Function VF - Virtual Function If SR-IOV capability is present, use it to initialize Virtual Function PCI device instances. pci_sriov_init function will read SR-IOV registers to create VF devices under the PF PCI device and also bind driver if available. This function needs to be invoked from Physical function device driver which expects VF device support, creating minimal impact on existing framework. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
e0024741 |
|
23-Jul-2020 |
Stefan Roese <sr@denx.de> |
pci: pci-uclass: Dynamically allocate the PCI regions Instead of using a fixed length pre-allocated array of regions, this patch moves to dynamically allocating the regions based on the number of available regions plus the necessary regions for DRAM banks. Since MAX_PCI_REGIONS is not needed any more, its removed completely with this patch. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Thierry Reding <treding@nvidia.com> Cc: Marek Vasut <marek.vasut+renesas@gmail.com>
|
#
143eb5b1 |
|
12-May-2020 |
Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
drivers: pci: add api to get dma regions Add api to get dma regions. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
284d062e |
|
09-Sep-2020 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
pci: add a few ARI related defines Add a few defines related to PCI ARI configuration. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
51eeae91 |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add VF BAR map support for Enhanced Allocation Makes dm_pci_map_bar API available to map BAR for Virtual function PCI devices which support Enhanced Allocation. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
b8852dcf |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add support for Single-Root I/O Virtualization SR-IOV - Single Root I/O Virtualization PF - Physical Function VF - Virtual Function If SR-IOV capability is present, use it to initialize Virtual Function PCI device instances. pci_sriov_init function will read SR-IOV registers to create VF devices under the PF PCI device and also bind driver if available. This function needs to be invoked from Physical function device driver which expects VF device support, creating minimal impact on existing framework. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
e0024741 |
|
23-Jul-2020 |
Stefan Roese <sr@denx.de> |
pci: pci-uclass: Dynamically allocate the PCI regions Instead of using a fixed length pre-allocated array of regions, this patch moves to dynamically allocating the regions based on the number of available regions plus the necessary regions for DRAM banks. Since MAX_PCI_REGIONS is not needed any more, its removed completely with this patch. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Thierry Reding <treding@nvidia.com> Cc: Marek Vasut <marek.vasut+renesas@gmail.com>
|
#
143eb5b1 |
|
12-May-2020 |
Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
drivers: pci: add api to get dma regions Add api to get dma regions. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
284d062e |
|
09-Sep-2020 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
pci: add a few ARI related defines Add a few defines related to PCI ARI configuration. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
51eeae91 |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add VF BAR map support for Enhanced Allocation Makes dm_pci_map_bar API available to map BAR for Virtual function PCI devices which support Enhanced Allocation. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
b8852dcf |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add support for Single-Root I/O Virtualization SR-IOV - Single Root I/O Virtualization PF - Physical Function VF - Virtual Function If SR-IOV capability is present, use it to initialize Virtual Function PCI device instances. pci_sriov_init function will read SR-IOV registers to create VF devices under the PF PCI device and also bind driver if available. This function needs to be invoked from Physical function device driver which expects VF device support, creating minimal impact on existing framework. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
e0024741 |
|
23-Jul-2020 |
Stefan Roese <sr@denx.de> |
pci: pci-uclass: Dynamically allocate the PCI regions Instead of using a fixed length pre-allocated array of regions, this patch moves to dynamically allocating the regions based on the number of available regions plus the necessary regions for DRAM banks. Since MAX_PCI_REGIONS is not needed any more, its removed completely with this patch. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Thierry Reding <treding@nvidia.com> Cc: Marek Vasut <marek.vasut+renesas@gmail.com>
|
#
143eb5b1 |
|
12-May-2020 |
Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
drivers: pci: add api to get dma regions Add api to get dma regions. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
284d062e |
|
09-Sep-2020 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
pci: add a few ARI related defines Add a few defines related to PCI ARI configuration. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
51eeae91 |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add VF BAR map support for Enhanced Allocation Makes dm_pci_map_bar API available to map BAR for Virtual function PCI devices which support Enhanced Allocation. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
b8852dcf |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add support for Single-Root I/O Virtualization SR-IOV - Single Root I/O Virtualization PF - Physical Function VF - Virtual Function If SR-IOV capability is present, use it to initialize Virtual Function PCI device instances. pci_sriov_init function will read SR-IOV registers to create VF devices under the PF PCI device and also bind driver if available. This function needs to be invoked from Physical function device driver which expects VF device support, creating minimal impact on existing framework. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
e0024741 |
|
23-Jul-2020 |
Stefan Roese <sr@denx.de> |
pci: pci-uclass: Dynamically allocate the PCI regions Instead of using a fixed length pre-allocated array of regions, this patch moves to dynamically allocating the regions based on the number of available regions plus the necessary regions for DRAM banks. Since MAX_PCI_REGIONS is not needed any more, its removed completely with this patch. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Thierry Reding <treding@nvidia.com> Cc: Marek Vasut <marek.vasut+renesas@gmail.com>
|
#
143eb5b1 |
|
12-May-2020 |
Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
drivers: pci: add api to get dma regions Add api to get dma regions. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
284d062e |
|
09-Sep-2020 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
pci: add a few ARI related defines Add a few defines related to PCI ARI configuration. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
51eeae91 |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add VF BAR map support for Enhanced Allocation Makes dm_pci_map_bar API available to map BAR for Virtual function PCI devices which support Enhanced Allocation. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
b8852dcf |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add support for Single-Root I/O Virtualization SR-IOV - Single Root I/O Virtualization PF - Physical Function VF - Virtual Function If SR-IOV capability is present, use it to initialize Virtual Function PCI device instances. pci_sriov_init function will read SR-IOV registers to create VF devices under the PF PCI device and also bind driver if available. This function needs to be invoked from Physical function device driver which expects VF device support, creating minimal impact on existing framework. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
e0024741 |
|
23-Jul-2020 |
Stefan Roese <sr@denx.de> |
pci: pci-uclass: Dynamically allocate the PCI regions Instead of using a fixed length pre-allocated array of regions, this patch moves to dynamically allocating the regions based on the number of available regions plus the necessary regions for DRAM banks. Since MAX_PCI_REGIONS is not needed any more, its removed completely with this patch. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Thierry Reding <treding@nvidia.com> Cc: Marek Vasut <marek.vasut+renesas@gmail.com>
|
#
143eb5b1 |
|
12-May-2020 |
Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
drivers: pci: add api to get dma regions Add api to get dma regions. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
284d062e |
|
09-Sep-2020 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
pci: add a few ARI related defines Add a few defines related to PCI ARI configuration. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
51eeae91 |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add VF BAR map support for Enhanced Allocation Makes dm_pci_map_bar API available to map BAR for Virtual function PCI devices which support Enhanced Allocation. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
b8852dcf |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add support for Single-Root I/O Virtualization SR-IOV - Single Root I/O Virtualization PF - Physical Function VF - Virtual Function If SR-IOV capability is present, use it to initialize Virtual Function PCI device instances. pci_sriov_init function will read SR-IOV registers to create VF devices under the PF PCI device and also bind driver if available. This function needs to be invoked from Physical function device driver which expects VF device support, creating minimal impact on existing framework. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
e0024741 |
|
23-Jul-2020 |
Stefan Roese <sr@denx.de> |
pci: pci-uclass: Dynamically allocate the PCI regions Instead of using a fixed length pre-allocated array of regions, this patch moves to dynamically allocating the regions based on the number of available regions plus the necessary regions for DRAM banks. Since MAX_PCI_REGIONS is not needed any more, its removed completely with this patch. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Thierry Reding <treding@nvidia.com> Cc: Marek Vasut <marek.vasut+renesas@gmail.com>
|
#
143eb5b1 |
|
12-May-2020 |
Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
drivers: pci: add api to get dma regions Add api to get dma regions. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
284d062e |
|
09-Sep-2020 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
pci: add a few ARI related defines Add a few defines related to PCI ARI configuration. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
51eeae91 |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add VF BAR map support for Enhanced Allocation Makes dm_pci_map_bar API available to map BAR for Virtual function PCI devices which support Enhanced Allocation. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
b8852dcf |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add support for Single-Root I/O Virtualization SR-IOV - Single Root I/O Virtualization PF - Physical Function VF - Virtual Function If SR-IOV capability is present, use it to initialize Virtual Function PCI device instances. pci_sriov_init function will read SR-IOV registers to create VF devices under the PF PCI device and also bind driver if available. This function needs to be invoked from Physical function device driver which expects VF device support, creating minimal impact on existing framework. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
e0024741 |
|
23-Jul-2020 |
Stefan Roese <sr@denx.de> |
pci: pci-uclass: Dynamically allocate the PCI regions Instead of using a fixed length pre-allocated array of regions, this patch moves to dynamically allocating the regions based on the number of available regions plus the necessary regions for DRAM banks. Since MAX_PCI_REGIONS is not needed any more, its removed completely with this patch. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Thierry Reding <treding@nvidia.com> Cc: Marek Vasut <marek.vasut+renesas@gmail.com>
|
#
143eb5b1 |
|
12-May-2020 |
Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
drivers: pci: add api to get dma regions Add api to get dma regions. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
284d062e |
|
09-Sep-2020 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
pci: add a few ARI related defines Add a few defines related to PCI ARI configuration. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
51eeae91 |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add VF BAR map support for Enhanced Allocation Makes dm_pci_map_bar API available to map BAR for Virtual function PCI devices which support Enhanced Allocation. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
b8852dcf |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add support for Single-Root I/O Virtualization SR-IOV - Single Root I/O Virtualization PF - Physical Function VF - Virtual Function If SR-IOV capability is present, use it to initialize Virtual Function PCI device instances. pci_sriov_init function will read SR-IOV registers to create VF devices under the PF PCI device and also bind driver if available. This function needs to be invoked from Physical function device driver which expects VF device support, creating minimal impact on existing framework. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
e0024741 |
|
23-Jul-2020 |
Stefan Roese <sr@denx.de> |
pci: pci-uclass: Dynamically allocate the PCI regions Instead of using a fixed length pre-allocated array of regions, this patch moves to dynamically allocating the regions based on the number of available regions plus the necessary regions for DRAM banks. Since MAX_PCI_REGIONS is not needed any more, its removed completely with this patch. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Thierry Reding <treding@nvidia.com> Cc: Marek Vasut <marek.vasut+renesas@gmail.com>
|
#
143eb5b1 |
|
12-May-2020 |
Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
drivers: pci: add api to get dma regions Add api to get dma regions. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
284d062e |
|
09-Sep-2020 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
pci: add a few ARI related defines Add a few defines related to PCI ARI configuration. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
51eeae91 |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add VF BAR map support for Enhanced Allocation Makes dm_pci_map_bar API available to map BAR for Virtual function PCI devices which support Enhanced Allocation. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
b8852dcf |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add support for Single-Root I/O Virtualization SR-IOV - Single Root I/O Virtualization PF - Physical Function VF - Virtual Function If SR-IOV capability is present, use it to initialize Virtual Function PCI device instances. pci_sriov_init function will read SR-IOV registers to create VF devices under the PF PCI device and also bind driver if available. This function needs to be invoked from Physical function device driver which expects VF device support, creating minimal impact on existing framework. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
e0024741 |
|
23-Jul-2020 |
Stefan Roese <sr@denx.de> |
pci: pci-uclass: Dynamically allocate the PCI regions Instead of using a fixed length pre-allocated array of regions, this patch moves to dynamically allocating the regions based on the number of available regions plus the necessary regions for DRAM banks. Since MAX_PCI_REGIONS is not needed any more, its removed completely with this patch. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Thierry Reding <treding@nvidia.com> Cc: Marek Vasut <marek.vasut+renesas@gmail.com>
|
#
143eb5b1 |
|
12-May-2020 |
Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
drivers: pci: add api to get dma regions Add api to get dma regions. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
284d062e |
|
09-Sep-2020 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
pci: add a few ARI related defines Add a few defines related to PCI ARI configuration. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
51eeae91 |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add VF BAR map support for Enhanced Allocation Makes dm_pci_map_bar API available to map BAR for Virtual function PCI devices which support Enhanced Allocation. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
b8852dcf |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add support for Single-Root I/O Virtualization SR-IOV - Single Root I/O Virtualization PF - Physical Function VF - Virtual Function If SR-IOV capability is present, use it to initialize Virtual Function PCI device instances. pci_sriov_init function will read SR-IOV registers to create VF devices under the PF PCI device and also bind driver if available. This function needs to be invoked from Physical function device driver which expects VF device support, creating minimal impact on existing framework. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
e0024741 |
|
23-Jul-2020 |
Stefan Roese <sr@denx.de> |
pci: pci-uclass: Dynamically allocate the PCI regions Instead of using a fixed length pre-allocated array of regions, this patch moves to dynamically allocating the regions based on the number of available regions plus the necessary regions for DRAM banks. Since MAX_PCI_REGIONS is not needed any more, its removed completely with this patch. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Thierry Reding <treding@nvidia.com> Cc: Marek Vasut <marek.vasut+renesas@gmail.com>
|
#
143eb5b1 |
|
12-May-2020 |
Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
drivers: pci: add api to get dma regions Add api to get dma regions. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
284d062e |
|
09-Sep-2020 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
pci: add a few ARI related defines Add a few defines related to PCI ARI configuration. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
51eeae91 |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add VF BAR map support for Enhanced Allocation Makes dm_pci_map_bar API available to map BAR for Virtual function PCI devices which support Enhanced Allocation. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
b8852dcf |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add support for Single-Root I/O Virtualization SR-IOV - Single Root I/O Virtualization PF - Physical Function VF - Virtual Function If SR-IOV capability is present, use it to initialize Virtual Function PCI device instances. pci_sriov_init function will read SR-IOV registers to create VF devices under the PF PCI device and also bind driver if available. This function needs to be invoked from Physical function device driver which expects VF device support, creating minimal impact on existing framework. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
e0024741 |
|
23-Jul-2020 |
Stefan Roese <sr@denx.de> |
pci: pci-uclass: Dynamically allocate the PCI regions Instead of using a fixed length pre-allocated array of regions, this patch moves to dynamically allocating the regions based on the number of available regions plus the necessary regions for DRAM banks. Since MAX_PCI_REGIONS is not needed any more, its removed completely with this patch. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Thierry Reding <treding@nvidia.com> Cc: Marek Vasut <marek.vasut+renesas@gmail.com>
|
#
143eb5b1 |
|
12-May-2020 |
Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
drivers: pci: add api to get dma regions Add api to get dma regions. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
284d062e |
|
09-Sep-2020 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
pci: add a few ARI related defines Add a few defines related to PCI ARI configuration. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
51eeae91 |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add VF BAR map support for Enhanced Allocation Makes dm_pci_map_bar API available to map BAR for Virtual function PCI devices which support Enhanced Allocation. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
b8852dcf |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add support for Single-Root I/O Virtualization SR-IOV - Single Root I/O Virtualization PF - Physical Function VF - Virtual Function If SR-IOV capability is present, use it to initialize Virtual Function PCI device instances. pci_sriov_init function will read SR-IOV registers to create VF devices under the PF PCI device and also bind driver if available. This function needs to be invoked from Physical function device driver which expects VF device support, creating minimal impact on existing framework. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
e0024741 |
|
23-Jul-2020 |
Stefan Roese <sr@denx.de> |
pci: pci-uclass: Dynamically allocate the PCI regions Instead of using a fixed length pre-allocated array of regions, this patch moves to dynamically allocating the regions based on the number of available regions plus the necessary regions for DRAM banks. Since MAX_PCI_REGIONS is not needed any more, its removed completely with this patch. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Thierry Reding <treding@nvidia.com> Cc: Marek Vasut <marek.vasut+renesas@gmail.com>
|
#
143eb5b1 |
|
12-May-2020 |
Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
drivers: pci: add api to get dma regions Add api to get dma regions. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
284d062e |
|
09-Sep-2020 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
pci: add a few ARI related defines Add a few defines related to PCI ARI configuration. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
51eeae91 |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add VF BAR map support for Enhanced Allocation Makes dm_pci_map_bar API available to map BAR for Virtual function PCI devices which support Enhanced Allocation. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
b8852dcf |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add support for Single-Root I/O Virtualization SR-IOV - Single Root I/O Virtualization PF - Physical Function VF - Virtual Function If SR-IOV capability is present, use it to initialize Virtual Function PCI device instances. pci_sriov_init function will read SR-IOV registers to create VF devices under the PF PCI device and also bind driver if available. This function needs to be invoked from Physical function device driver which expects VF device support, creating minimal impact on existing framework. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
e0024741 |
|
23-Jul-2020 |
Stefan Roese <sr@denx.de> |
pci: pci-uclass: Dynamically allocate the PCI regions Instead of using a fixed length pre-allocated array of regions, this patch moves to dynamically allocating the regions based on the number of available regions plus the necessary regions for DRAM banks. Since MAX_PCI_REGIONS is not needed any more, its removed completely with this patch. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Thierry Reding <treding@nvidia.com> Cc: Marek Vasut <marek.vasut+renesas@gmail.com>
|
#
143eb5b1 |
|
12-May-2020 |
Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
drivers: pci: add api to get dma regions Add api to get dma regions. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
284d062e |
|
09-Sep-2020 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
pci: add a few ARI related defines Add a few defines related to PCI ARI configuration. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
51eeae91 |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add VF BAR map support for Enhanced Allocation Makes dm_pci_map_bar API available to map BAR for Virtual function PCI devices which support Enhanced Allocation. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
b8852dcf |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add support for Single-Root I/O Virtualization SR-IOV - Single Root I/O Virtualization PF - Physical Function VF - Virtual Function If SR-IOV capability is present, use it to initialize Virtual Function PCI device instances. pci_sriov_init function will read SR-IOV registers to create VF devices under the PF PCI device and also bind driver if available. This function needs to be invoked from Physical function device driver which expects VF device support, creating minimal impact on existing framework. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
e0024741 |
|
23-Jul-2020 |
Stefan Roese <sr@denx.de> |
pci: pci-uclass: Dynamically allocate the PCI regions Instead of using a fixed length pre-allocated array of regions, this patch moves to dynamically allocating the regions based on the number of available regions plus the necessary regions for DRAM banks. Since MAX_PCI_REGIONS is not needed any more, its removed completely with this patch. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Thierry Reding <treding@nvidia.com> Cc: Marek Vasut <marek.vasut+renesas@gmail.com>
|
#
143eb5b1 |
|
12-May-2020 |
Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
drivers: pci: add api to get dma regions Add api to get dma regions. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
284d062e |
|
09-Sep-2020 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
pci: add a few ARI related defines Add a few defines related to PCI ARI configuration. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
51eeae91 |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add VF BAR map support for Enhanced Allocation Makes dm_pci_map_bar API available to map BAR for Virtual function PCI devices which support Enhanced Allocation. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
b8852dcf |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add support for Single-Root I/O Virtualization SR-IOV - Single Root I/O Virtualization PF - Physical Function VF - Virtual Function If SR-IOV capability is present, use it to initialize Virtual Function PCI device instances. pci_sriov_init function will read SR-IOV registers to create VF devices under the PF PCI device and also bind driver if available. This function needs to be invoked from Physical function device driver which expects VF device support, creating minimal impact on existing framework. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
e0024741 |
|
23-Jul-2020 |
Stefan Roese <sr@denx.de> |
pci: pci-uclass: Dynamically allocate the PCI regions Instead of using a fixed length pre-allocated array of regions, this patch moves to dynamically allocating the regions based on the number of available regions plus the necessary regions for DRAM banks. Since MAX_PCI_REGIONS is not needed any more, its removed completely with this patch. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Thierry Reding <treding@nvidia.com> Cc: Marek Vasut <marek.vasut+renesas@gmail.com>
|
#
143eb5b1 |
|
12-May-2020 |
Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
drivers: pci: add api to get dma regions Add api to get dma regions. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
284d062e |
|
09-Sep-2020 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
pci: add a few ARI related defines Add a few defines related to PCI ARI configuration. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
51eeae91 |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add VF BAR map support for Enhanced Allocation Makes dm_pci_map_bar API available to map BAR for Virtual function PCI devices which support Enhanced Allocation. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
b8852dcf |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add support for Single-Root I/O Virtualization SR-IOV - Single Root I/O Virtualization PF - Physical Function VF - Virtual Function If SR-IOV capability is present, use it to initialize Virtual Function PCI device instances. pci_sriov_init function will read SR-IOV registers to create VF devices under the PF PCI device and also bind driver if available. This function needs to be invoked from Physical function device driver which expects VF device support, creating minimal impact on existing framework. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
e0024741 |
|
23-Jul-2020 |
Stefan Roese <sr@denx.de> |
pci: pci-uclass: Dynamically allocate the PCI regions Instead of using a fixed length pre-allocated array of regions, this patch moves to dynamically allocating the regions based on the number of available regions plus the necessary regions for DRAM banks. Since MAX_PCI_REGIONS is not needed any more, its removed completely with this patch. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Thierry Reding <treding@nvidia.com> Cc: Marek Vasut <marek.vasut+renesas@gmail.com>
|
#
143eb5b1 |
|
12-May-2020 |
Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
drivers: pci: add api to get dma regions Add api to get dma regions. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
284d062e |
|
09-Sep-2020 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
pci: add a few ARI related defines Add a few defines related to PCI ARI configuration. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
51eeae91 |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add VF BAR map support for Enhanced Allocation Makes dm_pci_map_bar API available to map BAR for Virtual function PCI devices which support Enhanced Allocation. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
b8852dcf |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add support for Single-Root I/O Virtualization SR-IOV - Single Root I/O Virtualization PF - Physical Function VF - Virtual Function If SR-IOV capability is present, use it to initialize Virtual Function PCI device instances. pci_sriov_init function will read SR-IOV registers to create VF devices under the PF PCI device and also bind driver if available. This function needs to be invoked from Physical function device driver which expects VF device support, creating minimal impact on existing framework. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
e0024741 |
|
23-Jul-2020 |
Stefan Roese <sr@denx.de> |
pci: pci-uclass: Dynamically allocate the PCI regions Instead of using a fixed length pre-allocated array of regions, this patch moves to dynamically allocating the regions based on the number of available regions plus the necessary regions for DRAM banks. Since MAX_PCI_REGIONS is not needed any more, its removed completely with this patch. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Thierry Reding <treding@nvidia.com> Cc: Marek Vasut <marek.vasut+renesas@gmail.com>
|
#
143eb5b1 |
|
12-May-2020 |
Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
drivers: pci: add api to get dma regions Add api to get dma regions. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
284d062e |
|
09-Sep-2020 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
pci: add a few ARI related defines Add a few defines related to PCI ARI configuration. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
51eeae91 |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add VF BAR map support for Enhanced Allocation Makes dm_pci_map_bar API available to map BAR for Virtual function PCI devices which support Enhanced Allocation. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
b8852dcf |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add support for Single-Root I/O Virtualization SR-IOV - Single Root I/O Virtualization PF - Physical Function VF - Virtual Function If SR-IOV capability is present, use it to initialize Virtual Function PCI device instances. pci_sriov_init function will read SR-IOV registers to create VF devices under the PF PCI device and also bind driver if available. This function needs to be invoked from Physical function device driver which expects VF device support, creating minimal impact on existing framework. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
e0024741 |
|
23-Jul-2020 |
Stefan Roese <sr@denx.de> |
pci: pci-uclass: Dynamically allocate the PCI regions Instead of using a fixed length pre-allocated array of regions, this patch moves to dynamically allocating the regions based on the number of available regions plus the necessary regions for DRAM banks. Since MAX_PCI_REGIONS is not needed any more, its removed completely with this patch. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Thierry Reding <treding@nvidia.com> Cc: Marek Vasut <marek.vasut+renesas@gmail.com>
|
#
143eb5b1 |
|
12-May-2020 |
Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
drivers: pci: add api to get dma regions Add api to get dma regions. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
284d062e |
|
09-Sep-2020 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
pci: add a few ARI related defines Add a few defines related to PCI ARI configuration. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
51eeae91 |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add VF BAR map support for Enhanced Allocation Makes dm_pci_map_bar API available to map BAR for Virtual function PCI devices which support Enhanced Allocation. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
b8852dcf |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add support for Single-Root I/O Virtualization SR-IOV - Single Root I/O Virtualization PF - Physical Function VF - Virtual Function If SR-IOV capability is present, use it to initialize Virtual Function PCI device instances. pci_sriov_init function will read SR-IOV registers to create VF devices under the PF PCI device and also bind driver if available. This function needs to be invoked from Physical function device driver which expects VF device support, creating minimal impact on existing framework. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
e0024741 |
|
23-Jul-2020 |
Stefan Roese <sr@denx.de> |
pci: pci-uclass: Dynamically allocate the PCI regions Instead of using a fixed length pre-allocated array of regions, this patch moves to dynamically allocating the regions based on the number of available regions plus the necessary regions for DRAM banks. Since MAX_PCI_REGIONS is not needed any more, its removed completely with this patch. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Thierry Reding <treding@nvidia.com> Cc: Marek Vasut <marek.vasut+renesas@gmail.com>
|
#
143eb5b1 |
|
12-May-2020 |
Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
drivers: pci: add api to get dma regions Add api to get dma regions. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
284d062e |
|
09-Sep-2020 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
pci: add a few ARI related defines Add a few defines related to PCI ARI configuration. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
51eeae91 |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add VF BAR map support for Enhanced Allocation Makes dm_pci_map_bar API available to map BAR for Virtual function PCI devices which support Enhanced Allocation. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
b8852dcf |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add support for Single-Root I/O Virtualization SR-IOV - Single Root I/O Virtualization PF - Physical Function VF - Virtual Function If SR-IOV capability is present, use it to initialize Virtual Function PCI device instances. pci_sriov_init function will read SR-IOV registers to create VF devices under the PF PCI device and also bind driver if available. This function needs to be invoked from Physical function device driver which expects VF device support, creating minimal impact on existing framework. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
e0024741 |
|
23-Jul-2020 |
Stefan Roese <sr@denx.de> |
pci: pci-uclass: Dynamically allocate the PCI regions Instead of using a fixed length pre-allocated array of regions, this patch moves to dynamically allocating the regions based on the number of available regions plus the necessary regions for DRAM banks. Since MAX_PCI_REGIONS is not needed any more, its removed completely with this patch. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Thierry Reding <treding@nvidia.com> Cc: Marek Vasut <marek.vasut+renesas@gmail.com>
|
#
143eb5b1 |
|
12-May-2020 |
Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
drivers: pci: add api to get dma regions Add api to get dma regions. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
284d062e |
|
09-Sep-2020 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
pci: add a few ARI related defines Add a few defines related to PCI ARI configuration. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
51eeae91 |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add VF BAR map support for Enhanced Allocation Makes dm_pci_map_bar API available to map BAR for Virtual function PCI devices which support Enhanced Allocation. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
b8852dcf |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add support for Single-Root I/O Virtualization SR-IOV - Single Root I/O Virtualization PF - Physical Function VF - Virtual Function If SR-IOV capability is present, use it to initialize Virtual Function PCI device instances. pci_sriov_init function will read SR-IOV registers to create VF devices under the PF PCI device and also bind driver if available. This function needs to be invoked from Physical function device driver which expects VF device support, creating minimal impact on existing framework. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
e0024741 |
|
23-Jul-2020 |
Stefan Roese <sr@denx.de> |
pci: pci-uclass: Dynamically allocate the PCI regions Instead of using a fixed length pre-allocated array of regions, this patch moves to dynamically allocating the regions based on the number of available regions plus the necessary regions for DRAM banks. Since MAX_PCI_REGIONS is not needed any more, its removed completely with this patch. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Thierry Reding <treding@nvidia.com> Cc: Marek Vasut <marek.vasut+renesas@gmail.com>
|
#
143eb5b1 |
|
12-May-2020 |
Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
drivers: pci: add api to get dma regions Add api to get dma regions. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
284d062e |
|
09-Sep-2020 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
pci: add a few ARI related defines Add a few defines related to PCI ARI configuration. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
51eeae91 |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add VF BAR map support for Enhanced Allocation Makes dm_pci_map_bar API available to map BAR for Virtual function PCI devices which support Enhanced Allocation. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
b8852dcf |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add support for Single-Root I/O Virtualization SR-IOV - Single Root I/O Virtualization PF - Physical Function VF - Virtual Function If SR-IOV capability is present, use it to initialize Virtual Function PCI device instances. pci_sriov_init function will read SR-IOV registers to create VF devices under the PF PCI device and also bind driver if available. This function needs to be invoked from Physical function device driver which expects VF device support, creating minimal impact on existing framework. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
e0024741 |
|
23-Jul-2020 |
Stefan Roese <sr@denx.de> |
pci: pci-uclass: Dynamically allocate the PCI regions Instead of using a fixed length pre-allocated array of regions, this patch moves to dynamically allocating the regions based on the number of available regions plus the necessary regions for DRAM banks. Since MAX_PCI_REGIONS is not needed any more, its removed completely with this patch. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Thierry Reding <treding@nvidia.com> Cc: Marek Vasut <marek.vasut+renesas@gmail.com>
|
#
143eb5b1 |
|
12-May-2020 |
Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
drivers: pci: add api to get dma regions Add api to get dma regions. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
284d062e |
|
09-Sep-2020 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
pci: add a few ARI related defines Add a few defines related to PCI ARI configuration. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
51eeae91 |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add VF BAR map support for Enhanced Allocation Makes dm_pci_map_bar API available to map BAR for Virtual function PCI devices which support Enhanced Allocation. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
b8852dcf |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add support for Single-Root I/O Virtualization SR-IOV - Single Root I/O Virtualization PF - Physical Function VF - Virtual Function If SR-IOV capability is present, use it to initialize Virtual Function PCI device instances. pci_sriov_init function will read SR-IOV registers to create VF devices under the PF PCI device and also bind driver if available. This function needs to be invoked from Physical function device driver which expects VF device support, creating minimal impact on existing framework. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
e0024741 |
|
23-Jul-2020 |
Stefan Roese <sr@denx.de> |
pci: pci-uclass: Dynamically allocate the PCI regions Instead of using a fixed length pre-allocated array of regions, this patch moves to dynamically allocating the regions based on the number of available regions plus the necessary regions for DRAM banks. Since MAX_PCI_REGIONS is not needed any more, its removed completely with this patch. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Thierry Reding <treding@nvidia.com> Cc: Marek Vasut <marek.vasut+renesas@gmail.com>
|
#
143eb5b1 |
|
12-May-2020 |
Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
drivers: pci: add api to get dma regions Add api to get dma regions. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
284d062e |
|
09-Sep-2020 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
pci: add a few ARI related defines Add a few defines related to PCI ARI configuration. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
51eeae91 |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add VF BAR map support for Enhanced Allocation Makes dm_pci_map_bar API available to map BAR for Virtual function PCI devices which support Enhanced Allocation. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
b8852dcf |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add support for Single-Root I/O Virtualization SR-IOV - Single Root I/O Virtualization PF - Physical Function VF - Virtual Function If SR-IOV capability is present, use it to initialize Virtual Function PCI device instances. pci_sriov_init function will read SR-IOV registers to create VF devices under the PF PCI device and also bind driver if available. This function needs to be invoked from Physical function device driver which expects VF device support, creating minimal impact on existing framework. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
e0024741 |
|
23-Jul-2020 |
Stefan Roese <sr@denx.de> |
pci: pci-uclass: Dynamically allocate the PCI regions Instead of using a fixed length pre-allocated array of regions, this patch moves to dynamically allocating the regions based on the number of available regions plus the necessary regions for DRAM banks. Since MAX_PCI_REGIONS is not needed any more, its removed completely with this patch. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Thierry Reding <treding@nvidia.com> Cc: Marek Vasut <marek.vasut+renesas@gmail.com>
|
#
143eb5b1 |
|
12-May-2020 |
Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
drivers: pci: add api to get dma regions Add api to get dma regions. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
284d062e |
|
09-Sep-2020 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
pci: add a few ARI related defines Add a few defines related to PCI ARI configuration. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
51eeae91 |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add VF BAR map support for Enhanced Allocation Makes dm_pci_map_bar API available to map BAR for Virtual function PCI devices which support Enhanced Allocation. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
b8852dcf |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add support for Single-Root I/O Virtualization SR-IOV - Single Root I/O Virtualization PF - Physical Function VF - Virtual Function If SR-IOV capability is present, use it to initialize Virtual Function PCI device instances. pci_sriov_init function will read SR-IOV registers to create VF devices under the PF PCI device and also bind driver if available. This function needs to be invoked from Physical function device driver which expects VF device support, creating minimal impact on existing framework. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
e0024741 |
|
23-Jul-2020 |
Stefan Roese <sr@denx.de> |
pci: pci-uclass: Dynamically allocate the PCI regions Instead of using a fixed length pre-allocated array of regions, this patch moves to dynamically allocating the regions based on the number of available regions plus the necessary regions for DRAM banks. Since MAX_PCI_REGIONS is not needed any more, its removed completely with this patch. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Thierry Reding <treding@nvidia.com> Cc: Marek Vasut <marek.vasut+renesas@gmail.com>
|
#
143eb5b1 |
|
12-May-2020 |
Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
drivers: pci: add api to get dma regions Add api to get dma regions. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
284d062e |
|
09-Sep-2020 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
pci: add a few ARI related defines Add a few defines related to PCI ARI configuration. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
51eeae91 |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add VF BAR map support for Enhanced Allocation Makes dm_pci_map_bar API available to map BAR for Virtual function PCI devices which support Enhanced Allocation. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
b8852dcf |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add support for Single-Root I/O Virtualization SR-IOV - Single Root I/O Virtualization PF - Physical Function VF - Virtual Function If SR-IOV capability is present, use it to initialize Virtual Function PCI device instances. pci_sriov_init function will read SR-IOV registers to create VF devices under the PF PCI device and also bind driver if available. This function needs to be invoked from Physical function device driver which expects VF device support, creating minimal impact on existing framework. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
e0024741 |
|
23-Jul-2020 |
Stefan Roese <sr@denx.de> |
pci: pci-uclass: Dynamically allocate the PCI regions Instead of using a fixed length pre-allocated array of regions, this patch moves to dynamically allocating the regions based on the number of available regions plus the necessary regions for DRAM banks. Since MAX_PCI_REGIONS is not needed any more, its removed completely with this patch. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Thierry Reding <treding@nvidia.com> Cc: Marek Vasut <marek.vasut+renesas@gmail.com>
|
#
143eb5b1 |
|
12-May-2020 |
Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
drivers: pci: add api to get dma regions Add api to get dma regions. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
284d062e |
|
09-Sep-2020 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
pci: add a few ARI related defines Add a few defines related to PCI ARI configuration. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
51eeae91 |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add VF BAR map support for Enhanced Allocation Makes dm_pci_map_bar API available to map BAR for Virtual function PCI devices which support Enhanced Allocation. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
b8852dcf |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add support for Single-Root I/O Virtualization SR-IOV - Single Root I/O Virtualization PF - Physical Function VF - Virtual Function If SR-IOV capability is present, use it to initialize Virtual Function PCI device instances. pci_sriov_init function will read SR-IOV registers to create VF devices under the PF PCI device and also bind driver if available. This function needs to be invoked from Physical function device driver which expects VF device support, creating minimal impact on existing framework. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
e0024741 |
|
23-Jul-2020 |
Stefan Roese <sr@denx.de> |
pci: pci-uclass: Dynamically allocate the PCI regions Instead of using a fixed length pre-allocated array of regions, this patch moves to dynamically allocating the regions based on the number of available regions plus the necessary regions for DRAM banks. Since MAX_PCI_REGIONS is not needed any more, its removed completely with this patch. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Thierry Reding <treding@nvidia.com> Cc: Marek Vasut <marek.vasut+renesas@gmail.com>
|
#
143eb5b1 |
|
12-May-2020 |
Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
drivers: pci: add api to get dma regions Add api to get dma regions. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
284d062e |
|
09-Sep-2020 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
pci: add a few ARI related defines Add a few defines related to PCI ARI configuration. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
51eeae91 |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add VF BAR map support for Enhanced Allocation Makes dm_pci_map_bar API available to map BAR for Virtual function PCI devices which support Enhanced Allocation. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
b8852dcf |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add support for Single-Root I/O Virtualization SR-IOV - Single Root I/O Virtualization PF - Physical Function VF - Virtual Function If SR-IOV capability is present, use it to initialize Virtual Function PCI device instances. pci_sriov_init function will read SR-IOV registers to create VF devices under the PF PCI device and also bind driver if available. This function needs to be invoked from Physical function device driver which expects VF device support, creating minimal impact on existing framework. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
e0024741 |
|
23-Jul-2020 |
Stefan Roese <sr@denx.de> |
pci: pci-uclass: Dynamically allocate the PCI regions Instead of using a fixed length pre-allocated array of regions, this patch moves to dynamically allocating the regions based on the number of available regions plus the necessary regions for DRAM banks. Since MAX_PCI_REGIONS is not needed any more, its removed completely with this patch. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Thierry Reding <treding@nvidia.com> Cc: Marek Vasut <marek.vasut+renesas@gmail.com>
|
#
143eb5b1 |
|
12-May-2020 |
Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
drivers: pci: add api to get dma regions Add api to get dma regions. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
284d062e |
|
09-Sep-2020 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
pci: add a few ARI related defines Add a few defines related to PCI ARI configuration. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
51eeae91 |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add VF BAR map support for Enhanced Allocation Makes dm_pci_map_bar API available to map BAR for Virtual function PCI devices which support Enhanced Allocation. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
b8852dcf |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add support for Single-Root I/O Virtualization SR-IOV - Single Root I/O Virtualization PF - Physical Function VF - Virtual Function If SR-IOV capability is present, use it to initialize Virtual Function PCI device instances. pci_sriov_init function will read SR-IOV registers to create VF devices under the PF PCI device and also bind driver if available. This function needs to be invoked from Physical function device driver which expects VF device support, creating minimal impact on existing framework. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
e0024741 |
|
23-Jul-2020 |
Stefan Roese <sr@denx.de> |
pci: pci-uclass: Dynamically allocate the PCI regions Instead of using a fixed length pre-allocated array of regions, this patch moves to dynamically allocating the regions based on the number of available regions plus the necessary regions for DRAM banks. Since MAX_PCI_REGIONS is not needed any more, its removed completely with this patch. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Thierry Reding <treding@nvidia.com> Cc: Marek Vasut <marek.vasut+renesas@gmail.com>
|
#
143eb5b1 |
|
12-May-2020 |
Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
drivers: pci: add api to get dma regions Add api to get dma regions. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
284d062e |
|
09-Sep-2020 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
pci: add a few ARI related defines Add a few defines related to PCI ARI configuration. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
51eeae91 |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add VF BAR map support for Enhanced Allocation Makes dm_pci_map_bar API available to map BAR for Virtual function PCI devices which support Enhanced Allocation. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
b8852dcf |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add support for Single-Root I/O Virtualization SR-IOV - Single Root I/O Virtualization PF - Physical Function VF - Virtual Function If SR-IOV capability is present, use it to initialize Virtual Function PCI device instances. pci_sriov_init function will read SR-IOV registers to create VF devices under the PF PCI device and also bind driver if available. This function needs to be invoked from Physical function device driver which expects VF device support, creating minimal impact on existing framework. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
e0024741 |
|
23-Jul-2020 |
Stefan Roese <sr@denx.de> |
pci: pci-uclass: Dynamically allocate the PCI regions Instead of using a fixed length pre-allocated array of regions, this patch moves to dynamically allocating the regions based on the number of available regions plus the necessary regions for DRAM banks. Since MAX_PCI_REGIONS is not needed any more, its removed completely with this patch. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Thierry Reding <treding@nvidia.com> Cc: Marek Vasut <marek.vasut+renesas@gmail.com>
|
#
143eb5b1 |
|
12-May-2020 |
Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
drivers: pci: add api to get dma regions Add api to get dma regions. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
284d062e |
|
09-Sep-2020 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
pci: add a few ARI related defines Add a few defines related to PCI ARI configuration. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
51eeae91 |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add VF BAR map support for Enhanced Allocation Makes dm_pci_map_bar API available to map BAR for Virtual function PCI devices which support Enhanced Allocation. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
b8852dcf |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add support for Single-Root I/O Virtualization SR-IOV - Single Root I/O Virtualization PF - Physical Function VF - Virtual Function If SR-IOV capability is present, use it to initialize Virtual Function PCI device instances. pci_sriov_init function will read SR-IOV registers to create VF devices under the PF PCI device and also bind driver if available. This function needs to be invoked from Physical function device driver which expects VF device support, creating minimal impact on existing framework. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
e0024741 |
|
23-Jul-2020 |
Stefan Roese <sr@denx.de> |
pci: pci-uclass: Dynamically allocate the PCI regions Instead of using a fixed length pre-allocated array of regions, this patch moves to dynamically allocating the regions based on the number of available regions plus the necessary regions for DRAM banks. Since MAX_PCI_REGIONS is not needed any more, its removed completely with this patch. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Thierry Reding <treding@nvidia.com> Cc: Marek Vasut <marek.vasut+renesas@gmail.com>
|
#
143eb5b1 |
|
12-May-2020 |
Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
drivers: pci: add api to get dma regions Add api to get dma regions. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
284d062e |
|
09-Sep-2020 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
pci: add a few ARI related defines Add a few defines related to PCI ARI configuration. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
51eeae91 |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add VF BAR map support for Enhanced Allocation Makes dm_pci_map_bar API available to map BAR for Virtual function PCI devices which support Enhanced Allocation. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
b8852dcf |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add support for Single-Root I/O Virtualization SR-IOV - Single Root I/O Virtualization PF - Physical Function VF - Virtual Function If SR-IOV capability is present, use it to initialize Virtual Function PCI device instances. pci_sriov_init function will read SR-IOV registers to create VF devices under the PF PCI device and also bind driver if available. This function needs to be invoked from Physical function device driver which expects VF device support, creating minimal impact on existing framework. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
e0024741 |
|
23-Jul-2020 |
Stefan Roese <sr@denx.de> |
pci: pci-uclass: Dynamically allocate the PCI regions Instead of using a fixed length pre-allocated array of regions, this patch moves to dynamically allocating the regions based on the number of available regions plus the necessary regions for DRAM banks. Since MAX_PCI_REGIONS is not needed any more, its removed completely with this patch. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Thierry Reding <treding@nvidia.com> Cc: Marek Vasut <marek.vasut+renesas@gmail.com>
|
#
143eb5b1 |
|
12-May-2020 |
Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
drivers: pci: add api to get dma regions Add api to get dma regions. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
284d062e |
|
09-Sep-2020 |
Laurentiu Tudor <laurentiu.tudor@nxp.com> |
pci: add a few ARI related defines Add a few defines related to PCI ARI configuration. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
51eeae91 |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add VF BAR map support for Enhanced Allocation Makes dm_pci_map_bar API available to map BAR for Virtual function PCI devices which support Enhanced Allocation. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
b8852dcf |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add support for Single-Root I/O Virtualization SR-IOV - Single Root I/O Virtualization PF - Physical Function VF - Virtual Function If SR-IOV capability is present, use it to initialize Virtual Function PCI device instances. pci_sriov_init function will read SR-IOV registers to create VF devices under the PF PCI device and also bind driver if available. This function needs to be invoked from Physical function device driver which expects VF device support, creating minimal impact on existing framework. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
e0024741 |
|
23-Jul-2020 |
Stefan Roese <sr@denx.de> |
pci: pci-uclass: Dynamically allocate the PCI regions Instead of using a fixed length pre-allocated array of regions, this patch moves to dynamically allocating the regions based on the number of available regions plus the necessary regions for DRAM banks. Since MAX_PCI_REGIONS is not needed any more, its removed completely with this patch. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Thierry Reding <treding@nvidia.com> Cc: Marek Vasut <marek.vasut+renesas@gmail.com>
|
#
143eb5b1 |
|
12-May-2020 |
Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
drivers: pci: add api to get dma regions Add api to get dma regions. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
51eeae91 |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add VF BAR map support for Enhanced Allocation Makes dm_pci_map_bar API available to map BAR for Virtual function PCI devices which support Enhanced Allocation. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
b8852dcf |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add support for Single-Root I/O Virtualization SR-IOV - Single Root I/O Virtualization PF - Physical Function VF - Virtual Function If SR-IOV capability is present, use it to initialize Virtual Function PCI device instances. pci_sriov_init function will read SR-IOV registers to create VF devices under the PF PCI device and also bind driver if available. This function needs to be invoked from Physical function device driver which expects VF device support, creating minimal impact on existing framework. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
e0024741 |
|
23-Jul-2020 |
Stefan Roese <sr@denx.de> |
pci: pci-uclass: Dynamically allocate the PCI regions Instead of using a fixed length pre-allocated array of regions, this patch moves to dynamically allocating the regions based on the number of available regions plus the necessary regions for DRAM banks. Since MAX_PCI_REGIONS is not needed any more, its removed completely with this patch. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Thierry Reding <treding@nvidia.com> Cc: Marek Vasut <marek.vasut+renesas@gmail.com>
|
#
143eb5b1 |
|
12-May-2020 |
Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
drivers: pci: add api to get dma regions Add api to get dma regions. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
51eeae91 |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add VF BAR map support for Enhanced Allocation Makes dm_pci_map_bar API available to map BAR for Virtual function PCI devices which support Enhanced Allocation. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
b8852dcf |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add support for Single-Root I/O Virtualization SR-IOV - Single Root I/O Virtualization PF - Physical Function VF - Virtual Function If SR-IOV capability is present, use it to initialize Virtual Function PCI device instances. pci_sriov_init function will read SR-IOV registers to create VF devices under the PF PCI device and also bind driver if available. This function needs to be invoked from Physical function device driver which expects VF device support, creating minimal impact on existing framework. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
e0024741 |
|
23-Jul-2020 |
Stefan Roese <sr@denx.de> |
pci: pci-uclass: Dynamically allocate the PCI regions Instead of using a fixed length pre-allocated array of regions, this patch moves to dynamically allocating the regions based on the number of available regions plus the necessary regions for DRAM banks. Since MAX_PCI_REGIONS is not needed any more, its removed completely with this patch. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Thierry Reding <treding@nvidia.com> Cc: Marek Vasut <marek.vasut+renesas@gmail.com>
|
#
143eb5b1 |
|
12-May-2020 |
Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
drivers: pci: add api to get dma regions Add api to get dma regions. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
51eeae91 |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add VF BAR map support for Enhanced Allocation Makes dm_pci_map_bar API available to map BAR for Virtual function PCI devices which support Enhanced Allocation. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
b8852dcf |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add support for Single-Root I/O Virtualization SR-IOV - Single Root I/O Virtualization PF - Physical Function VF - Virtual Function If SR-IOV capability is present, use it to initialize Virtual Function PCI device instances. pci_sriov_init function will read SR-IOV registers to create VF devices under the PF PCI device and also bind driver if available. This function needs to be invoked from Physical function device driver which expects VF device support, creating minimal impact on existing framework. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
e0024741 |
|
23-Jul-2020 |
Stefan Roese <sr@denx.de> |
pci: pci-uclass: Dynamically allocate the PCI regions Instead of using a fixed length pre-allocated array of regions, this patch moves to dynamically allocating the regions based on the number of available regions plus the necessary regions for DRAM banks. Since MAX_PCI_REGIONS is not needed any more, its removed completely with this patch. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Thierry Reding <treding@nvidia.com> Cc: Marek Vasut <marek.vasut+renesas@gmail.com>
|
#
143eb5b1 |
|
12-May-2020 |
Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
drivers: pci: add api to get dma regions Add api to get dma regions. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
51eeae91 |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add VF BAR map support for Enhanced Allocation Makes dm_pci_map_bar API available to map BAR for Virtual function PCI devices which support Enhanced Allocation. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
b8852dcf |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add support for Single-Root I/O Virtualization SR-IOV - Single Root I/O Virtualization PF - Physical Function VF - Virtual Function If SR-IOV capability is present, use it to initialize Virtual Function PCI device instances. pci_sriov_init function will read SR-IOV registers to create VF devices under the PF PCI device and also bind driver if available. This function needs to be invoked from Physical function device driver which expects VF device support, creating minimal impact on existing framework. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
e0024741 |
|
23-Jul-2020 |
Stefan Roese <sr@denx.de> |
pci: pci-uclass: Dynamically allocate the PCI regions Instead of using a fixed length pre-allocated array of regions, this patch moves to dynamically allocating the regions based on the number of available regions plus the necessary regions for DRAM banks. Since MAX_PCI_REGIONS is not needed any more, its removed completely with this patch. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Thierry Reding <treding@nvidia.com> Cc: Marek Vasut <marek.vasut+renesas@gmail.com>
|
#
143eb5b1 |
|
12-May-2020 |
Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
drivers: pci: add api to get dma regions Add api to get dma regions. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
51eeae91 |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add VF BAR map support for Enhanced Allocation Makes dm_pci_map_bar API available to map BAR for Virtual function PCI devices which support Enhanced Allocation. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
b8852dcf |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add support for Single-Root I/O Virtualization SR-IOV - Single Root I/O Virtualization PF - Physical Function VF - Virtual Function If SR-IOV capability is present, use it to initialize Virtual Function PCI device instances. pci_sriov_init function will read SR-IOV registers to create VF devices under the PF PCI device and also bind driver if available. This function needs to be invoked from Physical function device driver which expects VF device support, creating minimal impact on existing framework. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
e0024741 |
|
23-Jul-2020 |
Stefan Roese <sr@denx.de> |
pci: pci-uclass: Dynamically allocate the PCI regions Instead of using a fixed length pre-allocated array of regions, this patch moves to dynamically allocating the regions based on the number of available regions plus the necessary regions for DRAM banks. Since MAX_PCI_REGIONS is not needed any more, its removed completely with this patch. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Thierry Reding <treding@nvidia.com> Cc: Marek Vasut <marek.vasut+renesas@gmail.com>
|
#
143eb5b1 |
|
12-May-2020 |
Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
drivers: pci: add api to get dma regions Add api to get dma regions. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
51eeae91 |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add VF BAR map support for Enhanced Allocation Makes dm_pci_map_bar API available to map BAR for Virtual function PCI devices which support Enhanced Allocation. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
b8852dcf |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add support for Single-Root I/O Virtualization SR-IOV - Single Root I/O Virtualization PF - Physical Function VF - Virtual Function If SR-IOV capability is present, use it to initialize Virtual Function PCI device instances. pci_sriov_init function will read SR-IOV registers to create VF devices under the PF PCI device and also bind driver if available. This function needs to be invoked from Physical function device driver which expects VF device support, creating minimal impact on existing framework. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
e0024741 |
|
23-Jul-2020 |
Stefan Roese <sr@denx.de> |
pci: pci-uclass: Dynamically allocate the PCI regions Instead of using a fixed length pre-allocated array of regions, this patch moves to dynamically allocating the regions based on the number of available regions plus the necessary regions for DRAM banks. Since MAX_PCI_REGIONS is not needed any more, its removed completely with this patch. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Thierry Reding <treding@nvidia.com> Cc: Marek Vasut <marek.vasut+renesas@gmail.com>
|
#
143eb5b1 |
|
12-May-2020 |
Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
drivers: pci: add api to get dma regions Add api to get dma regions. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
51eeae91 |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add VF BAR map support for Enhanced Allocation Makes dm_pci_map_bar API available to map BAR for Virtual function PCI devices which support Enhanced Allocation. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
b8852dcf |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add support for Single-Root I/O Virtualization SR-IOV - Single Root I/O Virtualization PF - Physical Function VF - Virtual Function If SR-IOV capability is present, use it to initialize Virtual Function PCI device instances. pci_sriov_init function will read SR-IOV registers to create VF devices under the PF PCI device and also bind driver if available. This function needs to be invoked from Physical function device driver which expects VF device support, creating minimal impact on existing framework. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
e0024741 |
|
23-Jul-2020 |
Stefan Roese <sr@denx.de> |
pci: pci-uclass: Dynamically allocate the PCI regions Instead of using a fixed length pre-allocated array of regions, this patch moves to dynamically allocating the regions based on the number of available regions plus the necessary regions for DRAM banks. Since MAX_PCI_REGIONS is not needed any more, its removed completely with this patch. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Thierry Reding <treding@nvidia.com> Cc: Marek Vasut <marek.vasut+renesas@gmail.com>
|
#
143eb5b1 |
|
12-May-2020 |
Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
drivers: pci: add api to get dma regions Add api to get dma regions. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
51eeae91 |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add VF BAR map support for Enhanced Allocation Makes dm_pci_map_bar API available to map BAR for Virtual function PCI devices which support Enhanced Allocation. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
b8852dcf |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add support for Single-Root I/O Virtualization SR-IOV - Single Root I/O Virtualization PF - Physical Function VF - Virtual Function If SR-IOV capability is present, use it to initialize Virtual Function PCI device instances. pci_sriov_init function will read SR-IOV registers to create VF devices under the PF PCI device and also bind driver if available. This function needs to be invoked from Physical function device driver which expects VF device support, creating minimal impact on existing framework. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
e0024741 |
|
23-Jul-2020 |
Stefan Roese <sr@denx.de> |
pci: pci-uclass: Dynamically allocate the PCI regions Instead of using a fixed length pre-allocated array of regions, this patch moves to dynamically allocating the regions based on the number of available regions plus the necessary regions for DRAM banks. Since MAX_PCI_REGIONS is not needed any more, its removed completely with this patch. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Thierry Reding <treding@nvidia.com> Cc: Marek Vasut <marek.vasut+renesas@gmail.com>
|
#
143eb5b1 |
|
12-May-2020 |
Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
drivers: pci: add api to get dma regions Add api to get dma regions. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
51eeae91 |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add VF BAR map support for Enhanced Allocation Makes dm_pci_map_bar API available to map BAR for Virtual function PCI devices which support Enhanced Allocation. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
b8852dcf |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add support for Single-Root I/O Virtualization SR-IOV - Single Root I/O Virtualization PF - Physical Function VF - Virtual Function If SR-IOV capability is present, use it to initialize Virtual Function PCI device instances. pci_sriov_init function will read SR-IOV registers to create VF devices under the PF PCI device and also bind driver if available. This function needs to be invoked from Physical function device driver which expects VF device support, creating minimal impact on existing framework. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
e0024741 |
|
23-Jul-2020 |
Stefan Roese <sr@denx.de> |
pci: pci-uclass: Dynamically allocate the PCI regions Instead of using a fixed length pre-allocated array of regions, this patch moves to dynamically allocating the regions based on the number of available regions plus the necessary regions for DRAM banks. Since MAX_PCI_REGIONS is not needed any more, its removed completely with this patch. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Thierry Reding <treding@nvidia.com> Cc: Marek Vasut <marek.vasut+renesas@gmail.com>
|
#
143eb5b1 |
|
12-May-2020 |
Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
drivers: pci: add api to get dma regions Add api to get dma regions. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
51eeae91 |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add VF BAR map support for Enhanced Allocation Makes dm_pci_map_bar API available to map BAR for Virtual function PCI devices which support Enhanced Allocation. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
b8852dcf |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add support for Single-Root I/O Virtualization SR-IOV - Single Root I/O Virtualization PF - Physical Function VF - Virtual Function If SR-IOV capability is present, use it to initialize Virtual Function PCI device instances. pci_sriov_init function will read SR-IOV registers to create VF devices under the PF PCI device and also bind driver if available. This function needs to be invoked from Physical function device driver which expects VF device support, creating minimal impact on existing framework. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
e0024741 |
|
23-Jul-2020 |
Stefan Roese <sr@denx.de> |
pci: pci-uclass: Dynamically allocate the PCI regions Instead of using a fixed length pre-allocated array of regions, this patch moves to dynamically allocating the regions based on the number of available regions plus the necessary regions for DRAM banks. Since MAX_PCI_REGIONS is not needed any more, its removed completely with this patch. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Thierry Reding <treding@nvidia.com> Cc: Marek Vasut <marek.vasut+renesas@gmail.com>
|
#
143eb5b1 |
|
12-May-2020 |
Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
drivers: pci: add api to get dma regions Add api to get dma regions. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
51eeae91 |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add VF BAR map support for Enhanced Allocation Makes dm_pci_map_bar API available to map BAR for Virtual function PCI devices which support Enhanced Allocation. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
b8852dcf |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add support for Single-Root I/O Virtualization SR-IOV - Single Root I/O Virtualization PF - Physical Function VF - Virtual Function If SR-IOV capability is present, use it to initialize Virtual Function PCI device instances. pci_sriov_init function will read SR-IOV registers to create VF devices under the PF PCI device and also bind driver if available. This function needs to be invoked from Physical function device driver which expects VF device support, creating minimal impact on existing framework. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
e0024741 |
|
23-Jul-2020 |
Stefan Roese <sr@denx.de> |
pci: pci-uclass: Dynamically allocate the PCI regions Instead of using a fixed length pre-allocated array of regions, this patch moves to dynamically allocating the regions based on the number of available regions plus the necessary regions for DRAM banks. Since MAX_PCI_REGIONS is not needed any more, its removed completely with this patch. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Thierry Reding <treding@nvidia.com> Cc: Marek Vasut <marek.vasut+renesas@gmail.com>
|
#
143eb5b1 |
|
12-May-2020 |
Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
drivers: pci: add api to get dma regions Add api to get dma regions. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
51eeae91 |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add VF BAR map support for Enhanced Allocation Makes dm_pci_map_bar API available to map BAR for Virtual function PCI devices which support Enhanced Allocation. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
b8852dcf |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add support for Single-Root I/O Virtualization SR-IOV - Single Root I/O Virtualization PF - Physical Function VF - Virtual Function If SR-IOV capability is present, use it to initialize Virtual Function PCI device instances. pci_sriov_init function will read SR-IOV registers to create VF devices under the PF PCI device and also bind driver if available. This function needs to be invoked from Physical function device driver which expects VF device support, creating minimal impact on existing framework. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
e0024741 |
|
23-Jul-2020 |
Stefan Roese <sr@denx.de> |
pci: pci-uclass: Dynamically allocate the PCI regions Instead of using a fixed length pre-allocated array of regions, this patch moves to dynamically allocating the regions based on the number of available regions plus the necessary regions for DRAM banks. Since MAX_PCI_REGIONS is not needed any more, its removed completely with this patch. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Thierry Reding <treding@nvidia.com> Cc: Marek Vasut <marek.vasut+renesas@gmail.com>
|
#
143eb5b1 |
|
12-May-2020 |
Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
drivers: pci: add api to get dma regions Add api to get dma regions. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
51eeae91 |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add VF BAR map support for Enhanced Allocation Makes dm_pci_map_bar API available to map BAR for Virtual function PCI devices which support Enhanced Allocation. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
b8852dcf |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add support for Single-Root I/O Virtualization SR-IOV - Single Root I/O Virtualization PF - Physical Function VF - Virtual Function If SR-IOV capability is present, use it to initialize Virtual Function PCI device instances. pci_sriov_init function will read SR-IOV registers to create VF devices under the PF PCI device and also bind driver if available. This function needs to be invoked from Physical function device driver which expects VF device support, creating minimal impact on existing framework. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
e0024741 |
|
23-Jul-2020 |
Stefan Roese <sr@denx.de> |
pci: pci-uclass: Dynamically allocate the PCI regions Instead of using a fixed length pre-allocated array of regions, this patch moves to dynamically allocating the regions based on the number of available regions plus the necessary regions for DRAM banks. Since MAX_PCI_REGIONS is not needed any more, its removed completely with this patch. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Thierry Reding <treding@nvidia.com> Cc: Marek Vasut <marek.vasut+renesas@gmail.com>
|
#
143eb5b1 |
|
12-May-2020 |
Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
drivers: pci: add api to get dma regions Add api to get dma regions. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
51eeae91 |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add VF BAR map support for Enhanced Allocation Makes dm_pci_map_bar API available to map BAR for Virtual function PCI devices which support Enhanced Allocation. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
b8852dcf |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add support for Single-Root I/O Virtualization SR-IOV - Single Root I/O Virtualization PF - Physical Function VF - Virtual Function If SR-IOV capability is present, use it to initialize Virtual Function PCI device instances. pci_sriov_init function will read SR-IOV registers to create VF devices under the PF PCI device and also bind driver if available. This function needs to be invoked from Physical function device driver which expects VF device support, creating minimal impact on existing framework. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
e0024741 |
|
23-Jul-2020 |
Stefan Roese <sr@denx.de> |
pci: pci-uclass: Dynamically allocate the PCI regions Instead of using a fixed length pre-allocated array of regions, this patch moves to dynamically allocating the regions based on the number of available regions plus the necessary regions for DRAM banks. Since MAX_PCI_REGIONS is not needed any more, its removed completely with this patch. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Thierry Reding <treding@nvidia.com> Cc: Marek Vasut <marek.vasut+renesas@gmail.com>
|
#
143eb5b1 |
|
12-May-2020 |
Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
drivers: pci: add api to get dma regions Add api to get dma regions. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
51eeae91 |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add VF BAR map support for Enhanced Allocation Makes dm_pci_map_bar API available to map BAR for Virtual function PCI devices which support Enhanced Allocation. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
b8852dcf |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add support for Single-Root I/O Virtualization SR-IOV - Single Root I/O Virtualization PF - Physical Function VF - Virtual Function If SR-IOV capability is present, use it to initialize Virtual Function PCI device instances. pci_sriov_init function will read SR-IOV registers to create VF devices under the PF PCI device and also bind driver if available. This function needs to be invoked from Physical function device driver which expects VF device support, creating minimal impact on existing framework. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
e0024741 |
|
23-Jul-2020 |
Stefan Roese <sr@denx.de> |
pci: pci-uclass: Dynamically allocate the PCI regions Instead of using a fixed length pre-allocated array of regions, this patch moves to dynamically allocating the regions based on the number of available regions plus the necessary regions for DRAM banks. Since MAX_PCI_REGIONS is not needed any more, its removed completely with this patch. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Thierry Reding <treding@nvidia.com> Cc: Marek Vasut <marek.vasut+renesas@gmail.com>
|
#
143eb5b1 |
|
12-May-2020 |
Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
drivers: pci: add api to get dma regions Add api to get dma regions. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
51eeae91 |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add VF BAR map support for Enhanced Allocation Makes dm_pci_map_bar API available to map BAR for Virtual function PCI devices which support Enhanced Allocation. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
b8852dcf |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add support for Single-Root I/O Virtualization SR-IOV - Single Root I/O Virtualization PF - Physical Function VF - Virtual Function If SR-IOV capability is present, use it to initialize Virtual Function PCI device instances. pci_sriov_init function will read SR-IOV registers to create VF devices under the PF PCI device and also bind driver if available. This function needs to be invoked from Physical function device driver which expects VF device support, creating minimal impact on existing framework. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
e0024741 |
|
23-Jul-2020 |
Stefan Roese <sr@denx.de> |
pci: pci-uclass: Dynamically allocate the PCI regions Instead of using a fixed length pre-allocated array of regions, this patch moves to dynamically allocating the regions based on the number of available regions plus the necessary regions for DRAM banks. Since MAX_PCI_REGIONS is not needed any more, its removed completely with this patch. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Thierry Reding <treding@nvidia.com> Cc: Marek Vasut <marek.vasut+renesas@gmail.com>
|
#
143eb5b1 |
|
12-May-2020 |
Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
drivers: pci: add api to get dma regions Add api to get dma regions. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
51eeae91 |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add VF BAR map support for Enhanced Allocation Makes dm_pci_map_bar API available to map BAR for Virtual function PCI devices which support Enhanced Allocation. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
b8852dcf |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add support for Single-Root I/O Virtualization SR-IOV - Single Root I/O Virtualization PF - Physical Function VF - Virtual Function If SR-IOV capability is present, use it to initialize Virtual Function PCI device instances. pci_sriov_init function will read SR-IOV registers to create VF devices under the PF PCI device and also bind driver if available. This function needs to be invoked from Physical function device driver which expects VF device support, creating minimal impact on existing framework. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
e0024741 |
|
23-Jul-2020 |
Stefan Roese <sr@denx.de> |
pci: pci-uclass: Dynamically allocate the PCI regions Instead of using a fixed length pre-allocated array of regions, this patch moves to dynamically allocating the regions based on the number of available regions plus the necessary regions for DRAM banks. Since MAX_PCI_REGIONS is not needed any more, its removed completely with this patch. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Thierry Reding <treding@nvidia.com> Cc: Marek Vasut <marek.vasut+renesas@gmail.com>
|
#
143eb5b1 |
|
12-May-2020 |
Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
drivers: pci: add api to get dma regions Add api to get dma regions. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
51eeae91 |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add VF BAR map support for Enhanced Allocation Makes dm_pci_map_bar API available to map BAR for Virtual function PCI devices which support Enhanced Allocation. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
b8852dcf |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add support for Single-Root I/O Virtualization SR-IOV - Single Root I/O Virtualization PF - Physical Function VF - Virtual Function If SR-IOV capability is present, use it to initialize Virtual Function PCI device instances. pci_sriov_init function will read SR-IOV registers to create VF devices under the PF PCI device and also bind driver if available. This function needs to be invoked from Physical function device driver which expects VF device support, creating minimal impact on existing framework. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
e0024741 |
|
23-Jul-2020 |
Stefan Roese <sr@denx.de> |
pci: pci-uclass: Dynamically allocate the PCI regions Instead of using a fixed length pre-allocated array of regions, this patch moves to dynamically allocating the regions based on the number of available regions plus the necessary regions for DRAM banks. Since MAX_PCI_REGIONS is not needed any more, its removed completely with this patch. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Thierry Reding <treding@nvidia.com> Cc: Marek Vasut <marek.vasut+renesas@gmail.com>
|
#
143eb5b1 |
|
12-May-2020 |
Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
drivers: pci: add api to get dma regions Add api to get dma regions. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
51eeae91 |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add VF BAR map support for Enhanced Allocation Makes dm_pci_map_bar API available to map BAR for Virtual function PCI devices which support Enhanced Allocation. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
b8852dcf |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add support for Single-Root I/O Virtualization SR-IOV - Single Root I/O Virtualization PF - Physical Function VF - Virtual Function If SR-IOV capability is present, use it to initialize Virtual Function PCI device instances. pci_sriov_init function will read SR-IOV registers to create VF devices under the PF PCI device and also bind driver if available. This function needs to be invoked from Physical function device driver which expects VF device support, creating minimal impact on existing framework. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
e0024741 |
|
23-Jul-2020 |
Stefan Roese <sr@denx.de> |
pci: pci-uclass: Dynamically allocate the PCI regions Instead of using a fixed length pre-allocated array of regions, this patch moves to dynamically allocating the regions based on the number of available regions plus the necessary regions for DRAM banks. Since MAX_PCI_REGIONS is not needed any more, its removed completely with this patch. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Thierry Reding <treding@nvidia.com> Cc: Marek Vasut <marek.vasut+renesas@gmail.com>
|
#
143eb5b1 |
|
12-May-2020 |
Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
drivers: pci: add api to get dma regions Add api to get dma regions. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
51eeae91 |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add VF BAR map support for Enhanced Allocation Makes dm_pci_map_bar API available to map BAR for Virtual function PCI devices which support Enhanced Allocation. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
b8852dcf |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add support for Single-Root I/O Virtualization SR-IOV - Single Root I/O Virtualization PF - Physical Function VF - Virtual Function If SR-IOV capability is present, use it to initialize Virtual Function PCI device instances. pci_sriov_init function will read SR-IOV registers to create VF devices under the PF PCI device and also bind driver if available. This function needs to be invoked from Physical function device driver which expects VF device support, creating minimal impact on existing framework. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
e0024741 |
|
23-Jul-2020 |
Stefan Roese <sr@denx.de> |
pci: pci-uclass: Dynamically allocate the PCI regions Instead of using a fixed length pre-allocated array of regions, this patch moves to dynamically allocating the regions based on the number of available regions plus the necessary regions for DRAM banks. Since MAX_PCI_REGIONS is not needed any more, its removed completely with this patch. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Thierry Reding <treding@nvidia.com> Cc: Marek Vasut <marek.vasut+renesas@gmail.com>
|
#
143eb5b1 |
|
12-May-2020 |
Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
drivers: pci: add api to get dma regions Add api to get dma regions. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
51eeae91 |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add VF BAR map support for Enhanced Allocation Makes dm_pci_map_bar API available to map BAR for Virtual function PCI devices which support Enhanced Allocation. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
b8852dcf |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add support for Single-Root I/O Virtualization SR-IOV - Single Root I/O Virtualization PF - Physical Function VF - Virtual Function If SR-IOV capability is present, use it to initialize Virtual Function PCI device instances. pci_sriov_init function will read SR-IOV registers to create VF devices under the PF PCI device and also bind driver if available. This function needs to be invoked from Physical function device driver which expects VF device support, creating minimal impact on existing framework. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
e0024741 |
|
23-Jul-2020 |
Stefan Roese <sr@denx.de> |
pci: pci-uclass: Dynamically allocate the PCI regions Instead of using a fixed length pre-allocated array of regions, this patch moves to dynamically allocating the regions based on the number of available regions plus the necessary regions for DRAM banks. Since MAX_PCI_REGIONS is not needed any more, its removed completely with this patch. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Thierry Reding <treding@nvidia.com> Cc: Marek Vasut <marek.vasut+renesas@gmail.com>
|
#
143eb5b1 |
|
12-May-2020 |
Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
drivers: pci: add api to get dma regions Add api to get dma regions. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
51eeae91 |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add VF BAR map support for Enhanced Allocation Makes dm_pci_map_bar API available to map BAR for Virtual function PCI devices which support Enhanced Allocation. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
b8852dcf |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add support for Single-Root I/O Virtualization SR-IOV - Single Root I/O Virtualization PF - Physical Function VF - Virtual Function If SR-IOV capability is present, use it to initialize Virtual Function PCI device instances. pci_sriov_init function will read SR-IOV registers to create VF devices under the PF PCI device and also bind driver if available. This function needs to be invoked from Physical function device driver which expects VF device support, creating minimal impact on existing framework. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
e0024741 |
|
23-Jul-2020 |
Stefan Roese <sr@denx.de> |
pci: pci-uclass: Dynamically allocate the PCI regions Instead of using a fixed length pre-allocated array of regions, this patch moves to dynamically allocating the regions based on the number of available regions plus the necessary regions for DRAM banks. Since MAX_PCI_REGIONS is not needed any more, its removed completely with this patch. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Thierry Reding <treding@nvidia.com> Cc: Marek Vasut <marek.vasut+renesas@gmail.com>
|
#
143eb5b1 |
|
12-May-2020 |
Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
drivers: pci: add api to get dma regions Add api to get dma regions. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
51eeae91 |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add VF BAR map support for Enhanced Allocation Makes dm_pci_map_bar API available to map BAR for Virtual function PCI devices which support Enhanced Allocation. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
b8852dcf |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add support for Single-Root I/O Virtualization SR-IOV - Single Root I/O Virtualization PF - Physical Function VF - Virtual Function If SR-IOV capability is present, use it to initialize Virtual Function PCI device instances. pci_sriov_init function will read SR-IOV registers to create VF devices under the PF PCI device and also bind driver if available. This function needs to be invoked from Physical function device driver which expects VF device support, creating minimal impact on existing framework. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
e0024741 |
|
23-Jul-2020 |
Stefan Roese <sr@denx.de> |
pci: pci-uclass: Dynamically allocate the PCI regions Instead of using a fixed length pre-allocated array of regions, this patch moves to dynamically allocating the regions based on the number of available regions plus the necessary regions for DRAM banks. Since MAX_PCI_REGIONS is not needed any more, its removed completely with this patch. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Thierry Reding <treding@nvidia.com> Cc: Marek Vasut <marek.vasut+renesas@gmail.com>
|
#
143eb5b1 |
|
12-May-2020 |
Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
drivers: pci: add api to get dma regions Add api to get dma regions. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
51eeae91 |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add VF BAR map support for Enhanced Allocation Makes dm_pci_map_bar API available to map BAR for Virtual function PCI devices which support Enhanced Allocation. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
b8852dcf |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add support for Single-Root I/O Virtualization SR-IOV - Single Root I/O Virtualization PF - Physical Function VF - Virtual Function If SR-IOV capability is present, use it to initialize Virtual Function PCI device instances. pci_sriov_init function will read SR-IOV registers to create VF devices under the PF PCI device and also bind driver if available. This function needs to be invoked from Physical function device driver which expects VF device support, creating minimal impact on existing framework. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
e0024741 |
|
23-Jul-2020 |
Stefan Roese <sr@denx.de> |
pci: pci-uclass: Dynamically allocate the PCI regions Instead of using a fixed length pre-allocated array of regions, this patch moves to dynamically allocating the regions based on the number of available regions plus the necessary regions for DRAM banks. Since MAX_PCI_REGIONS is not needed any more, its removed completely with this patch. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Thierry Reding <treding@nvidia.com> Cc: Marek Vasut <marek.vasut+renesas@gmail.com>
|
#
143eb5b1 |
|
12-May-2020 |
Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
drivers: pci: add api to get dma regions Add api to get dma regions. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
51eeae91 |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add VF BAR map support for Enhanced Allocation Makes dm_pci_map_bar API available to map BAR for Virtual function PCI devices which support Enhanced Allocation. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
b8852dcf |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add support for Single-Root I/O Virtualization SR-IOV - Single Root I/O Virtualization PF - Physical Function VF - Virtual Function If SR-IOV capability is present, use it to initialize Virtual Function PCI device instances. pci_sriov_init function will read SR-IOV registers to create VF devices under the PF PCI device and also bind driver if available. This function needs to be invoked from Physical function device driver which expects VF device support, creating minimal impact on existing framework. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
e0024741 |
|
23-Jul-2020 |
Stefan Roese <sr@denx.de> |
pci: pci-uclass: Dynamically allocate the PCI regions Instead of using a fixed length pre-allocated array of regions, this patch moves to dynamically allocating the regions based on the number of available regions plus the necessary regions for DRAM banks. Since MAX_PCI_REGIONS is not needed any more, its removed completely with this patch. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Thierry Reding <treding@nvidia.com> Cc: Marek Vasut <marek.vasut+renesas@gmail.com>
|
#
143eb5b1 |
|
12-May-2020 |
Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
drivers: pci: add api to get dma regions Add api to get dma regions. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
51eeae91 |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add VF BAR map support for Enhanced Allocation Makes dm_pci_map_bar API available to map BAR for Virtual function PCI devices which support Enhanced Allocation. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
b8852dcf |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add support for Single-Root I/O Virtualization SR-IOV - Single Root I/O Virtualization PF - Physical Function VF - Virtual Function If SR-IOV capability is present, use it to initialize Virtual Function PCI device instances. pci_sriov_init function will read SR-IOV registers to create VF devices under the PF PCI device and also bind driver if available. This function needs to be invoked from Physical function device driver which expects VF device support, creating minimal impact on existing framework. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
e0024741 |
|
23-Jul-2020 |
Stefan Roese <sr@denx.de> |
pci: pci-uclass: Dynamically allocate the PCI regions Instead of using a fixed length pre-allocated array of regions, this patch moves to dynamically allocating the regions based on the number of available regions plus the necessary regions for DRAM banks. Since MAX_PCI_REGIONS is not needed any more, its removed completely with this patch. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Thierry Reding <treding@nvidia.com> Cc: Marek Vasut <marek.vasut+renesas@gmail.com>
|
#
143eb5b1 |
|
12-May-2020 |
Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
drivers: pci: add api to get dma regions Add api to get dma regions. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
51eeae91 |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add VF BAR map support for Enhanced Allocation Makes dm_pci_map_bar API available to map BAR for Virtual function PCI devices which support Enhanced Allocation. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
b8852dcf |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add support for Single-Root I/O Virtualization SR-IOV - Single Root I/O Virtualization PF - Physical Function VF - Virtual Function If SR-IOV capability is present, use it to initialize Virtual Function PCI device instances. pci_sriov_init function will read SR-IOV registers to create VF devices under the PF PCI device and also bind driver if available. This function needs to be invoked from Physical function device driver which expects VF device support, creating minimal impact on existing framework. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
e0024741 |
|
23-Jul-2020 |
Stefan Roese <sr@denx.de> |
pci: pci-uclass: Dynamically allocate the PCI regions Instead of using a fixed length pre-allocated array of regions, this patch moves to dynamically allocating the regions based on the number of available regions plus the necessary regions for DRAM banks. Since MAX_PCI_REGIONS is not needed any more, its removed completely with this patch. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Thierry Reding <treding@nvidia.com> Cc: Marek Vasut <marek.vasut+renesas@gmail.com>
|
#
143eb5b1 |
|
12-May-2020 |
Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
drivers: pci: add api to get dma regions Add api to get dma regions. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
51eeae91 |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add VF BAR map support for Enhanced Allocation Makes dm_pci_map_bar API available to map BAR for Virtual function PCI devices which support Enhanced Allocation. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
b8852dcf |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add support for Single-Root I/O Virtualization SR-IOV - Single Root I/O Virtualization PF - Physical Function VF - Virtual Function If SR-IOV capability is present, use it to initialize Virtual Function PCI device instances. pci_sriov_init function will read SR-IOV registers to create VF devices under the PF PCI device and also bind driver if available. This function needs to be invoked from Physical function device driver which expects VF device support, creating minimal impact on existing framework. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
e0024741 |
|
23-Jul-2020 |
Stefan Roese <sr@denx.de> |
pci: pci-uclass: Dynamically allocate the PCI regions Instead of using a fixed length pre-allocated array of regions, this patch moves to dynamically allocating the regions based on the number of available regions plus the necessary regions for DRAM banks. Since MAX_PCI_REGIONS is not needed any more, its removed completely with this patch. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Thierry Reding <treding@nvidia.com> Cc: Marek Vasut <marek.vasut+renesas@gmail.com>
|
#
143eb5b1 |
|
12-May-2020 |
Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
drivers: pci: add api to get dma regions Add api to get dma regions. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
51eeae91 |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add VF BAR map support for Enhanced Allocation Makes dm_pci_map_bar API available to map BAR for Virtual function PCI devices which support Enhanced Allocation. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
b8852dcf |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add support for Single-Root I/O Virtualization SR-IOV - Single Root I/O Virtualization PF - Physical Function VF - Virtual Function If SR-IOV capability is present, use it to initialize Virtual Function PCI device instances. pci_sriov_init function will read SR-IOV registers to create VF devices under the PF PCI device and also bind driver if available. This function needs to be invoked from Physical function device driver which expects VF device support, creating minimal impact on existing framework. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
e0024741 |
|
23-Jul-2020 |
Stefan Roese <sr@denx.de> |
pci: pci-uclass: Dynamically allocate the PCI regions Instead of using a fixed length pre-allocated array of regions, this patch moves to dynamically allocating the regions based on the number of available regions plus the necessary regions for DRAM banks. Since MAX_PCI_REGIONS is not needed any more, its removed completely with this patch. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Thierry Reding <treding@nvidia.com> Cc: Marek Vasut <marek.vasut+renesas@gmail.com>
|
#
143eb5b1 |
|
12-May-2020 |
Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
drivers: pci: add api to get dma regions Add api to get dma regions. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
51eeae91 |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add VF BAR map support for Enhanced Allocation Makes dm_pci_map_bar API available to map BAR for Virtual function PCI devices which support Enhanced Allocation. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
b8852dcf |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add support for Single-Root I/O Virtualization SR-IOV - Single Root I/O Virtualization PF - Physical Function VF - Virtual Function If SR-IOV capability is present, use it to initialize Virtual Function PCI device instances. pci_sriov_init function will read SR-IOV registers to create VF devices under the PF PCI device and also bind driver if available. This function needs to be invoked from Physical function device driver which expects VF device support, creating minimal impact on existing framework. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
e0024741 |
|
23-Jul-2020 |
Stefan Roese <sr@denx.de> |
pci: pci-uclass: Dynamically allocate the PCI regions Instead of using a fixed length pre-allocated array of regions, this patch moves to dynamically allocating the regions based on the number of available regions plus the necessary regions for DRAM banks. Since MAX_PCI_REGIONS is not needed any more, its removed completely with this patch. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Thierry Reding <treding@nvidia.com> Cc: Marek Vasut <marek.vasut+renesas@gmail.com>
|
#
143eb5b1 |
|
12-May-2020 |
Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
drivers: pci: add api to get dma regions Add api to get dma regions. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
51eeae91 |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add VF BAR map support for Enhanced Allocation Makes dm_pci_map_bar API available to map BAR for Virtual function PCI devices which support Enhanced Allocation. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
b8852dcf |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add support for Single-Root I/O Virtualization SR-IOV - Single Root I/O Virtualization PF - Physical Function VF - Virtual Function If SR-IOV capability is present, use it to initialize Virtual Function PCI device instances. pci_sriov_init function will read SR-IOV registers to create VF devices under the PF PCI device and also bind driver if available. This function needs to be invoked from Physical function device driver which expects VF device support, creating minimal impact on existing framework. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
e0024741 |
|
23-Jul-2020 |
Stefan Roese <sr@denx.de> |
pci: pci-uclass: Dynamically allocate the PCI regions Instead of using a fixed length pre-allocated array of regions, this patch moves to dynamically allocating the regions based on the number of available regions plus the necessary regions for DRAM banks. Since MAX_PCI_REGIONS is not needed any more, its removed completely with this patch. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Thierry Reding <treding@nvidia.com> Cc: Marek Vasut <marek.vasut+renesas@gmail.com>
|
#
143eb5b1 |
|
12-May-2020 |
Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
drivers: pci: add api to get dma regions Add api to get dma regions. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
51eeae91 |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add VF BAR map support for Enhanced Allocation Makes dm_pci_map_bar API available to map BAR for Virtual function PCI devices which support Enhanced Allocation. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
b8852dcf |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add support for Single-Root I/O Virtualization SR-IOV - Single Root I/O Virtualization PF - Physical Function VF - Virtual Function If SR-IOV capability is present, use it to initialize Virtual Function PCI device instances. pci_sriov_init function will read SR-IOV registers to create VF devices under the PF PCI device and also bind driver if available. This function needs to be invoked from Physical function device driver which expects VF device support, creating minimal impact on existing framework. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
e0024741 |
|
23-Jul-2020 |
Stefan Roese <sr@denx.de> |
pci: pci-uclass: Dynamically allocate the PCI regions Instead of using a fixed length pre-allocated array of regions, this patch moves to dynamically allocating the regions based on the number of available regions plus the necessary regions for DRAM banks. Since MAX_PCI_REGIONS is not needed any more, its removed completely with this patch. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Thierry Reding <treding@nvidia.com> Cc: Marek Vasut <marek.vasut+renesas@gmail.com>
|
#
143eb5b1 |
|
12-May-2020 |
Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
drivers: pci: add api to get dma regions Add api to get dma regions. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
51eeae91 |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add VF BAR map support for Enhanced Allocation Makes dm_pci_map_bar API available to map BAR for Virtual function PCI devices which support Enhanced Allocation. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
b8852dcf |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add support for Single-Root I/O Virtualization SR-IOV - Single Root I/O Virtualization PF - Physical Function VF - Virtual Function If SR-IOV capability is present, use it to initialize Virtual Function PCI device instances. pci_sriov_init function will read SR-IOV registers to create VF devices under the PF PCI device and also bind driver if available. This function needs to be invoked from Physical function device driver which expects VF device support, creating minimal impact on existing framework. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
e0024741 |
|
23-Jul-2020 |
Stefan Roese <sr@denx.de> |
pci: pci-uclass: Dynamically allocate the PCI regions Instead of using a fixed length pre-allocated array of regions, this patch moves to dynamically allocating the regions based on the number of available regions plus the necessary regions for DRAM banks. Since MAX_PCI_REGIONS is not needed any more, its removed completely with this patch. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Thierry Reding <treding@nvidia.com> Cc: Marek Vasut <marek.vasut+renesas@gmail.com>
|
#
143eb5b1 |
|
12-May-2020 |
Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
drivers: pci: add api to get dma regions Add api to get dma regions. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
51eeae91 |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add VF BAR map support for Enhanced Allocation Makes dm_pci_map_bar API available to map BAR for Virtual function PCI devices which support Enhanced Allocation. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
b8852dcf |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add support for Single-Root I/O Virtualization SR-IOV - Single Root I/O Virtualization PF - Physical Function VF - Virtual Function If SR-IOV capability is present, use it to initialize Virtual Function PCI device instances. pci_sriov_init function will read SR-IOV registers to create VF devices under the PF PCI device and also bind driver if available. This function needs to be invoked from Physical function device driver which expects VF device support, creating minimal impact on existing framework. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
e0024741 |
|
23-Jul-2020 |
Stefan Roese <sr@denx.de> |
pci: pci-uclass: Dynamically allocate the PCI regions Instead of using a fixed length pre-allocated array of regions, this patch moves to dynamically allocating the regions based on the number of available regions plus the necessary regions for DRAM banks. Since MAX_PCI_REGIONS is not needed any more, its removed completely with this patch. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Thierry Reding <treding@nvidia.com> Cc: Marek Vasut <marek.vasut+renesas@gmail.com>
|
#
143eb5b1 |
|
12-May-2020 |
Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
drivers: pci: add api to get dma regions Add api to get dma regions. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
51eeae91 |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add VF BAR map support for Enhanced Allocation Makes dm_pci_map_bar API available to map BAR for Virtual function PCI devices which support Enhanced Allocation. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
b8852dcf |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add support for Single-Root I/O Virtualization SR-IOV - Single Root I/O Virtualization PF - Physical Function VF - Virtual Function If SR-IOV capability is present, use it to initialize Virtual Function PCI device instances. pci_sriov_init function will read SR-IOV registers to create VF devices under the PF PCI device and also bind driver if available. This function needs to be invoked from Physical function device driver which expects VF device support, creating minimal impact on existing framework. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
e0024741 |
|
23-Jul-2020 |
Stefan Roese <sr@denx.de> |
pci: pci-uclass: Dynamically allocate the PCI regions Instead of using a fixed length pre-allocated array of regions, this patch moves to dynamically allocating the regions based on the number of available regions plus the necessary regions for DRAM banks. Since MAX_PCI_REGIONS is not needed any more, its removed completely with this patch. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Thierry Reding <treding@nvidia.com> Cc: Marek Vasut <marek.vasut+renesas@gmail.com>
|
#
143eb5b1 |
|
12-May-2020 |
Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
drivers: pci: add api to get dma regions Add api to get dma regions. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
51eeae91 |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add VF BAR map support for Enhanced Allocation Makes dm_pci_map_bar API available to map BAR for Virtual function PCI devices which support Enhanced Allocation. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
b8852dcf |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add support for Single-Root I/O Virtualization SR-IOV - Single Root I/O Virtualization PF - Physical Function VF - Virtual Function If SR-IOV capability is present, use it to initialize Virtual Function PCI device instances. pci_sriov_init function will read SR-IOV registers to create VF devices under the PF PCI device and also bind driver if available. This function needs to be invoked from Physical function device driver which expects VF device support, creating minimal impact on existing framework. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
e0024741 |
|
23-Jul-2020 |
Stefan Roese <sr@denx.de> |
pci: pci-uclass: Dynamically allocate the PCI regions Instead of using a fixed length pre-allocated array of regions, this patch moves to dynamically allocating the regions based on the number of available regions plus the necessary regions for DRAM banks. Since MAX_PCI_REGIONS is not needed any more, its removed completely with this patch. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Thierry Reding <treding@nvidia.com> Cc: Marek Vasut <marek.vasut+renesas@gmail.com>
|
#
143eb5b1 |
|
12-May-2020 |
Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
drivers: pci: add api to get dma regions Add api to get dma regions. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
51eeae91 |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add VF BAR map support for Enhanced Allocation Makes dm_pci_map_bar API available to map BAR for Virtual function PCI devices which support Enhanced Allocation. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
b8852dcf |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add support for Single-Root I/O Virtualization SR-IOV - Single Root I/O Virtualization PF - Physical Function VF - Virtual Function If SR-IOV capability is present, use it to initialize Virtual Function PCI device instances. pci_sriov_init function will read SR-IOV registers to create VF devices under the PF PCI device and also bind driver if available. This function needs to be invoked from Physical function device driver which expects VF device support, creating minimal impact on existing framework. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
e0024741 |
|
23-Jul-2020 |
Stefan Roese <sr@denx.de> |
pci: pci-uclass: Dynamically allocate the PCI regions Instead of using a fixed length pre-allocated array of regions, this patch moves to dynamically allocating the regions based on the number of available regions plus the necessary regions for DRAM banks. Since MAX_PCI_REGIONS is not needed any more, its removed completely with this patch. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Thierry Reding <treding@nvidia.com> Cc: Marek Vasut <marek.vasut+renesas@gmail.com>
|
#
143eb5b1 |
|
12-May-2020 |
Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
drivers: pci: add api to get dma regions Add api to get dma regions. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
51eeae91 |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add VF BAR map support for Enhanced Allocation Makes dm_pci_map_bar API available to map BAR for Virtual function PCI devices which support Enhanced Allocation. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
b8852dcf |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add support for Single-Root I/O Virtualization SR-IOV - Single Root I/O Virtualization PF - Physical Function VF - Virtual Function If SR-IOV capability is present, use it to initialize Virtual Function PCI device instances. pci_sriov_init function will read SR-IOV registers to create VF devices under the PF PCI device and also bind driver if available. This function needs to be invoked from Physical function device driver which expects VF device support, creating minimal impact on existing framework. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
e0024741 |
|
23-Jul-2020 |
Stefan Roese <sr@denx.de> |
pci: pci-uclass: Dynamically allocate the PCI regions Instead of using a fixed length pre-allocated array of regions, this patch moves to dynamically allocating the regions based on the number of available regions plus the necessary regions for DRAM banks. Since MAX_PCI_REGIONS is not needed any more, its removed completely with this patch. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Thierry Reding <treding@nvidia.com> Cc: Marek Vasut <marek.vasut+renesas@gmail.com>
|
#
143eb5b1 |
|
12-May-2020 |
Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
drivers: pci: add api to get dma regions Add api to get dma regions. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
51eeae91 |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add VF BAR map support for Enhanced Allocation Makes dm_pci_map_bar API available to map BAR for Virtual function PCI devices which support Enhanced Allocation. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
b8852dcf |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add support for Single-Root I/O Virtualization SR-IOV - Single Root I/O Virtualization PF - Physical Function VF - Virtual Function If SR-IOV capability is present, use it to initialize Virtual Function PCI device instances. pci_sriov_init function will read SR-IOV registers to create VF devices under the PF PCI device and also bind driver if available. This function needs to be invoked from Physical function device driver which expects VF device support, creating minimal impact on existing framework. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
e0024741 |
|
23-Jul-2020 |
Stefan Roese <sr@denx.de> |
pci: pci-uclass: Dynamically allocate the PCI regions Instead of using a fixed length pre-allocated array of regions, this patch moves to dynamically allocating the regions based on the number of available regions plus the necessary regions for DRAM banks. Since MAX_PCI_REGIONS is not needed any more, its removed completely with this patch. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Thierry Reding <treding@nvidia.com> Cc: Marek Vasut <marek.vasut+renesas@gmail.com>
|
#
143eb5b1 |
|
12-May-2020 |
Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
drivers: pci: add api to get dma regions Add api to get dma regions. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
51eeae91 |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add VF BAR map support for Enhanced Allocation Makes dm_pci_map_bar API available to map BAR for Virtual function PCI devices which support Enhanced Allocation. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
b8852dcf |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add support for Single-Root I/O Virtualization SR-IOV - Single Root I/O Virtualization PF - Physical Function VF - Virtual Function If SR-IOV capability is present, use it to initialize Virtual Function PCI device instances. pci_sriov_init function will read SR-IOV registers to create VF devices under the PF PCI device and also bind driver if available. This function needs to be invoked from Physical function device driver which expects VF device support, creating minimal impact on existing framework. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
e0024741 |
|
23-Jul-2020 |
Stefan Roese <sr@denx.de> |
pci: pci-uclass: Dynamically allocate the PCI regions Instead of using a fixed length pre-allocated array of regions, this patch moves to dynamically allocating the regions based on the number of available regions plus the necessary regions for DRAM banks. Since MAX_PCI_REGIONS is not needed any more, its removed completely with this patch. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Thierry Reding <treding@nvidia.com> Cc: Marek Vasut <marek.vasut+renesas@gmail.com>
|
#
143eb5b1 |
|
12-May-2020 |
Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
drivers: pci: add api to get dma regions Add api to get dma regions. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
51eeae91 |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add VF BAR map support for Enhanced Allocation Makes dm_pci_map_bar API available to map BAR for Virtual function PCI devices which support Enhanced Allocation. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
b8852dcf |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add support for Single-Root I/O Virtualization SR-IOV - Single Root I/O Virtualization PF - Physical Function VF - Virtual Function If SR-IOV capability is present, use it to initialize Virtual Function PCI device instances. pci_sriov_init function will read SR-IOV registers to create VF devices under the PF PCI device and also bind driver if available. This function needs to be invoked from Physical function device driver which expects VF device support, creating minimal impact on existing framework. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
e0024741 |
|
23-Jul-2020 |
Stefan Roese <sr@denx.de> |
pci: pci-uclass: Dynamically allocate the PCI regions Instead of using a fixed length pre-allocated array of regions, this patch moves to dynamically allocating the regions based on the number of available regions plus the necessary regions for DRAM banks. Since MAX_PCI_REGIONS is not needed any more, its removed completely with this patch. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Thierry Reding <treding@nvidia.com> Cc: Marek Vasut <marek.vasut+renesas@gmail.com>
|
#
143eb5b1 |
|
12-May-2020 |
Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
drivers: pci: add api to get dma regions Add api to get dma regions. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
51eeae91 |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add VF BAR map support for Enhanced Allocation Makes dm_pci_map_bar API available to map BAR for Virtual function PCI devices which support Enhanced Allocation. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
b8852dcf |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add support for Single-Root I/O Virtualization SR-IOV - Single Root I/O Virtualization PF - Physical Function VF - Virtual Function If SR-IOV capability is present, use it to initialize Virtual Function PCI device instances. pci_sriov_init function will read SR-IOV registers to create VF devices under the PF PCI device and also bind driver if available. This function needs to be invoked from Physical function device driver which expects VF device support, creating minimal impact on existing framework. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
e0024741 |
|
23-Jul-2020 |
Stefan Roese <sr@denx.de> |
pci: pci-uclass: Dynamically allocate the PCI regions Instead of using a fixed length pre-allocated array of regions, this patch moves to dynamically allocating the regions based on the number of available regions plus the necessary regions for DRAM banks. Since MAX_PCI_REGIONS is not needed any more, its removed completely with this patch. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Thierry Reding <treding@nvidia.com> Cc: Marek Vasut <marek.vasut+renesas@gmail.com>
|
#
143eb5b1 |
|
12-May-2020 |
Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
drivers: pci: add api to get dma regions Add api to get dma regions. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
51eeae91 |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add VF BAR map support for Enhanced Allocation Makes dm_pci_map_bar API available to map BAR for Virtual function PCI devices which support Enhanced Allocation. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
b8852dcf |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add support for Single-Root I/O Virtualization SR-IOV - Single Root I/O Virtualization PF - Physical Function VF - Virtual Function If SR-IOV capability is present, use it to initialize Virtual Function PCI device instances. pci_sriov_init function will read SR-IOV registers to create VF devices under the PF PCI device and also bind driver if available. This function needs to be invoked from Physical function device driver which expects VF device support, creating minimal impact on existing framework. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
e0024741 |
|
23-Jul-2020 |
Stefan Roese <sr@denx.de> |
pci: pci-uclass: Dynamically allocate the PCI regions Instead of using a fixed length pre-allocated array of regions, this patch moves to dynamically allocating the regions based on the number of available regions plus the necessary regions for DRAM banks. Since MAX_PCI_REGIONS is not needed any more, its removed completely with this patch. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Thierry Reding <treding@nvidia.com> Cc: Marek Vasut <marek.vasut+renesas@gmail.com>
|
#
143eb5b1 |
|
12-May-2020 |
Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
drivers: pci: add api to get dma regions Add api to get dma regions. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
51eeae91 |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add VF BAR map support for Enhanced Allocation Makes dm_pci_map_bar API available to map BAR for Virtual function PCI devices which support Enhanced Allocation. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
b8852dcf |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add support for Single-Root I/O Virtualization SR-IOV - Single Root I/O Virtualization PF - Physical Function VF - Virtual Function If SR-IOV capability is present, use it to initialize Virtual Function PCI device instances. pci_sriov_init function will read SR-IOV registers to create VF devices under the PF PCI device and also bind driver if available. This function needs to be invoked from Physical function device driver which expects VF device support, creating minimal impact on existing framework. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
e0024741 |
|
23-Jul-2020 |
Stefan Roese <sr@denx.de> |
pci: pci-uclass: Dynamically allocate the PCI regions Instead of using a fixed length pre-allocated array of regions, this patch moves to dynamically allocating the regions based on the number of available regions plus the necessary regions for DRAM banks. Since MAX_PCI_REGIONS is not needed any more, its removed completely with this patch. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Thierry Reding <treding@nvidia.com> Cc: Marek Vasut <marek.vasut+renesas@gmail.com>
|
#
143eb5b1 |
|
12-May-2020 |
Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
drivers: pci: add api to get dma regions Add api to get dma regions. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
51eeae91 |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add VF BAR map support for Enhanced Allocation Makes dm_pci_map_bar API available to map BAR for Virtual function PCI devices which support Enhanced Allocation. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
b8852dcf |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add support for Single-Root I/O Virtualization SR-IOV - Single Root I/O Virtualization PF - Physical Function VF - Virtual Function If SR-IOV capability is present, use it to initialize Virtual Function PCI device instances. pci_sriov_init function will read SR-IOV registers to create VF devices under the PF PCI device and also bind driver if available. This function needs to be invoked from Physical function device driver which expects VF device support, creating minimal impact on existing framework. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
e0024741 |
|
23-Jul-2020 |
Stefan Roese <sr@denx.de> |
pci: pci-uclass: Dynamically allocate the PCI regions Instead of using a fixed length pre-allocated array of regions, this patch moves to dynamically allocating the regions based on the number of available regions plus the necessary regions for DRAM banks. Since MAX_PCI_REGIONS is not needed any more, its removed completely with this patch. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Thierry Reding <treding@nvidia.com> Cc: Marek Vasut <marek.vasut+renesas@gmail.com>
|
#
143eb5b1 |
|
12-May-2020 |
Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
drivers: pci: add api to get dma regions Add api to get dma regions. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
51eeae91 |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add VF BAR map support for Enhanced Allocation Makes dm_pci_map_bar API available to map BAR for Virtual function PCI devices which support Enhanced Allocation. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
b8852dcf |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add support for Single-Root I/O Virtualization SR-IOV - Single Root I/O Virtualization PF - Physical Function VF - Virtual Function If SR-IOV capability is present, use it to initialize Virtual Function PCI device instances. pci_sriov_init function will read SR-IOV registers to create VF devices under the PF PCI device and also bind driver if available. This function needs to be invoked from Physical function device driver which expects VF device support, creating minimal impact on existing framework. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
e0024741 |
|
23-Jul-2020 |
Stefan Roese <sr@denx.de> |
pci: pci-uclass: Dynamically allocate the PCI regions Instead of using a fixed length pre-allocated array of regions, this patch moves to dynamically allocating the regions based on the number of available regions plus the necessary regions for DRAM banks. Since MAX_PCI_REGIONS is not needed any more, its removed completely with this patch. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Thierry Reding <treding@nvidia.com> Cc: Marek Vasut <marek.vasut+renesas@gmail.com>
|
#
143eb5b1 |
|
12-May-2020 |
Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
drivers: pci: add api to get dma regions Add api to get dma regions. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
51eeae91 |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add VF BAR map support for Enhanced Allocation Makes dm_pci_map_bar API available to map BAR for Virtual function PCI devices which support Enhanced Allocation. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
b8852dcf |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add support for Single-Root I/O Virtualization SR-IOV - Single Root I/O Virtualization PF - Physical Function VF - Virtual Function If SR-IOV capability is present, use it to initialize Virtual Function PCI device instances. pci_sriov_init function will read SR-IOV registers to create VF devices under the PF PCI device and also bind driver if available. This function needs to be invoked from Physical function device driver which expects VF device support, creating minimal impact on existing framework. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
e0024741 |
|
23-Jul-2020 |
Stefan Roese <sr@denx.de> |
pci: pci-uclass: Dynamically allocate the PCI regions Instead of using a fixed length pre-allocated array of regions, this patch moves to dynamically allocating the regions based on the number of available regions plus the necessary regions for DRAM banks. Since MAX_PCI_REGIONS is not needed any more, its removed completely with this patch. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Thierry Reding <treding@nvidia.com> Cc: Marek Vasut <marek.vasut+renesas@gmail.com>
|
#
143eb5b1 |
|
12-May-2020 |
Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
drivers: pci: add api to get dma regions Add api to get dma regions. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
51eeae91 |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add VF BAR map support for Enhanced Allocation Makes dm_pci_map_bar API available to map BAR for Virtual function PCI devices which support Enhanced Allocation. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
b8852dcf |
|
19-Oct-2019 |
Suneel Garapati <sgarapati@marvell.com> |
pci: pci-uclass: Add support for Single-Root I/O Virtualization SR-IOV - Single Root I/O Virtualization PF - Physical Function VF - Virtual Function If SR-IOV capability is present, use it to initialize Virtual Function PCI device instances. pci_sriov_init function will read SR-IOV registers to create VF devices under the PF PCI device and also bind driver if available. This function needs to be invoked from Physical function device driver which expects VF device support, creating minimal impact on existing framework. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
|
#
e0024741 |
|
23-Jul-2020 |
Stefan Roese <sr@denx.de> |
pci: pci-uclass: Dynamically allocate the PCI regions Instead of using a fixed length pre-allocated array of regions, this patch moves to dynamically allocating the regions based on the number of available regions plus the necessary regions for DRAM banks. Since MAX_PCI_REGIONS is not needed any more, its removed completely with this patch. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Thierry Reding <treding@nvidia.com> Cc: Marek Vasut <marek.vasut+renesas@gmail.com>
|
#
143eb5b1 |
|
12-May-2020 |
Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
drivers: pci: add api to get dma regions Add api to get dma regions. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
143eb5b1 |
|
12-May-2020 |
Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
drivers: pci: add api to get dma regions Add api to get dma regions. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
143eb5b1 |
|
12-May-2020 |
Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
drivers: pci: add api to get dma regions Add api to get dma regions. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
143eb5b1 |
|
12-May-2020 |
Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
drivers: pci: add api to get dma regions Add api to get dma regions. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
143eb5b1 |
|
12-May-2020 |
Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
drivers: pci: add api to get dma regions Add api to get dma regions. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
143eb5b1 |
|
12-May-2020 |
Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
drivers: pci: add api to get dma regions Add api to get dma regions. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
143eb5b1 |
|
12-May-2020 |
Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
drivers: pci: add api to get dma regions Add api to get dma regions. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
143eb5b1 |
|
12-May-2020 |
Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
drivers: pci: add api to get dma regions Add api to get dma regions. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
143eb5b1 |
|
12-May-2020 |
Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
drivers: pci: add api to get dma regions Add api to get dma regions. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
143eb5b1 |
|
12-May-2020 |
Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
drivers: pci: add api to get dma regions Add api to get dma regions. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
143eb5b1 |
|
12-May-2020 |
Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
drivers: pci: add api to get dma regions Add api to get dma regions. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
143eb5b1 |
|
12-May-2020 |
Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
drivers: pci: add api to get dma regions Add api to get dma regions. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
143eb5b1 |
|
12-May-2020 |
Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
drivers: pci: add api to get dma regions Add api to get dma regions. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
143eb5b1 |
|
12-May-2020 |
Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
drivers: pci: add api to get dma regions Add api to get dma regions. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
143eb5b1 |
|
12-May-2020 |
Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
drivers: pci: add api to get dma regions Add api to get dma regions. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
143eb5b1 |
|
12-May-2020 |
Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> |
drivers: pci: add api to get dma regions Add api to get dma regions. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
db75485f |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Add some PCI Express capability register offset definitions Add PCI Express capability definitions required by the Broadcom STB PCIe controller driver. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
b6687e19 |
|
25-May-2020 |
Sylwester Nawrocki <s.nawrocki@samsung.com> |
pci: Move some PCIe register offset definitions to a common header Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
5f20c283 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
pci: Fix typo in definition for PCI_DEV Fix a typo in the comment. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f0597038 |
|
08-Apr-2020 |
Simon Glass <sjg@chromium.org> |
pci: Add a macro to convert BDF from linux to U-Boot U-Boot's BDF format has its bits in the same position as the device tree PCI definition. Some x86 devices use linux format in their register format and it is useful to be able to convert to U-Boot format. Add a macro for this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
58fc2b54 |
|
05-Feb-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
pci: definition of pci_addr_t and pci_size_t Currently the size of pci_addr_t and pci_size_t depends on CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads to an error pci_hose_phys_to_bus: invalid physical address which is due to the truncation of the bus address in _dm_pci_phys_to_bus. Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error PCI: Failed autoconfig bar 10 So let's use unsigned long for pci_addr_t and pci_size_t if CONFIG_SYS_PCI_64BIT is not defined. Considering that 32bit U-Boot is used to launch some 64bit x86 systems we cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
194fca91 |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update a few more interfaces for const udevice * Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6dd4b014 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move pci_get_devfn() into a common file Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2206ac24 |
|
06-Dec-2019 |
Simon Glass <sjg@chromium.org> |
dm: pci: Allow delaying auto-config until after relocation At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6498fda1 |
|
21-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Remember the device being emulated Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bdaa9761 |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
pci: Correct 'specifified' and 'Plese' typos Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
37a1cf9c |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Move pci_offset_to_barnum() to pci.h This function is useful in PCI emulators. More it into the header file to avoid duplicating it in other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fae2c16e |
|
25-Sep-2019 |
Simon Glass <sjg@chromium.org> |
sandbox: pci: Drop the get_devfn() method This method is not used anymore since the bus/device/function of PCI devices can be obtained from their (parent's per-child) platform data. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b8e1f827 |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add API to issue FLR on a PCI function if supported Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0b143d8a |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
drivers: pci: add map_bar support for Enhanced Allocation Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
2204bc1b |
|
07-Jun-2019 |
Alex Marginean <alexm.osslist@gmail.com> |
pci: fixed dm_pci_map_bar comment The comment now indicates that the input argument bar is a register offset, not a BAR index. It also mentions which BARs are supported for type 0/1 and that the function can return 0 on error. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
62c72995 |
|
07-May-2019 |
Simon Glass <sjg@chromium.org> |
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
8781d04f |
|
05-Apr-2019 |
Ramon Fried <ramon.fried@gmail.com> |
pci: pci.h: add missing maskbit PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
aec4298c |
|
15-Mar-2019 |
Thierry Reding <treding@nvidia.com> |
pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale with the number of DRAM banks, otherwise we will end up with too little space in the hose->regions array to store all system memory regions. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
2253d648 |
|
11-Feb-2019 |
Stefan Roese <sr@denx.de> |
pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
7d38db55 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Fix comment in struct pci_child_platdata This is platdata, not private data, so the comment is currently incorrect. Fix it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
11503be4 |
|
16-Feb-2019 |
Simon Glass <sjg@chromium.org> |
pci: Don't export pci_hose_config_device() This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
b5214200 |
|
25-Jan-2019 |
Stefan Roese <sr@denx.de> |
pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
a8c5f8d3 |
|
15-Oct-2018 |
Bin Meng <bmeng.cn@gmail.com> |
dm: pci: Add APIs to find next capability and extended capability This introduces two new APIs dm_pci_find_next_capability() and dm_pci_find_next_ext_capability() to get PCI capability address and PCI express extended capability address for a given PCI device starting from a given offset. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
dac01fd8 |
|
03-Aug-2018 |
Bin Meng <bmeng.cn@gmail.com> |
dm: pci: Add APIs to find capability and extended capability This introduces two new APIs dm_pci_find_capability() and dm_pci_find_ext_capability() to get PCI capability address and PCI express extended capability address for a given PCI device. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
5d544f96 |
|
03-Aug-2018 |
Bin Meng <bmeng.cn@gmail.com> |
pci: Add all known capability and extended capability ids Currently we don't have a complete list of capability and extended capability ids. This adds them. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4345998a |
|
03-Aug-2018 |
Bin Meng <bmeng.cn@gmail.com> |
pci: sandbox: Support dynamically binding device driver At present all emulated sandbox pci devices must be present in the device tree in order to be used. The real world pci uclass driver supports pci device driver matching, and we should add such support on sandbox too. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
01259c93 |
|
03-Aug-2018 |
Bin Meng <bmeng.cn@gmail.com> |
pci: Remove 440ep-specific macros These macros should not be put in the generic pci.h header file. Since they are not referenced anywhere, remove them completely. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
5ce9aca8 |
|
14-May-2018 |
Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi> |
PCI: Document pciauto_region_allocate() Add a doc comment for pciauto_region_allocate(). Signed-off-by: Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d71975ae |
|
14-May-2018 |
Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi> |
PCI: autoconfig: Don't allocate 64-bit addresses to 32-bit only resources Currently, if we happen to allocate an address requiring 64 bits to a device only supporting 32-bit BARs, the address eventually gets silently truncated to 32 bits. Avoid this by adding a new flag to pciauto_region_allocate() to bail out in such situations. Signed-off-by: Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
83d290c5 |
|
06-May-2018 |
Tom Rini <trini@konsulko.com> |
SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
ed68ccbf |
|
13-Mar-2018 |
Stefan Roese <sr@denx.de> |
pci: Remove unused ppc4xx variable from struct pci_controller ppc4xx support was removed some time ago. Lets remove the now unused "pci_fb" variable from "struct pci_controller" as well. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Simon Glass <sjg@chromium.org>
|
#
badb9922 |
|
19-Sep-2017 |
Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi> |
pci: Add helper for implementing memory-mapped config space accesses This sort of pattern for implementing memory-mapped PCI config space accesses appears in U-Boot twice already, and a third user is coming up. So add helper functions to avoid code duplication, similar to how Linux has pci_generic_config_write and pci_generic_config_read. Signed-off-by: Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
6ecbe137 |
|
12-May-2017 |
Tim Harvey <tharvey@gateworks.com> |
drivers: pci: imx: add imx_pcie_remove function There is no dedicated reset signal wired up for the MX6QDL thus if the bootloader enables the link we need some special handling to get the core back into a state where it is safe to touch it for configuration. While there has been some special handling in the Linux kernel to do this, it was removed in 4.11 thus we need to do it properly in the bootloader and therefore without this if you enable PCI in the bootloader you will hang while booting the 4.11 kernel. This puts the PCIe controller back into a safe state for the kernel driver before launching the kernel. Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com> Tested-by: Peter Senna Tschudin <peter.senna@collabora.com>
|
#
eeb5b1ad |
|
10-Mar-2016 |
Stuart Yoder <stuart.yoder@nxp.com> |
pci: make pci_get_hose_head() available to external users Put pci_get_hose_head() prototype in header so it is available to external users, allowing them to find and iterate over all pci controllers. Signed-off-by: Stuart Yoder <stuart.yoder@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
4974a6ff |
|
06-Mar-2016 |
Simon Glass <sjg@chromium.org> |
pci: Correct a few comments and nits Two comments are missing a parameter and there is an extra blank line. Also two of the region access macros are misnamed. Correct these problems. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
319dba1f |
|
06-Mar-2016 |
Simon Glass <sjg@chromium.org> |
pci: Add functions to update PCI configuration registers It is common to read a config register value, clear and set some bits, then write back the updated value. Add functions to do this in one step, for convenience. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
308143ef |
|
02-Feb-2016 |
Bin Meng <bmeng.cn@gmail.com> |
dm: pci: Add missing forward declarations When CONFIG_DM_PCI_COMPAT is not on, there is only a forward declaration for pci_write_config32(). Add other missing ones. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
9d731c82 |
|
18-Jan-2016 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to write a BAR Add a driver-model version of the pci_write_bar32 function so that this is supported in the new API. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
7e78b9ef |
|
29-Nov-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Switch to DM API for PCI address mapping We should use the new address mapping functions unless we are in compatibility mode. Disable the old functions by default. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
21d1fe7e |
|
29-Nov-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add driver model API functions for address mapping At present the PCI address map functions use the old API. Add new functions for this so that drivers can be converted. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
bab17cf1 |
|
29-Nov-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to read a PCI BAR Add a driver-model function for reading the PCI BAR from a device. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
a0eb8356 |
|
29-Nov-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a driver-model version of pci_find_class() Add a function which scans the driver model device information rather than scanning the PCI bus again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
5c0bf647 |
|
29-Nov-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a driver-model version of pci_find_device() Add a function which scans the driver model device information rather than scanning the PCI bus again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
5e23b8b4 |
|
29-Nov-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Use driver model PCI API in auto-config At present we are using legacy functions even in the auto-configuration code used by driver model. Add a new pci_auto.c version which uses the correct API. Create a new pci_internal.h header to hold functions that are used within the PCI subsystem, but are not exported to other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f3f1faef |
|
29-Nov-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a dm_ prefix to pci_bus_find_bdf() Most driver model PCI functions have a dm_ prefix. At some point, when the old code is converted to driver model and the old functions are removed, we will drop that prefix. For consistency, we should use the dm_ prefix for all driver model functions. Update pci_bus_find_bdf() accordingly. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
21ccce1b |
|
29-Nov-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a dm_ prefix to pci_get_bdf() Most driver model PCI functions have a dm_ prefix. At some point, when the old code is converted to driver model and the old functions are removed, we will drop that prefix. For consistency, we should use the dm_ prefix for all driver model functions. Update pci_get_bdf() accordingly. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
3ba5f74a |
|
26-Nov-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Disable PCI compatibility functions by default We eventually need to drop the compatibility functions for driver model. As a first step, create a configuration option to enable them and hide them when the option is disabled. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
54fe7b1c |
|
26-Nov-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a comment about how to find struct pci_controller With driver mode, struct pci_controller is stored as uclass-private data. Add a comment to that effect. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f9260336 |
|
19-Nov-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to find the regions for a PCI bus This function looks up the controller and returns a pointer to each region type. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Stephen Warren <swarren@nvidia.com> Tested-by: Stephen Warren <swarren@nvidia.com>
|
#
9f60fb0d |
|
19-Nov-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to get the controller for a bus A PCI bus may be a bridge device where the controller is the bridge's parent. Add a function to return the controller device, given a PCI device. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Stephen Warren <swarren@nvidia.com> Tested-by: Stephen Warren <swarren@nvidia.com>
|
#
9289db6c |
|
19-Nov-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add functions to emulate 8- and 16-bit access Provide a few functions to support using 32-bit access to emulate 8- and 16-bit access. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Stephen Warren <swarren@nvidia.com> Tested-by: Stephen Warren <swarren@nvidia.com>
|
#
bcbe3d15 |
|
28-Sep-2015 |
Simon Glass <sjg@chromium.org> |
dm: Rename dev_get_parentdata() to dev_get_parent_priv() The current name is inconsistent with other driver model data access functions. Rename it and fix up all users. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
dc5740df |
|
22-Aug-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a comment to help find pci_hose_read_config_byte, etc. These functions are defined by macros so do not show up with grep. Add a comment to help. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
76c3fbcd |
|
10-Aug-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a way to iterate through all PCI devices These functions allow iteration through all PCI devices including bridges. The children of each PCI bus are returned in turn. This can be useful for configuring, checking or enumerating all the devices. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
66afb4ed |
|
10-Aug-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Provide friendly config access functions At present there are no PCI functions which allow access to PCI configuration using a struct udevice. This is a sad situation for driver model as it makes use of PCI harder. Add these functions. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
5f48d798 |
|
27-Jul-2015 |
Simon Glass <sjg@chromium.org> |
pci: Add a constant for an invalid interrupt Rather than using 0xff in the code, add a constant. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
ed5b580b |
|
09-Jul-2015 |
Minghuan Lian <Minghuan.Lian@freescale.com> |
drivers/pci: Add function to find an extended capability PCIe extends device's configuration space to 4k and provides extended capability. The patch adds function to find them. The code is ported from Linux PCIe driver. Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: York Sun <yorksun@freescale.com>
|
#
4b515e4f |
|
06-Jul-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a function to get the BDF for a device It is useful to be able to find the full PCI address (bus, device and function) for a PCI device. Add a function to provide this. Adjust the existing code to use this. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
aba92962 |
|
06-Jul-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add support for PCI driver matching At present all PCI devices must be present in the device tree in order to be used. Many or most PCI devices don't require any configuration other than that which is done automatically by U-Boot. It is inefficent to add a node with nothing but a compatible string in order to get a device working. Add a mechanism whereby PCI drivers can be declared along with the device parameters they support (vendor/device/class). When no suitable driver is found in the device tree the list of such devices is consulted to determine the correct driver. If this also fails, then a generic driver is used as before. The mechanism used is very similar to that provided by Linux and the header file defintions are copied from Linux 4.1. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
6c89663c |
|
07-Jul-2015 |
Bin Meng <bmeng.cn@gmail.com> |
pci: Configure expansion ROM during auto config process Currently PCI expansion ROM address is assigned by a call to pciauto_setup_rom() outside of the pci auto config process. This does not work when expansion ROM is on a device behind PCI bridge where bridge's memory limit register was already programmed to a value that does not cover the newly assigned expansion ROM address. To fix this, we should configure the ROM address during the auto config process. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Acked-by: Simon Glass <sjg@chromium.org>
|
#
aec241df |
|
07-Jun-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Use the correct hose when configuring devices Only the PCI controller has access to the PCI region information. Make sure to use the controller (rather than any attached bridges) when configuring devices. This corrects a failure to scan and configure devices when driver model is enabled for PCI. Also add a comment to explain the problem. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
36d0d3b4 |
|
05-Mar-2015 |
Simon Glass <sjg@chromium.org> |
dm: sandbox: pci: Add a PCI emulation uclass Since sandbox does not have real devices (unless it borrows those from the host) it must use emulations. Provide a uclass which permits PCI operations to be passed through to an emulation device. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
ff3e077b |
|
05-Mar-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Add a uclass for PCI Add a uclass for PCI controllers and a generic one for PCI devices. Adjust the 'pci' command and the existing PCI support to work with this new uclass. Keep most of the compatibility code in a separate file so that it can be removed one day. TODO: Add more header file comments to the new parts of pci.h Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
aab6724c |
|
05-Mar-2015 |
Simon Glass <sjg@chromium.org> |
dm: pci: Move common PCI functions into their own file Driver model will share many functions with the existing PCI implementation. Move these into their own file to avoid duplication and confusion. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
250e039d |
|
27-Jan-2015 |
Simon Glass <sjg@chromium.org> |
pci: Add a function to find a device by class There is an existing function prototype in the header file but it is not implemented. Implement something similar. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
4a2708a0 |
|
14-Jan-2015 |
Simon Glass <sjg@chromium.org> |
x86: Access the VGA ROM when needed Add code to the generic pci_rom file to access the VGA ROM in PCI space when needed. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
d622ac39 |
|
15-Dec-2014 |
Masahiro Yamada <yamada.m@jp.panasonic.com> |
powerpc: mpc824x: remove MPC824X cpu support All the MPC824X boards are still non-generic boards: A3000, CPC45, CU824, eXalion, MVBLUE, MUSENKI, Sandpoint824x, utx8245 Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Josef Wagner <Wagner@Microsys.de> Cc: Torsten Demke <torsten.demke@fci.com> Cc: Jim Thompson <jim@musenki.com> Cc: Greg Allen <gallen@arlut.utexas.edu>
|
#
e8a552eb |
|
14-Nov-2014 |
Simon Glass <sjg@chromium.org> |
pci: Add functions to read and write a BAR address Some PCI functions cannot be auto-configured. Add a function to set up a fixed BAR which can be used in these situations. Also add a function to read the current address of a BAR. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
4efe52bf |
|
12-Nov-2014 |
Thierry Reding <treding@nvidia.com> |
pci: Honour pci_skip_dev() When enumerating devices, honour the pci_skip_dev() function. This can be used by PCI controller drivers to restrict which devices will be probed. This is required by the NVIDIA Tegra PCIe controller driver, which will fail with a data abort exception if an access is attempted to a device number larger than 0 outside of bus 0. pci_skip_dev() is therefore implemented to prevent any such accesses. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
0991866c |
|
07-Aug-2014 |
Tim Harvey <tharvey@gateworks.com> |
pci: add support for board_pci_fixup_dev function Some board-level drivers may wish to have per-device fixup functions for PCI devices. Signed-off-by: Tim Harvey <tharvey@gateworks.com>
|
#
fa5cec03 |
|
08-Nov-2013 |
Paul Burton <paul.burton@imgtec.com> |
pci.h: allow inclusion in assembly source This patch simply #ifdef's out the C-specific parts of pci.h when it is included by an assembly file. This will allow the macros it contains to be used from assembly source as will be done in a followup commit adding support for more modern MIPS Malta boards. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
|
#
287df01e |
|
11-Oct-2013 |
Zhao Qiang <B45475@freescale.com> |
PCIe:change the method to get the address of a requested capability in configuration space. Previously, the address of a requested capability is define like that "#define PCI_DCR 0x78" But, the addresses of capabilities is different with regard to PCIe revs. So this method is not flexible. Now a function to get the address of a requested capability is added and used. It can get the address dynamically by capability ID. The step of this function: 1. Read Status register in PCIe configuration space to confirm that Capabilities List is valid. 2. Find the address of Capabilities Pointer Register. 3. Find the address of requested capability from the first capability. Signed-off-by: Zhao Qiang <B45475@freescale.com>
|
#
7b4e5844 |
|
03-Jul-2013 |
Zang Roy-R61911 <tie-fei.zang@freescale.com> |
powerpc/pcie: add PCIe version 3.x support T4240 PCIe IP is version 3.0 and has some update comparing previous QorIQ products. 1. Move Freescale specific register define to arch/powerpc/include/asm/fsl_pci.h and update the register offset define for T4240. 2. add the status/control register define use status/control register to judge the link status 3. The original code uses 'Programming Interface' field to judge if PCIE is EP or RC mode, however, T4240 does not support this functionality. According to PCIE specification, 'Header Type' offset 0x0e is used to indicate header type, so for PCIE controller, the patch changes code to use 'Header Type' field to identify if the PCIE is RC or EP mode. This patch fixes the PCIe card link up issue on T4240QDS. Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com>
|
#
1a459660 |
|
08-Jul-2013 |
Wolfgang Denk <wd@denx.de> |
Add GPL-2.0+ SPDX-License-Identifier to source files Signed-off-by: Wolfgang Denk <wd@denx.de> [trini: Fixup common/cmd_io.c] Signed-off-by: Tom Rini <trini@ti.com>
|
#
bc3442aa |
|
11-Jun-2013 |
Simon Glass <sjg@chromium.org> |
pci: Convert extern inline functions to static inline I am not sure of the meaning of extern inline, but this gives errors when building with function instrumenting enabled. Change these functions to static inline. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
842033e6 |
|
30-May-2013 |
Gabor Juhos <juhosg@openwrt.org> |
pci: introduce CONFIG_PCI_INDIRECT_BRIDGE option The pci_indirect.c file is always compiled when CONFIG_PCI is defined although the indirect PCI bridge support is not needed by every board. Introduce a new CONFIG_PCI_INDIRECT_BRIDGE config option and only compile indirect PCI bridge support if this options is enabled. Also add the new option into the configuration files of the boards which needs that. Compile tested for powerpc, x86, arm and nds32. MAKEALL results: powerpc: --------------------- SUMMARY ---------------------------- Boards compiled: 641 Boards with warnings but no errors: 2 ( ELPPC MPC8323ERDB ) ---------------------------------------------------------- Note: the warnings for ELPPC and MPC8323ERDB are present even without the actual patch. x86: --------------------- SUMMARY ---------------------------- Boards compiled: 1 ---------------------------------------------------------- arm: --------------------- SUMMARY ---------------------------- Boards compiled: 311 ---------------------------------------------------------- nds32: --------------------- SUMMARY ---------------------------- Boards compiled: 3 ---------------------------------------------------------- Cc: Tom Rini <trini@ti.com> Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com> Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
|
#
55ae10f8 |
|
20-Oct-2012 |
Bill Richardson <wfrichar@chromium.org> |
x86: gpio: Add GPIO driver for Intel ICH6 and later. Implement <asm-generic/gpio.h> functions for Intel ICH6 and later. Only GPIOs 0-31 are handled by this code. Signed-off-by: Bill Richardson <wfrichar@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
a3a70725 |
|
24-Mar-2012 |
Linus Walleij <linus.walleij@linaro.org> |
pci: declare pciauto functions in header The FSL PCI driver uses local prototypes for pciauto_[pre|post]scan_setup_bridge(), this does not seem right, so move them to the <pci.h> file. Fixed a small extern declaration too, this is harmless but distracts the view since all other prototypes are explicitly external. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
|
#
a1e47b66 |
|
03-Mar-2012 |
Linus Walleij <linus.walleij@linaro.org> |
pci: move pciauto_config_init() to pci.h Fixing build regressions for the Integrator I get find that a few boards try to work around the missing declaration of pciauto_config_init() by declaring it in the local scope. This does not make sense when the sibling functions are in <pci.h> so move the function to the header, ridding the build error in the Integrator and getting rid of the local declarations here and there. Reported-by: Wolfgang Denk <wd@denx.de> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
|
#
b03a466d |
|
01-Feb-2011 |
Prabhakar Kushwaha <prabhakar@freescale.com> |
powerpc/85xx: Handle PCIe initialization requires for P1021 class SoCs The P1011, P1012, P1015, P1016, P1020, P1021, P1024, & P1025 SoCs require that we initialize the SERDES registers if the lanes are configured for PCIe. Additionally these devices PCIe controller do not support ASPM and we have to explicitly disable it. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
|
#
10fa8d7c |
|
19-Jan-2011 |
Leo Liu <liucai.lfn@gmail.com> |
mpc83xx: fix pcie configuration space read/write This patch fix a problem for the pcie enumeration when the mpc83xx pcie controller is connected with switch or we use both of the two pcie controller. Signed-off-by: Leo Liu <liucai.lfn@gmail.com> fix codingstyle and compiler warning: 'pcie_priv' defined but not used Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
|
#
3a0e3c27 |
|
17-Dec-2010 |
Kumar Gala <galak@kernel.crashing.org> |
powerpc/fsl-pci: Determine pci_controller based on cfg addr for dts fixup Previously we passed in a specifically named struct pci_controller to determine if we had setup the particular PCI bus. Now we can search for the struct so we dont have to depend on the name or the struct being statically allocated. Introduced new find_hose_by_cfg_addr() to get back a pci_controller struct back by searching for it means we can do things like dynamically allocate them or not have to expose the static structures to all users. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Wolfgang Denk <wd@denx.de>
|
#
983eb9d1 |
|
29-Oct-2010 |
Peter Tyser <ptyser@xes-inc.com> |
pci: Clean up PCI info when CONFIG_PCI_SCAN_SHOW This change does the following: - Removes the printing of the PCI interrupt line value. This is normally set to 0 by U-Boot on bootup and is rarely used during everyday operation. - Prints out the PCI function number of a device. Previously a device with multiple functions would be printed identically 2 times, which is generally confusing. For example, on an Intel 2 port gigabit Ethernet card the following was displayed: ... 04 01 8086 1010 0200 00 04 01 8086 1010 0200 00 ... - Prints a text description of each device's PCI class instead of the raw PCI class code. The textual description makes it much easier to determine what devices are installed on a PCI bus. - Changes the general formatting of the PCI device output. Previous output: PCIE1: connected as Root Complex 04 01 8086 1010 0200 00 04 01 8086 1010 0200 00 03 00 10b5 8112 0604 00 02 01 10b5 8518 0604 00 02 02 10b5 8518 0604 00 08 00 1957 0040 0b20 00 07 00 10b5 8518 0604 00 09 00 10b5 8112 0604 00 07 01 10b5 8518 0604 00 07 02 10b5 8518 0604 00 06 00 10b5 8518 0604 00 02 03 10b5 8518 0604 00 01 00 10b5 8518 0604 00 PCIE1: Bus 00 - 0b PCIE2: connected as Root Complex 0d 00 1957 0040 0b20 00 PCIE2: Bus 0c - 0d Updated output: PCIE1: connected as Root Complex 04:01.0 - 8086:1010 - Network controller 04:01.1 - 8086:1010 - Network controller 03:00.0 - 10b5:8112 - Bridge device 02:01.0 - 10b5:8518 - Bridge device 02:02.0 - 10b5:8518 - Bridge device 08:00.0 - 1957:0040 - Processor 07:00.0 - 10b5:8518 - Bridge device 09:00.0 - 10b5:8112 - Bridge device 07:01.0 - 10b5:8518 - Bridge device 07:02.0 - 10b5:8518 - Bridge device 06:00.0 - 10b5:8518 - Bridge device 02:03.0 - 10b5:8518 - Bridge device 01:00.0 - 10b5:8518 - Bridge device PCIE1: Bus 00 - 0b PCIE2: connected as Root Complex 0d:00.0 - 1957:0040 - Processor PCIE2: Bus 0c - 0d Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
|
#
8295b944 |
|
05-Aug-2009 |
Kumar Gala <galak@kernel.crashing.org> |
pci/fsl_pci_init: Use PCIe capability to determine if controller is PCIe Change the code to use the PCIe capabilities register to determine if we are a PCIe controller or not. Additionally cleaned up some white space and formatting in the file. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
|
#
cc2a8c77 |
|
19-Feb-2009 |
Anton Vorontsov <avorontsov@ru.mvista.com> |
PCI: Add pci_last_busno() helper This is just a handy routine that reports last PCI busno: we walk down all the hoses and return last hose's last_busno. Will be used by PCI/PCIe initialization code. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
|
#
6e61fae4 |
|
03-Feb-2009 |
Becky Bruce <beckyb@kernel.crashing.org> |
drivers/pci: Create pci_map_bar function It is no longer always true that the pci bus address can be used as the virtual address for pci accesses. pci_map_bar() is created to return the virtual address for a pci region. Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org>
|
#
ff4e66e9 |
|
06-Feb-2009 |
Kumar Gala <galak@kernel.crashing.org> |
pci: Rename PCI_REGION_MEMORY to PCI_REGION_SYS_MEMORY for clarity The PCI_REGION_MEMORY and PCI_REGION_MEM are a bit to similar and can be confusing when reading the code. Rename PCI_REGION_MEMORY to PCI_REGION_SYS_MEMORY to clarify its used for system memory mapping purposes. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
|
#
fd6646c0 |
|
07-Jan-2009 |
Anton Vorontsov <avorontsov@ru.mvista.com> |
mpc83xx: Add support for MPC83xx PCI-E controllers This patch adds support for MPC83xx PCI-E controllers in Root Complex mode. The patch is based on Tony Li and Dave Liu work[1]. Though unlike the original patch, by default we don't register PCI-E buses for use in U-Boot, we only configure the controllers for future use in other OSes (Linux). This is done because we don't have enough of spare BATs to map all the PCI-E regions. To actually use PCI-E in U-Boot, users should explicitly define CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES symbol in the board file. And only then U-Boot will able to access PCI-E, but at the cost of disabled address translation. [1] http://lists.denx.de/pipermail/u-boot/2008-January/027630.html Signed-off-by: Tony Li <tony.li@freescale.com> Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Acked-by: Dave Liu <daveliu@freescale.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
|
#
30e76d5e |
|
21-Oct-2008 |
Kumar Gala <galak@kernel.crashing.org> |
pci: Allow for PCI addresses to be 64-bit PCI bus is inherently 64-bit. While not all system require access to the full 64-bit PCI address range some do. This allows those systems to enable the full PCI address width via CONFIG_SYS_PCI_64BIT. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Andrew Fleming-AFLEMING <afleming@freescale.com> Acked-by: Wolfgang Denk <wd@denx.de>
|
#
36f32675 |
|
07-May-2008 |
Becky Bruce <bgill@freescale.com> |
Update pci code to use phys_addr_t Physical addrs need to be represented by phys_addr_t, not unsigned long. Otherwise, systems that use CONFIG_PHYS_64BIT are going to fail mightily. Signed-off-by: Becky Bruce <becky.bruce@freescale.com>
|
#
63cec581 |
|
02-Aug-2007 |
Ed Swarthout <Ed.Swarthout@freescale.com> |
Make MPC8641's PCI/PCI-E driver a common driver for many FSL parts. All of the PCI/PCI-Express driver and initialization code that was in the MPC8641HPCN port has now been moved into the common drivers/fsl_pci_init.c. In a subsequent patch, this will be utilized by the 85xx ports as well. Common PCI-E IMMAP register blocks for FSL 85xx/86xx are added. Also enable the second PCI-Express controller on 8641 by getting its BATS and CFG_ setup right. Fixed a u16 vendor compiler warning in AHCI driver too. Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com> Signed-off-by: Zhang Wei <wei.zhang@freescale.com> Signed-off-by: Jon Loeliger <jdl@freescale.com>
|
#
13a7fcdf |
|
19-Oct-2006 |
Jon Loeliger <jdl@freescale.com> |
* Fix a bunch of compiler warnings for gcc 4.0 Signed-off-by: Matthew McClintock <msm@freescale.com>
|
#
7376eb87 |
|
11-Oct-2006 |
Matthew McClintock <msm@freescale.com> |
* Fix a bunch of compiler warnings for gcc 4.0 Signed-off-by: Matthew McClintock <msm@freescale.com>
|
#
f0e6f57f |
|
28-Jun-2006 |
Matthew McClintock <msm@freescale.com> |
* Added PCI-X #defines for PCI-X initialization Patch by Andy Fleming on 17-Mar-2006 Signed-off-by: Andy Fleming <afleming@freescale.com>
|
#
b636aaeb |
|
28-Jun-2006 |
Matthew McClintock <msm@freescale.com> |
* Added PCI-X #defines for PCI-X initialization Patch by Andy Fleming on 17-Mar-2006 Signed-off-by: Andy Fleming <afleming@freescale.com>
|
#
debb7354 |
|
26-Apr-2006 |
Jon Loeliger <jdl@freescale.com> |
Initial support for MPC8641 HPCN board.
|
#
993a2275 |
|
12-Mar-2006 |
Wolfgang Denk <wd@pollux.denx.de> |
Fix bad declaration on pci_cfgfunc_nothing Patch by Sam Song, 19 Jun 2005
|
#
a179012e |
|
11-Jan-2006 |
Kumar Gala <galak@kernel.crashing.org> |
Added support for PCI prefetchable region and BARs If a host controller sets up a region as prefetchable and a device's BAR denotes it as prefetchable, allocate the BAR into the prefetch region. If a BAR is prefetchable and no prefetchable region has been setup by the controller we fall back to allocating the BAR into the normally memory region. Patch by Kumar Gala 11 Jan 2006
|
#
c157d8e2 |
|
01-Aug-2005 |
Stefan Roese <sr@denx.de> |
Add support for AMCC PPC440EP/GR eval boards Yosemite and Yellowstone. Patch by Steven Blakeslee, 27 Jul 2005
|
#
7a8e9bed |
|
31-May-2003 |
wdenk <wdenk> |
* Patch by Marc Singer, 29 May 2003: Fixed rarp boot method for IA32 and other little-endian CPUs. * Patch by Marc Singer, 28 May 2003: Added port I/O commands. * Patch by Matthew McClintock, 28 May 2003 - cpu/mpc824x/start.S: fix relocation code when booting from RAM - minor patches for utx8245 * Patch by Daniel Engstr�m, 28 May 2003: x86 update * Patch by Dave Ellis, 9 May 2003 + 27 May 2003: add nand flash support to SXNI855T configuration fix/extend nand flash support: - fix 'nand erase' command so does not erase bad blocks - fix 'nand write' command so does not write to bad blocks - fix nand_probe() so handles no flash detected properly - add doc/README.nand - add .jffs2 and .oob options to nand read/write - add 'nand bad' command to list bad blocks - add 'clean' option to 'nand erase' to write JFFS2 clean markers - make NAND read/write faster * Patch by Rune Torgersen, 23 May 2003: Update for MPC8266ADS board
|
#
c7de829c |
|
19-Nov-2002 |
wdenk <wdenk> |
* Patch by Thomas Frieden, 13 Nov 2002: Add code for AmigaOne board (preliminary merge to U-Boot, still WIP) * Patch by Jon Diekema, 12 Nov 2002: - Adding URL for IEEE OUI lookup - Making the autoboot #defines dependent on CONFIG_AUTOBOOT_KEYED being defined. - In the CONFIG_EXTRA_ENV_SETTINGS #define, the root-on-initrd and root-on-nfs macros are designed to switch how the default boot method gets defined.
|
#
c609719b |
|
02-Nov-2002 |
wdenk <wdenk> |
Initial revision
|