#
d678a59d |
|
18-May-2024 |
Tom Rini <trini@konsulko.com> |
Revert "Merge patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"" When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"' I failed to notice that b4 noticed it was based on next and so took that as the base commit and merged that part of next to master. This reverts commit c8ffd1356d42223cbb8c86280a083cc3c93e6426, reversing changes made to 2ee6f3a5f7550de3599faef9704e166e5dcace35. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com> |
#
e51478ba |
|
27-Apr-2024 |
Tom Rini <trini@konsulko.com> |
x86: Remove <common.h> and add needed includes Remove <common.h> from all x86 architecture files and when needed add missing include files directly. Signed-off-by: Tom Rini <trini@konsulko.com> |
#
f72d0d4a |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Convert existing spy records to simple Very few of the existing event-spy records use the arguments they are passed. Update them to use a simple spy instead, to simplify the code. Where an adaptor function is currently used, remove it where possible. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
55171aed |
|
04-May-2023 |
Simon Glass <sjg@chromium.org> |
dm: Emit the arch_cpu_init_dm() even only before relocation The original function was only called once, before relocation. The new one is called again after relocation. This was not the intent of the original call. Fix this by renaming and updating the calling logic. With this, chromebook_link64 makes it through SPL. Fixes: 7fe32b3442f0 ("event: Convert arch_cpu_init_dm() to use events") Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
7fe32b34 |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert arch_cpu_init_dm() to use events Instead of a special function, send an event after driver model is inited and adjust the boards which use this function. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
35b65dd8 |
|
15-Dec-2020 |
Harald Seiler <hws@denx.de> |
reset: Remove addr parameter from reset_cpu() Historically, the reset_cpu() function had an `addr` parameter which was meant to pass in an address of the reset vector location, where the CPU should reset to. This feature is no longer used anywhere in U-Boot as all reset_cpu() implementations now ignore the passed value. Generic code has been added which always calls reset_cpu() with `0` which means this feature can no longer be used easily anyway. Over time, many implementations seem to have "misunderstood" the existence of this parameter as a way to customize/parameterize the reset (e.g. COLD vs WARM resets). As this is not properly supported, the code will almost always not do what it is intended to (because all call-sites just call reset_cpu() with 0). To avoid confusion and to clean up the codebase from unused left-overs of the past, remove the `addr` parameter entirely. Code which intends to support different kinds of resets should be rewritten as a sysreset driver instead. This transformation was done with the following coccinelle patch: @@ expression argvalue; @@ - reset_cpu(argvalue) + reset_cpu() @@ identifier argname; type argtype; @@ - reset_cpu(argtype argname) + reset_cpu(void) { ... } Signed-off-by: Harald Seiler <hws@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
401d1c4f |
|
30-Oct-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop asm/global_data.h from common header Move this out of the common header and include it only where needed. In a number of cases this requires adding "struct udevice;" to avoid adding another large header or in other cases replacing / adding missing header files that had been pulled in, very indirectly. Finally, we have a few cases where we did not need to include <asm/global_data.h> at all, so remove that include. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Rini <trini@konsulko.com> |
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
691d719d |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop init.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
30c7c434 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move checkcpu() out of common.h This function belongs in cpu_func.h so move it over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com> |
#
a827ba91 |
|
31-Aug-2019 |
Simon Glass <sjg@chromium.org> |
x86: pci: Drop the first parameter in pci_x86_r/w_config() This parameter is needed by the PCI driver-mode interface but is always NULL on x86. There are a number of calls to this function so it makes sense to minimise the parameters. Adjust the x86 function to omit the first parameter, and introduce stub functions to handle the conversion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/next to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com> |
#
83d290c5 |
|
06-May-2018 |
Tom Rini <trini@konsulko.com> |
SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com> |
#
76d1d02f |
|
28-Mar-2017 |
Simon Glass <sjg@chromium.org> |
board_f: x86: Use checkcpu() for CPU init At present we misuse print_cpuinfo() do so CPU init on x86. This is done because it is the next available call after the console is enabled. But several arches use checkcpu() instead. Despite the horrible name (which we can fix), it seems a better choice. Adjust the various x86 CPU implementations to move their init code into checkcpu() and use print_cpuinfo() only for printing CPU info. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Stefan Roese <sr@denx.de> |
#
8d8f3acd |
|
16-Jan-2017 |
Simon Glass <sjg@chromium.org> |
x86: ivybridge: Add more debugging for failures Add various debug() messages in places where errors occur. This aids with debugging. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
4cc00f06 |
|
25-Jul-2016 |
Simon Glass <sjg@chromium.org> |
x86: Add debugging when cpu_common_init() fails Add a debug() at this point to help figure out what is wrong. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
7e4a6ae6 |
|
16-Mar-2016 |
Simon Glass <sjg@chromium.org> |
x86: Move common PCH code into a common place The SATA indexed register write functions are common to several Intel PCHs. Move this into a common location. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
50dd3da0 |
|
11-Mar-2016 |
Simon Glass <sjg@chromium.org> |
x86: Move common CPU code to its own place Some of the Intel CPU code is common to several Intel CPUs. Move it into a common location along with required declarations. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
06d336cc |
|
11-Mar-2016 |
Simon Glass <sjg@chromium.org> |
x86: Create a common header for Intel register access There are several blocks of registers that are accessed from all over the code on Intel CPUs. These don't currently have their own driver and it is not clear whether having a driver makes sense. An example is the Memory Controller Hub (MCH). We map it to a known location on some Intel chips (mostly those without FSP - Firmware Support Package). Add a new header file for these registers, and move MCH into it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
9e66506d |
|
11-Mar-2016 |
Simon Glass <sjg@chromium.org> |
x86: Move microcode code to a common location This code is used on several Intel CPUs. Move it into a common location. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
3f603cbb |
|
11-Feb-2016 |
Simon Glass <sjg@chromium.org> |
dm: Use uclass_first_device_err() where it is useful Use this new function in places where it simplifies the code. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
5213f280 |
|
17-Jan-2016 |
Simon Glass <sjg@chromium.org> |
x86: ivybridge: Convert enable_usb_bar() to use DM PCI API Convert this function over to use the driver model PCI API. In this case we want to avoid using the real PCI devices since they have not yet been probed. Instead, write directly to their PCI configuration address. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
0c7645bd |
|
17-Jan-2016 |
Simon Glass <sjg@chromium.org> |
x86: ivybridge: Use the I2C driver to perform SMbus init Move the init code into the I2C driver. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Heiko Schocher <hs@denx.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
d46f2a68 |
|
17-Jan-2016 |
Simon Glass <sjg@chromium.org> |
x86: ivybridge: Do the SATA init before relocation The SATA device needs to set itself up so that it appears correctly on the PCI bus. The easiest way to do this is to set it up to probe before relocation. This can do the early setup. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
9fd11c7a |
|
17-Jan-2016 |
Simon Glass <sjg@chromium.org> |
x86: ivybridge: Move GPIO init to the LPC init() method This init can happen in the driver also. Move it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
17e0a9ab |
|
17-Jan-2016 |
Simon Glass <sjg@chromium.org> |
x86: ivybridge: Move graphics init much later We don't need to init the graphics controller so early. Move it alongside the other graphics setup, just before we run the ROM. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
f633efa3 |
|
17-Jan-2016 |
Simon Glass <sjg@chromium.org> |
x86: ivybridge: Probe the LPC in CPU init We can drop the explicit probe of the PCH since the LPC is a child device and this will happen automatically. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
655925a9 |
|
17-Jan-2016 |
Simon Glass <sjg@chromium.org> |
x86: ivybridge: Move northbridge init into the probe() method Now that we have a proper driver for the nortbridge, set it up in by probing it, and move the early init code into the probe() method. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
858361b1 |
|
17-Jan-2016 |
Simon Glass <sjg@chromium.org> |
x86: ivybridge: Rename bd82x6x_init() Rename the existing bd82x6x_init() to bd82x6x_init_extra(). We will remove this in a later patch. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
fe40bd4d |
|
17-Jan-2016 |
Simon Glass <sjg@chromium.org> |
x86: ivybridge: Move more init to the probe() function Move SPI and port80 init to lpc_early_init(), called from the LPC's probe() method. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
788cd908 |
|
17-Jan-2016 |
Simon Glass <sjg@chromium.org> |
x86: ivybridge: Move lpc_early_init() to probe() Move this code to the LPC's probe() method so that it will happen automatically when the LPC is probed before relocation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
4acc83d4 |
|
17-Jan-2016 |
Simon Glass <sjg@chromium.org> |
x86: ivybridge: Set up the LPC device using driver model Find the LPC device in arch_cpu_init_dm() as a first step to converting this code to use driver model. Probing the LPC will probe its parent (the PCH) automatically, so make sure that probing the PCH does nothing before relocation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
789fa275 |
|
25-Nov-2015 |
Bin Meng <bmeng.cn@gmail.com> |
x86: Remove HAVE_ACPI_RESUME These are currently dead codes. Until we have complete ACPI support, we don't know if it works or not. Remove to avoid confusion. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> |
#
80af3984 |
|
13-Nov-2015 |
Bin Meng <bmeng.cn@gmail.com> |
x86: Convert to use driver model timer Convert all x86 boards to use driver model tsc timer. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> |
#
7b95252d |
|
18-Oct-2015 |
Simon Glass <sjg@chromium.org> |
x86: chromebook_link: Enable the debug UART Add support for the debug UART on link. This is useful for early debugging. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
5021c81f |
|
28-Apr-2015 |
Simon Glass <sjg@chromium.org> |
x86: ivybridge: Use reset_cpu() Now that reset_cpu() functions correctly, use it instead of directly accessing the port. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
90b16d14 |
|
26-Mar-2015 |
Simon Glass <sjg@chromium.org> |
x86: chromebook_link: dts: Add PCH and LPC devices The PCH (Platform Controller Hub) is on the PCI bus, so show it as such. The LPC (Low Pin Count) and SPI bus are inside the PCH, so put these in the right place also. Rename the compatible strings to be more descriptive since this board is the only user. Once we are using driver model fully on x86, these will be dropped. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
aad78d27 |
|
05-Mar-2015 |
Simon Glass <sjg@chromium.org> |
dm: x86: pci: Convert chromebook_link to use driver model for pci Move chromebook_link over to driver model for PCI. This involves: - adding a uclass for platform controller hub - removing most of the existing PCI driver - adjusting how CPU init works to use driver model instead - rename the lpc compatible string (it will be removed later) This does not really take advantage of driver model fully, but it does work. Furture work will improve the code structure to remove many of the explicit calls to init the board. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
161d2e4e |
|
05-Mar-2015 |
Simon Glass <sjg@chromium.org> |
x86: Split up arch_cpu_init() At present we do more in this function than we should. Split out the post-driver-model part into a separate function. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
31f57c28 |
|
05-Mar-2015 |
Simon Glass <sjg@chromium.org> |
x86: Add a x86_ prefix to the x86-specific PCI functions These functions currently use a generic name, but they are for x86 only. This may introduce confusion and prevents U-Boot from using these names more widely. In fact it should be possible to remove these at some point and use generic functions, but for now, rename them. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
c72f74e2 |
|
01-Jan-2015 |
Simon Glass <sjg@chromium.org> |
x86: ivybridge: Update microcode early in boot At present the normal update (which happens much later) does not work. This seems to have something to do with the 'no eviction' mode in the CAR, or at least moving the microcode update after that causes it not to work. For now, do an update early on so that it definitely works. Also refuse to continue unless the microcode update check (later in boot) is successful. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
3a5659f7 |
|
01-Jan-2015 |
Simon Glass <sjg@chromium.org> |
x86: ivybridge: Drop support for ROM caching This is set up along with CAR (Cache-as-RAM) anyway. When we relocate we don't really need ROM caching (we read the VGA BIOS from ROM but that is about it) Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
95a5a474 |
|
12-Dec-2014 |
Bin Meng <bmeng.cn@gmail.com> |
x86: Add post failure codes for bist and car Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> |
#
3eafce05 |
|
12-Nov-2014 |
Simon Glass <sjg@chromium.org> |
x86: ivybridge: Add LAPIC support The local advanced programmable interrupt controller is not used much in U-Boot but we do need to set it up. Add basic support for this, which will be extended as needed. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
8e0df066 |
|
12-Nov-2014 |
Simon Glass <sjg@chromium.org> |
x86: ivybridge: Add early init for PCH devices Many PCH devices are hard-coded to a particular PCI address. Set these up early in case they are needed. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
77f9b1fb |
|
12-Nov-2014 |
Simon Glass <sjg@chromium.org> |
x86: ivybridge: Perform Intel microcode update on boot Microcode updates are stored in the device tree. Work through these and apply any that are needed. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
94060ff2 |
|
12-Nov-2014 |
Simon Glass <sjg@chromium.org> |
x86: ivybridge: Check BIST value on boot The built-in self test value should be checked before we continue booting. Refuse to continue if there is something wrong. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
f5fbbe95 |
|
12-Nov-2014 |
Simon Glass <sjg@chromium.org> |
x86: ivybridge: Perform initial CPU setup Set up the flex ratio (controls speed versus heat output) and a few other very early things. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
2b605154 |
|
12-Nov-2014 |
Simon Glass <sjg@chromium.org> |
x86: ivybridge: Add early LPC init so that serial works The PCH (Platform Controller Hub) includes an LPC (Low Pin Count) device which provides a serial port. This is accessible on Chromebooks, so enable it early in the boot process. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
6e5b12b6 |
|
12-Nov-2014 |
Simon Glass <sjg@chromium.org> |
x86: ivybridge: Enable PCI in early init Enable PCI so we can access devices that need to be set up before relocation. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
70a09c6c |
|
12-Nov-2014 |
Simon Glass <sjg@chromium.org> |
x86: chromebook_link: Implement CAR support (cache as RAM) Add support for CAR so that we have memory to use prior to DRAM init. On link there is a total of 128KB of CAR available, although some is used for the memory reference code. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
8ef07571 |
|
12-Nov-2014 |
Simon Glass <sjg@chromium.org> |
x86: Add chromebook_link board This board is a 'bare' version of the existing 'link 'board. It does not require coreboot to run, but is intended to start directly from the reset vector. This initial commit has place holders for a wide range of features. These will be added in follow-on patches and series. So far it cannot be booted as there is no ROM image produced, but it does build without errors. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
e51478ba |
|
27-Apr-2024 |
Tom Rini <trini@konsulko.com> |
x86: Remove <common.h> and add needed includes Remove <common.h> from all x86 architecture files and when needed add missing include files directly. Signed-off-by: Tom Rini <trini@konsulko.com> |
#
f72d0d4a |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Convert existing spy records to simple Very few of the existing event-spy records use the arguments they are passed. Update them to use a simple spy instead, to simplify the code. Where an adaptor function is currently used, remove it where possible. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
55171aed |
|
04-May-2023 |
Simon Glass <sjg@chromium.org> |
dm: Emit the arch_cpu_init_dm() even only before relocation The original function was only called once, before relocation. The new one is called again after relocation. This was not the intent of the original call. Fix this by renaming and updating the calling logic. With this, chromebook_link64 makes it through SPL. Fixes: 7fe32b3442f0 ("event: Convert arch_cpu_init_dm() to use events") Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
7fe32b34 |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert arch_cpu_init_dm() to use events Instead of a special function, send an event after driver model is inited and adjust the boards which use this function. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
35b65dd8 |
|
15-Dec-2020 |
Harald Seiler <hws@denx.de> |
reset: Remove addr parameter from reset_cpu() Historically, the reset_cpu() function had an `addr` parameter which was meant to pass in an address of the reset vector location, where the CPU should reset to. This feature is no longer used anywhere in U-Boot as all reset_cpu() implementations now ignore the passed value. Generic code has been added which always calls reset_cpu() with `0` which means this feature can no longer be used easily anyway. Over time, many implementations seem to have "misunderstood" the existence of this parameter as a way to customize/parameterize the reset (e.g. COLD vs WARM resets). As this is not properly supported, the code will almost always not do what it is intended to (because all call-sites just call reset_cpu() with 0). To avoid confusion and to clean up the codebase from unused left-overs of the past, remove the `addr` parameter entirely. Code which intends to support different kinds of resets should be rewritten as a sysreset driver instead. This transformation was done with the following coccinelle patch: @@ expression argvalue; @@ - reset_cpu(argvalue) + reset_cpu() @@ identifier argname; type argtype; @@ - reset_cpu(argtype argname) + reset_cpu(void) { ... } Signed-off-by: Harald Seiler <hws@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
401d1c4f |
|
30-Oct-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop asm/global_data.h from common header Move this out of the common header and include it only where needed. In a number of cases this requires adding "struct udevice;" to avoid adding another large header or in other cases replacing / adding missing header files that had been pulled in, very indirectly. Finally, we have a few cases where we did not need to include <asm/global_data.h> at all, so remove that include. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Rini <trini@konsulko.com> |
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
691d719d |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop init.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
30c7c434 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move checkcpu() out of common.h This function belongs in cpu_func.h so move it over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com> |
#
a827ba91 |
|
31-Aug-2019 |
Simon Glass <sjg@chromium.org> |
x86: pci: Drop the first parameter in pci_x86_r/w_config() This parameter is needed by the PCI driver-mode interface but is always NULL on x86. There are a number of calls to this function so it makes sense to minimise the parameters. Adjust the x86 function to omit the first parameter, and introduce stub functions to handle the conversion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/next to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com> |
#
83d290c5 |
|
06-May-2018 |
Tom Rini <trini@konsulko.com> |
SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com> |
#
76d1d02f |
|
28-Mar-2017 |
Simon Glass <sjg@chromium.org> |
board_f: x86: Use checkcpu() for CPU init At present we misuse print_cpuinfo() do so CPU init on x86. This is done because it is the next available call after the console is enabled. But several arches use checkcpu() instead. Despite the horrible name (which we can fix), it seems a better choice. Adjust the various x86 CPU implementations to move their init code into checkcpu() and use print_cpuinfo() only for printing CPU info. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Stefan Roese <sr@denx.de> |
#
8d8f3acd |
|
16-Jan-2017 |
Simon Glass <sjg@chromium.org> |
x86: ivybridge: Add more debugging for failures Add various debug() messages in places where errors occur. This aids with debugging. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
4cc00f06 |
|
25-Jul-2016 |
Simon Glass <sjg@chromium.org> |
x86: Add debugging when cpu_common_init() fails Add a debug() at this point to help figure out what is wrong. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
7e4a6ae6 |
|
16-Mar-2016 |
Simon Glass <sjg@chromium.org> |
x86: Move common PCH code into a common place The SATA indexed register write functions are common to several Intel PCHs. Move this into a common location. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
50dd3da0 |
|
11-Mar-2016 |
Simon Glass <sjg@chromium.org> |
x86: Move common CPU code to its own place Some of the Intel CPU code is common to several Intel CPUs. Move it into a common location along with required declarations. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
06d336cc |
|
11-Mar-2016 |
Simon Glass <sjg@chromium.org> |
x86: Create a common header for Intel register access There are several blocks of registers that are accessed from all over the code on Intel CPUs. These don't currently have their own driver and it is not clear whether having a driver makes sense. An example is the Memory Controller Hub (MCH). We map it to a known location on some Intel chips (mostly those without FSP - Firmware Support Package). Add a new header file for these registers, and move MCH into it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
9e66506d |
|
11-Mar-2016 |
Simon Glass <sjg@chromium.org> |
x86: Move microcode code to a common location This code is used on several Intel CPUs. Move it into a common location. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
3f603cbb |
|
11-Feb-2016 |
Simon Glass <sjg@chromium.org> |
dm: Use uclass_first_device_err() where it is useful Use this new function in places where it simplifies the code. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
5213f280 |
|
17-Jan-2016 |
Simon Glass <sjg@chromium.org> |
x86: ivybridge: Convert enable_usb_bar() to use DM PCI API Convert this function over to use the driver model PCI API. In this case we want to avoid using the real PCI devices since they have not yet been probed. Instead, write directly to their PCI configuration address. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
0c7645bd |
|
17-Jan-2016 |
Simon Glass <sjg@chromium.org> |
x86: ivybridge: Use the I2C driver to perform SMbus init Move the init code into the I2C driver. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Heiko Schocher <hs@denx.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
d46f2a68 |
|
17-Jan-2016 |
Simon Glass <sjg@chromium.org> |
x86: ivybridge: Do the SATA init before relocation The SATA device needs to set itself up so that it appears correctly on the PCI bus. The easiest way to do this is to set it up to probe before relocation. This can do the early setup. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
9fd11c7a |
|
17-Jan-2016 |
Simon Glass <sjg@chromium.org> |
x86: ivybridge: Move GPIO init to the LPC init() method This init can happen in the driver also. Move it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
17e0a9ab |
|
17-Jan-2016 |
Simon Glass <sjg@chromium.org> |
x86: ivybridge: Move graphics init much later We don't need to init the graphics controller so early. Move it alongside the other graphics setup, just before we run the ROM. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
f633efa3 |
|
17-Jan-2016 |
Simon Glass <sjg@chromium.org> |
x86: ivybridge: Probe the LPC in CPU init We can drop the explicit probe of the PCH since the LPC is a child device and this will happen automatically. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
655925a9 |
|
17-Jan-2016 |
Simon Glass <sjg@chromium.org> |
x86: ivybridge: Move northbridge init into the probe() method Now that we have a proper driver for the nortbridge, set it up in by probing it, and move the early init code into the probe() method. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
858361b1 |
|
17-Jan-2016 |
Simon Glass <sjg@chromium.org> |
x86: ivybridge: Rename bd82x6x_init() Rename the existing bd82x6x_init() to bd82x6x_init_extra(). We will remove this in a later patch. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
fe40bd4d |
|
17-Jan-2016 |
Simon Glass <sjg@chromium.org> |
x86: ivybridge: Move more init to the probe() function Move SPI and port80 init to lpc_early_init(), called from the LPC's probe() method. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
788cd908 |
|
17-Jan-2016 |
Simon Glass <sjg@chromium.org> |
x86: ivybridge: Move lpc_early_init() to probe() Move this code to the LPC's probe() method so that it will happen automatically when the LPC is probed before relocation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
4acc83d4 |
|
17-Jan-2016 |
Simon Glass <sjg@chromium.org> |
x86: ivybridge: Set up the LPC device using driver model Find the LPC device in arch_cpu_init_dm() as a first step to converting this code to use driver model. Probing the LPC will probe its parent (the PCH) automatically, so make sure that probing the PCH does nothing before relocation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
789fa275 |
|
25-Nov-2015 |
Bin Meng <bmeng.cn@gmail.com> |
x86: Remove HAVE_ACPI_RESUME These are currently dead codes. Until we have complete ACPI support, we don't know if it works or not. Remove to avoid confusion. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> |
#
80af3984 |
|
13-Nov-2015 |
Bin Meng <bmeng.cn@gmail.com> |
x86: Convert to use driver model timer Convert all x86 boards to use driver model tsc timer. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> |
#
7b95252d |
|
18-Oct-2015 |
Simon Glass <sjg@chromium.org> |
x86: chromebook_link: Enable the debug UART Add support for the debug UART on link. This is useful for early debugging. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
5021c81f |
|
28-Apr-2015 |
Simon Glass <sjg@chromium.org> |
x86: ivybridge: Use reset_cpu() Now that reset_cpu() functions correctly, use it instead of directly accessing the port. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
90b16d14 |
|
26-Mar-2015 |
Simon Glass <sjg@chromium.org> |
x86: chromebook_link: dts: Add PCH and LPC devices The PCH (Platform Controller Hub) is on the PCI bus, so show it as such. The LPC (Low Pin Count) and SPI bus are inside the PCH, so put these in the right place also. Rename the compatible strings to be more descriptive since this board is the only user. Once we are using driver model fully on x86, these will be dropped. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
aad78d27 |
|
05-Mar-2015 |
Simon Glass <sjg@chromium.org> |
dm: x86: pci: Convert chromebook_link to use driver model for pci Move chromebook_link over to driver model for PCI. This involves: - adding a uclass for platform controller hub - removing most of the existing PCI driver - adjusting how CPU init works to use driver model instead - rename the lpc compatible string (it will be removed later) This does not really take advantage of driver model fully, but it does work. Furture work will improve the code structure to remove many of the explicit calls to init the board. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
161d2e4e |
|
05-Mar-2015 |
Simon Glass <sjg@chromium.org> |
x86: Split up arch_cpu_init() At present we do more in this function than we should. Split out the post-driver-model part into a separate function. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
31f57c28 |
|
05-Mar-2015 |
Simon Glass <sjg@chromium.org> |
x86: Add a x86_ prefix to the x86-specific PCI functions These functions currently use a generic name, but they are for x86 only. This may introduce confusion and prevents U-Boot from using these names more widely. In fact it should be possible to remove these at some point and use generic functions, but for now, rename them. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
c72f74e2 |
|
01-Jan-2015 |
Simon Glass <sjg@chromium.org> |
x86: ivybridge: Update microcode early in boot At present the normal update (which happens much later) does not work. This seems to have something to do with the 'no eviction' mode in the CAR, or at least moving the microcode update after that causes it not to work. For now, do an update early on so that it definitely works. Also refuse to continue unless the microcode update check (later in boot) is successful. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
3a5659f7 |
|
01-Jan-2015 |
Simon Glass <sjg@chromium.org> |
x86: ivybridge: Drop support for ROM caching This is set up along with CAR (Cache-as-RAM) anyway. When we relocate we don't really need ROM caching (we read the VGA BIOS from ROM but that is about it) Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
95a5a474 |
|
12-Dec-2014 |
Bin Meng <bmeng.cn@gmail.com> |
x86: Add post failure codes for bist and car Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> |
#
3eafce05 |
|
12-Nov-2014 |
Simon Glass <sjg@chromium.org> |
x86: ivybridge: Add LAPIC support The local advanced programmable interrupt controller is not used much in U-Boot but we do need to set it up. Add basic support for this, which will be extended as needed. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
8e0df066 |
|
12-Nov-2014 |
Simon Glass <sjg@chromium.org> |
x86: ivybridge: Add early init for PCH devices Many PCH devices are hard-coded to a particular PCI address. Set these up early in case they are needed. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
77f9b1fb |
|
12-Nov-2014 |
Simon Glass <sjg@chromium.org> |
x86: ivybridge: Perform Intel microcode update on boot Microcode updates are stored in the device tree. Work through these and apply any that are needed. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
94060ff2 |
|
12-Nov-2014 |
Simon Glass <sjg@chromium.org> |
x86: ivybridge: Check BIST value on boot The built-in self test value should be checked before we continue booting. Refuse to continue if there is something wrong. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
f5fbbe95 |
|
12-Nov-2014 |
Simon Glass <sjg@chromium.org> |
x86: ivybridge: Perform initial CPU setup Set up the flex ratio (controls speed versus heat output) and a few other very early things. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
2b605154 |
|
12-Nov-2014 |
Simon Glass <sjg@chromium.org> |
x86: ivybridge: Add early LPC init so that serial works The PCH (Platform Controller Hub) includes an LPC (Low Pin Count) device which provides a serial port. This is accessible on Chromebooks, so enable it early in the boot process. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
6e5b12b6 |
|
12-Nov-2014 |
Simon Glass <sjg@chromium.org> |
x86: ivybridge: Enable PCI in early init Enable PCI so we can access devices that need to be set up before relocation. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
70a09c6c |
|
12-Nov-2014 |
Simon Glass <sjg@chromium.org> |
x86: chromebook_link: Implement CAR support (cache as RAM) Add support for CAR so that we have memory to use prior to DRAM init. On link there is a total of 128KB of CAR available, although some is used for the memory reference code. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
8ef07571 |
|
12-Nov-2014 |
Simon Glass <sjg@chromium.org> |
x86: Add chromebook_link board This board is a 'bare' version of the existing 'link 'board. It does not require coreboot to run, but is intended to start directly from the reset vector. This initial commit has place holders for a wide range of features. These will be added in follow-on patches and series. So far it cannot be booted as there is no ROM image produced, but it does build without errors. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
f72d0d4a |
|
21-Aug-2023 |
Simon Glass <sjg@chromium.org> |
event: Convert existing spy records to simple Very few of the existing event-spy records use the arguments they are passed. Update them to use a simple spy instead, to simplify the code. Where an adaptor function is currently used, remove it where possible. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
55171aed |
|
04-May-2023 |
Simon Glass <sjg@chromium.org> |
dm: Emit the arch_cpu_init_dm() even only before relocation The original function was only called once, before relocation. The new one is called again after relocation. This was not the intent of the original call. Fix this by renaming and updating the calling logic. With this, chromebook_link64 makes it through SPL. Fixes: 7fe32b3442f0 ("event: Convert arch_cpu_init_dm() to use events") Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
7fe32b34 |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert arch_cpu_init_dm() to use events Instead of a special function, send an event after driver model is inited and adjust the boards which use this function. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
35b65dd8 |
|
15-Dec-2020 |
Harald Seiler <hws@denx.de> |
reset: Remove addr parameter from reset_cpu() Historically, the reset_cpu() function had an `addr` parameter which was meant to pass in an address of the reset vector location, where the CPU should reset to. This feature is no longer used anywhere in U-Boot as all reset_cpu() implementations now ignore the passed value. Generic code has been added which always calls reset_cpu() with `0` which means this feature can no longer be used easily anyway. Over time, many implementations seem to have "misunderstood" the existence of this parameter as a way to customize/parameterize the reset (e.g. COLD vs WARM resets). As this is not properly supported, the code will almost always not do what it is intended to (because all call-sites just call reset_cpu() with 0). To avoid confusion and to clean up the codebase from unused left-overs of the past, remove the `addr` parameter entirely. Code which intends to support different kinds of resets should be rewritten as a sysreset driver instead. This transformation was done with the following coccinelle patch: @@ expression argvalue; @@ - reset_cpu(argvalue) + reset_cpu() @@ identifier argname; type argtype; @@ - reset_cpu(argtype argname) + reset_cpu(void) { ... } Signed-off-by: Harald Seiler <hws@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
401d1c4f |
|
30-Oct-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop asm/global_data.h from common header Move this out of the common header and include it only where needed. In a number of cases this requires adding "struct udevice;" to avoid adding another large header or in other cases replacing / adding missing header files that had been pulled in, very indirectly. Finally, we have a few cases where we did not need to include <asm/global_data.h> at all, so remove that include. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Rini <trini@konsulko.com> |
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
691d719d |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop init.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
30c7c434 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move checkcpu() out of common.h This function belongs in cpu_func.h so move it over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com> |
#
a827ba91 |
|
31-Aug-2019 |
Simon Glass <sjg@chromium.org> |
x86: pci: Drop the first parameter in pci_x86_r/w_config() This parameter is needed by the PCI driver-mode interface but is always NULL on x86. There are a number of calls to this function so it makes sense to minimise the parameters. Adjust the x86 function to omit the first parameter, and introduce stub functions to handle the conversion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/next to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com> |
#
83d290c5 |
|
06-May-2018 |
Tom Rini <trini@konsulko.com> |
SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com> |
#
76d1d02f |
|
28-Mar-2017 |
Simon Glass <sjg@chromium.org> |
board_f: x86: Use checkcpu() for CPU init At present we misuse print_cpuinfo() do so CPU init on x86. This is done because it is the next available call after the console is enabled. But several arches use checkcpu() instead. Despite the horrible name (which we can fix), it seems a better choice. Adjust the various x86 CPU implementations to move their init code into checkcpu() and use print_cpuinfo() only for printing CPU info. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Stefan Roese <sr@denx.de> |
#
8d8f3acd |
|
16-Jan-2017 |
Simon Glass <sjg@chromium.org> |
x86: ivybridge: Add more debugging for failures Add various debug() messages in places where errors occur. This aids with debugging. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
4cc00f06 |
|
25-Jul-2016 |
Simon Glass <sjg@chromium.org> |
x86: Add debugging when cpu_common_init() fails Add a debug() at this point to help figure out what is wrong. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
7e4a6ae6 |
|
16-Mar-2016 |
Simon Glass <sjg@chromium.org> |
x86: Move common PCH code into a common place The SATA indexed register write functions are common to several Intel PCHs. Move this into a common location. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
50dd3da0 |
|
11-Mar-2016 |
Simon Glass <sjg@chromium.org> |
x86: Move common CPU code to its own place Some of the Intel CPU code is common to several Intel CPUs. Move it into a common location along with required declarations. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
06d336cc |
|
11-Mar-2016 |
Simon Glass <sjg@chromium.org> |
x86: Create a common header for Intel register access There are several blocks of registers that are accessed from all over the code on Intel CPUs. These don't currently have their own driver and it is not clear whether having a driver makes sense. An example is the Memory Controller Hub (MCH). We map it to a known location on some Intel chips (mostly those without FSP - Firmware Support Package). Add a new header file for these registers, and move MCH into it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
9e66506d |
|
11-Mar-2016 |
Simon Glass <sjg@chromium.org> |
x86: Move microcode code to a common location This code is used on several Intel CPUs. Move it into a common location. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
3f603cbb |
|
11-Feb-2016 |
Simon Glass <sjg@chromium.org> |
dm: Use uclass_first_device_err() where it is useful Use this new function in places where it simplifies the code. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
5213f280 |
|
17-Jan-2016 |
Simon Glass <sjg@chromium.org> |
x86: ivybridge: Convert enable_usb_bar() to use DM PCI API Convert this function over to use the driver model PCI API. In this case we want to avoid using the real PCI devices since they have not yet been probed. Instead, write directly to their PCI configuration address. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
0c7645bd |
|
17-Jan-2016 |
Simon Glass <sjg@chromium.org> |
x86: ivybridge: Use the I2C driver to perform SMbus init Move the init code into the I2C driver. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Heiko Schocher <hs@denx.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
d46f2a68 |
|
17-Jan-2016 |
Simon Glass <sjg@chromium.org> |
x86: ivybridge: Do the SATA init before relocation The SATA device needs to set itself up so that it appears correctly on the PCI bus. The easiest way to do this is to set it up to probe before relocation. This can do the early setup. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
9fd11c7a |
|
17-Jan-2016 |
Simon Glass <sjg@chromium.org> |
x86: ivybridge: Move GPIO init to the LPC init() method This init can happen in the driver also. Move it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
17e0a9ab |
|
17-Jan-2016 |
Simon Glass <sjg@chromium.org> |
x86: ivybridge: Move graphics init much later We don't need to init the graphics controller so early. Move it alongside the other graphics setup, just before we run the ROM. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
f633efa3 |
|
17-Jan-2016 |
Simon Glass <sjg@chromium.org> |
x86: ivybridge: Probe the LPC in CPU init We can drop the explicit probe of the PCH since the LPC is a child device and this will happen automatically. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
655925a9 |
|
17-Jan-2016 |
Simon Glass <sjg@chromium.org> |
x86: ivybridge: Move northbridge init into the probe() method Now that we have a proper driver for the nortbridge, set it up in by probing it, and move the early init code into the probe() method. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
858361b1 |
|
17-Jan-2016 |
Simon Glass <sjg@chromium.org> |
x86: ivybridge: Rename bd82x6x_init() Rename the existing bd82x6x_init() to bd82x6x_init_extra(). We will remove this in a later patch. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
fe40bd4d |
|
17-Jan-2016 |
Simon Glass <sjg@chromium.org> |
x86: ivybridge: Move more init to the probe() function Move SPI and port80 init to lpc_early_init(), called from the LPC's probe() method. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
788cd908 |
|
17-Jan-2016 |
Simon Glass <sjg@chromium.org> |
x86: ivybridge: Move lpc_early_init() to probe() Move this code to the LPC's probe() method so that it will happen automatically when the LPC is probed before relocation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
4acc83d4 |
|
17-Jan-2016 |
Simon Glass <sjg@chromium.org> |
x86: ivybridge: Set up the LPC device using driver model Find the LPC device in arch_cpu_init_dm() as a first step to converting this code to use driver model. Probing the LPC will probe its parent (the PCH) automatically, so make sure that probing the PCH does nothing before relocation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
789fa275 |
|
25-Nov-2015 |
Bin Meng <bmeng.cn@gmail.com> |
x86: Remove HAVE_ACPI_RESUME These are currently dead codes. Until we have complete ACPI support, we don't know if it works or not. Remove to avoid confusion. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> |
#
80af3984 |
|
13-Nov-2015 |
Bin Meng <bmeng.cn@gmail.com> |
x86: Convert to use driver model timer Convert all x86 boards to use driver model tsc timer. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> |
#
7b95252d |
|
18-Oct-2015 |
Simon Glass <sjg@chromium.org> |
x86: chromebook_link: Enable the debug UART Add support for the debug UART on link. This is useful for early debugging. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
5021c81f |
|
28-Apr-2015 |
Simon Glass <sjg@chromium.org> |
x86: ivybridge: Use reset_cpu() Now that reset_cpu() functions correctly, use it instead of directly accessing the port. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
90b16d14 |
|
26-Mar-2015 |
Simon Glass <sjg@chromium.org> |
x86: chromebook_link: dts: Add PCH and LPC devices The PCH (Platform Controller Hub) is on the PCI bus, so show it as such. The LPC (Low Pin Count) and SPI bus are inside the PCH, so put these in the right place also. Rename the compatible strings to be more descriptive since this board is the only user. Once we are using driver model fully on x86, these will be dropped. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
aad78d27 |
|
05-Mar-2015 |
Simon Glass <sjg@chromium.org> |
dm: x86: pci: Convert chromebook_link to use driver model for pci Move chromebook_link over to driver model for PCI. This involves: - adding a uclass for platform controller hub - removing most of the existing PCI driver - adjusting how CPU init works to use driver model instead - rename the lpc compatible string (it will be removed later) This does not really take advantage of driver model fully, but it does work. Furture work will improve the code structure to remove many of the explicit calls to init the board. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
161d2e4e |
|
05-Mar-2015 |
Simon Glass <sjg@chromium.org> |
x86: Split up arch_cpu_init() At present we do more in this function than we should. Split out the post-driver-model part into a separate function. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
31f57c28 |
|
05-Mar-2015 |
Simon Glass <sjg@chromium.org> |
x86: Add a x86_ prefix to the x86-specific PCI functions These functions currently use a generic name, but they are for x86 only. This may introduce confusion and prevents U-Boot from using these names more widely. In fact it should be possible to remove these at some point and use generic functions, but for now, rename them. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
c72f74e2 |
|
01-Jan-2015 |
Simon Glass <sjg@chromium.org> |
x86: ivybridge: Update microcode early in boot At present the normal update (which happens much later) does not work. This seems to have something to do with the 'no eviction' mode in the CAR, or at least moving the microcode update after that causes it not to work. For now, do an update early on so that it definitely works. Also refuse to continue unless the microcode update check (later in boot) is successful. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
3a5659f7 |
|
01-Jan-2015 |
Simon Glass <sjg@chromium.org> |
x86: ivybridge: Drop support for ROM caching This is set up along with CAR (Cache-as-RAM) anyway. When we relocate we don't really need ROM caching (we read the VGA BIOS from ROM but that is about it) Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
95a5a474 |
|
12-Dec-2014 |
Bin Meng <bmeng.cn@gmail.com> |
x86: Add post failure codes for bist and car Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> |
#
3eafce05 |
|
12-Nov-2014 |
Simon Glass <sjg@chromium.org> |
x86: ivybridge: Add LAPIC support The local advanced programmable interrupt controller is not used much in U-Boot but we do need to set it up. Add basic support for this, which will be extended as needed. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
8e0df066 |
|
12-Nov-2014 |
Simon Glass <sjg@chromium.org> |
x86: ivybridge: Add early init for PCH devices Many PCH devices are hard-coded to a particular PCI address. Set these up early in case they are needed. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
77f9b1fb |
|
12-Nov-2014 |
Simon Glass <sjg@chromium.org> |
x86: ivybridge: Perform Intel microcode update on boot Microcode updates are stored in the device tree. Work through these and apply any that are needed. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
94060ff2 |
|
12-Nov-2014 |
Simon Glass <sjg@chromium.org> |
x86: ivybridge: Check BIST value on boot The built-in self test value should be checked before we continue booting. Refuse to continue if there is something wrong. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
f5fbbe95 |
|
12-Nov-2014 |
Simon Glass <sjg@chromium.org> |
x86: ivybridge: Perform initial CPU setup Set up the flex ratio (controls speed versus heat output) and a few other very early things. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
2b605154 |
|
12-Nov-2014 |
Simon Glass <sjg@chromium.org> |
x86: ivybridge: Add early LPC init so that serial works The PCH (Platform Controller Hub) includes an LPC (Low Pin Count) device which provides a serial port. This is accessible on Chromebooks, so enable it early in the boot process. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
6e5b12b6 |
|
12-Nov-2014 |
Simon Glass <sjg@chromium.org> |
x86: ivybridge: Enable PCI in early init Enable PCI so we can access devices that need to be set up before relocation. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
70a09c6c |
|
12-Nov-2014 |
Simon Glass <sjg@chromium.org> |
x86: chromebook_link: Implement CAR support (cache as RAM) Add support for CAR so that we have memory to use prior to DRAM init. On link there is a total of 128KB of CAR available, although some is used for the memory reference code. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
8ef07571 |
|
12-Nov-2014 |
Simon Glass <sjg@chromium.org> |
x86: Add chromebook_link board This board is a 'bare' version of the existing 'link 'board. It does not require coreboot to run, but is intended to start directly from the reset vector. This initial commit has place holders for a wide range of features. These will be added in follow-on patches and series. So far it cannot be booted as there is no ROM image produced, but it does build without errors. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
55171aed |
|
04-May-2023 |
Simon Glass <sjg@chromium.org> |
dm: Emit the arch_cpu_init_dm() even only before relocation The original function was only called once, before relocation. The new one is called again after relocation. This was not the intent of the original call. Fix this by renaming and updating the calling logic. With this, chromebook_link64 makes it through SPL. Fixes: 7fe32b3442f0 ("event: Convert arch_cpu_init_dm() to use events") Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
7fe32b34 |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert arch_cpu_init_dm() to use events Instead of a special function, send an event after driver model is inited and adjust the boards which use this function. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
35b65dd8 |
|
15-Dec-2020 |
Harald Seiler <hws@denx.de> |
reset: Remove addr parameter from reset_cpu() Historically, the reset_cpu() function had an `addr` parameter which was meant to pass in an address of the reset vector location, where the CPU should reset to. This feature is no longer used anywhere in U-Boot as all reset_cpu() implementations now ignore the passed value. Generic code has been added which always calls reset_cpu() with `0` which means this feature can no longer be used easily anyway. Over time, many implementations seem to have "misunderstood" the existence of this parameter as a way to customize/parameterize the reset (e.g. COLD vs WARM resets). As this is not properly supported, the code will almost always not do what it is intended to (because all call-sites just call reset_cpu() with 0). To avoid confusion and to clean up the codebase from unused left-overs of the past, remove the `addr` parameter entirely. Code which intends to support different kinds of resets should be rewritten as a sysreset driver instead. This transformation was done with the following coccinelle patch: @@ expression argvalue; @@ - reset_cpu(argvalue) + reset_cpu() @@ identifier argname; type argtype; @@ - reset_cpu(argtype argname) + reset_cpu(void) { ... } Signed-off-by: Harald Seiler <hws@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
401d1c4f |
|
30-Oct-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop asm/global_data.h from common header Move this out of the common header and include it only where needed. In a number of cases this requires adding "struct udevice;" to avoid adding another large header or in other cases replacing / adding missing header files that had been pulled in, very indirectly. Finally, we have a few cases where we did not need to include <asm/global_data.h> at all, so remove that include. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Rini <trini@konsulko.com> |
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
691d719d |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop init.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
30c7c434 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move checkcpu() out of common.h This function belongs in cpu_func.h so move it over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com> |
#
a827ba91 |
|
31-Aug-2019 |
Simon Glass <sjg@chromium.org> |
x86: pci: Drop the first parameter in pci_x86_r/w_config() This parameter is needed by the PCI driver-mode interface but is always NULL on x86. There are a number of calls to this function so it makes sense to minimise the parameters. Adjust the x86 function to omit the first parameter, and introduce stub functions to handle the conversion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/next to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com> |
#
83d290c5 |
|
06-May-2018 |
Tom Rini <trini@konsulko.com> |
SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com> |
#
76d1d02f |
|
28-Mar-2017 |
Simon Glass <sjg@chromium.org> |
board_f: x86: Use checkcpu() for CPU init At present we misuse print_cpuinfo() do so CPU init on x86. This is done because it is the next available call after the console is enabled. But several arches use checkcpu() instead. Despite the horrible name (which we can fix), it seems a better choice. Adjust the various x86 CPU implementations to move their init code into checkcpu() and use print_cpuinfo() only for printing CPU info. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Stefan Roese <sr@denx.de> |
#
8d8f3acd |
|
16-Jan-2017 |
Simon Glass <sjg@chromium.org> |
x86: ivybridge: Add more debugging for failures Add various debug() messages in places where errors occur. This aids with debugging. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
4cc00f06 |
|
25-Jul-2016 |
Simon Glass <sjg@chromium.org> |
x86: Add debugging when cpu_common_init() fails Add a debug() at this point to help figure out what is wrong. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
7e4a6ae6 |
|
16-Mar-2016 |
Simon Glass <sjg@chromium.org> |
x86: Move common PCH code into a common place The SATA indexed register write functions are common to several Intel PCHs. Move this into a common location. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
50dd3da0 |
|
11-Mar-2016 |
Simon Glass <sjg@chromium.org> |
x86: Move common CPU code to its own place Some of the Intel CPU code is common to several Intel CPUs. Move it into a common location along with required declarations. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
06d336cc |
|
11-Mar-2016 |
Simon Glass <sjg@chromium.org> |
x86: Create a common header for Intel register access There are several blocks of registers that are accessed from all over the code on Intel CPUs. These don't currently have their own driver and it is not clear whether having a driver makes sense. An example is the Memory Controller Hub (MCH). We map it to a known location on some Intel chips (mostly those without FSP - Firmware Support Package). Add a new header file for these registers, and move MCH into it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
9e66506d |
|
11-Mar-2016 |
Simon Glass <sjg@chromium.org> |
x86: Move microcode code to a common location This code is used on several Intel CPUs. Move it into a common location. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
3f603cbb |
|
11-Feb-2016 |
Simon Glass <sjg@chromium.org> |
dm: Use uclass_first_device_err() where it is useful Use this new function in places where it simplifies the code. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
5213f280 |
|
17-Jan-2016 |
Simon Glass <sjg@chromium.org> |
x86: ivybridge: Convert enable_usb_bar() to use DM PCI API Convert this function over to use the driver model PCI API. In this case we want to avoid using the real PCI devices since they have not yet been probed. Instead, write directly to their PCI configuration address. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
0c7645bd |
|
17-Jan-2016 |
Simon Glass <sjg@chromium.org> |
x86: ivybridge: Use the I2C driver to perform SMbus init Move the init code into the I2C driver. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Heiko Schocher <hs@denx.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
d46f2a68 |
|
17-Jan-2016 |
Simon Glass <sjg@chromium.org> |
x86: ivybridge: Do the SATA init before relocation The SATA device needs to set itself up so that it appears correctly on the PCI bus. The easiest way to do this is to set it up to probe before relocation. This can do the early setup. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
9fd11c7a |
|
17-Jan-2016 |
Simon Glass <sjg@chromium.org> |
x86: ivybridge: Move GPIO init to the LPC init() method This init can happen in the driver also. Move it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
17e0a9ab |
|
17-Jan-2016 |
Simon Glass <sjg@chromium.org> |
x86: ivybridge: Move graphics init much later We don't need to init the graphics controller so early. Move it alongside the other graphics setup, just before we run the ROM. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
f633efa3 |
|
17-Jan-2016 |
Simon Glass <sjg@chromium.org> |
x86: ivybridge: Probe the LPC in CPU init We can drop the explicit probe of the PCH since the LPC is a child device and this will happen automatically. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
655925a9 |
|
17-Jan-2016 |
Simon Glass <sjg@chromium.org> |
x86: ivybridge: Move northbridge init into the probe() method Now that we have a proper driver for the nortbridge, set it up in by probing it, and move the early init code into the probe() method. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
858361b1 |
|
17-Jan-2016 |
Simon Glass <sjg@chromium.org> |
x86: ivybridge: Rename bd82x6x_init() Rename the existing bd82x6x_init() to bd82x6x_init_extra(). We will remove this in a later patch. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
fe40bd4d |
|
17-Jan-2016 |
Simon Glass <sjg@chromium.org> |
x86: ivybridge: Move more init to the probe() function Move SPI and port80 init to lpc_early_init(), called from the LPC's probe() method. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
788cd908 |
|
17-Jan-2016 |
Simon Glass <sjg@chromium.org> |
x86: ivybridge: Move lpc_early_init() to probe() Move this code to the LPC's probe() method so that it will happen automatically when the LPC is probed before relocation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
4acc83d4 |
|
17-Jan-2016 |
Simon Glass <sjg@chromium.org> |
x86: ivybridge: Set up the LPC device using driver model Find the LPC device in arch_cpu_init_dm() as a first step to converting this code to use driver model. Probing the LPC will probe its parent (the PCH) automatically, so make sure that probing the PCH does nothing before relocation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
789fa275 |
|
25-Nov-2015 |
Bin Meng <bmeng.cn@gmail.com> |
x86: Remove HAVE_ACPI_RESUME These are currently dead codes. Until we have complete ACPI support, we don't know if it works or not. Remove to avoid confusion. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> |
#
80af3984 |
|
13-Nov-2015 |
Bin Meng <bmeng.cn@gmail.com> |
x86: Convert to use driver model timer Convert all x86 boards to use driver model tsc timer. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> |
#
7b95252d |
|
18-Oct-2015 |
Simon Glass <sjg@chromium.org> |
x86: chromebook_link: Enable the debug UART Add support for the debug UART on link. This is useful for early debugging. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
5021c81f |
|
28-Apr-2015 |
Simon Glass <sjg@chromium.org> |
x86: ivybridge: Use reset_cpu() Now that reset_cpu() functions correctly, use it instead of directly accessing the port. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
90b16d14 |
|
26-Mar-2015 |
Simon Glass <sjg@chromium.org> |
x86: chromebook_link: dts: Add PCH and LPC devices The PCH (Platform Controller Hub) is on the PCI bus, so show it as such. The LPC (Low Pin Count) and SPI bus are inside the PCH, so put these in the right place also. Rename the compatible strings to be more descriptive since this board is the only user. Once we are using driver model fully on x86, these will be dropped. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
aad78d27 |
|
05-Mar-2015 |
Simon Glass <sjg@chromium.org> |
dm: x86: pci: Convert chromebook_link to use driver model for pci Move chromebook_link over to driver model for PCI. This involves: - adding a uclass for platform controller hub - removing most of the existing PCI driver - adjusting how CPU init works to use driver model instead - rename the lpc compatible string (it will be removed later) This does not really take advantage of driver model fully, but it does work. Furture work will improve the code structure to remove many of the explicit calls to init the board. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
161d2e4e |
|
05-Mar-2015 |
Simon Glass <sjg@chromium.org> |
x86: Split up arch_cpu_init() At present we do more in this function than we should. Split out the post-driver-model part into a separate function. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
31f57c28 |
|
05-Mar-2015 |
Simon Glass <sjg@chromium.org> |
x86: Add a x86_ prefix to the x86-specific PCI functions These functions currently use a generic name, but they are for x86 only. This may introduce confusion and prevents U-Boot from using these names more widely. In fact it should be possible to remove these at some point and use generic functions, but for now, rename them. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
c72f74e2 |
|
01-Jan-2015 |
Simon Glass <sjg@chromium.org> |
x86: ivybridge: Update microcode early in boot At present the normal update (which happens much later) does not work. This seems to have something to do with the 'no eviction' mode in the CAR, or at least moving the microcode update after that causes it not to work. For now, do an update early on so that it definitely works. Also refuse to continue unless the microcode update check (later in boot) is successful. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
3a5659f7 |
|
01-Jan-2015 |
Simon Glass <sjg@chromium.org> |
x86: ivybridge: Drop support for ROM caching This is set up along with CAR (Cache-as-RAM) anyway. When we relocate we don't really need ROM caching (we read the VGA BIOS from ROM but that is about it) Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
95a5a474 |
|
12-Dec-2014 |
Bin Meng <bmeng.cn@gmail.com> |
x86: Add post failure codes for bist and car Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> |
#
3eafce05 |
|
12-Nov-2014 |
Simon Glass <sjg@chromium.org> |
x86: ivybridge: Add LAPIC support The local advanced programmable interrupt controller is not used much in U-Boot but we do need to set it up. Add basic support for this, which will be extended as needed. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
8e0df066 |
|
12-Nov-2014 |
Simon Glass <sjg@chromium.org> |
x86: ivybridge: Add early init for PCH devices Many PCH devices are hard-coded to a particular PCI address. Set these up early in case they are needed. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
77f9b1fb |
|
12-Nov-2014 |
Simon Glass <sjg@chromium.org> |
x86: ivybridge: Perform Intel microcode update on boot Microcode updates are stored in the device tree. Work through these and apply any that are needed. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
94060ff2 |
|
12-Nov-2014 |
Simon Glass <sjg@chromium.org> |
x86: ivybridge: Check BIST value on boot The built-in self test value should be checked before we continue booting. Refuse to continue if there is something wrong. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
f5fbbe95 |
|
12-Nov-2014 |
Simon Glass <sjg@chromium.org> |
x86: ivybridge: Perform initial CPU setup Set up the flex ratio (controls speed versus heat output) and a few other very early things. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
2b605154 |
|
12-Nov-2014 |
Simon Glass <sjg@chromium.org> |
x86: ivybridge: Add early LPC init so that serial works The PCH (Platform Controller Hub) includes an LPC (Low Pin Count) device which provides a serial port. This is accessible on Chromebooks, so enable it early in the boot process. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
6e5b12b6 |
|
12-Nov-2014 |
Simon Glass <sjg@chromium.org> |
x86: ivybridge: Enable PCI in early init Enable PCI so we can access devices that need to be set up before relocation. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
70a09c6c |
|
12-Nov-2014 |
Simon Glass <sjg@chromium.org> |
x86: chromebook_link: Implement CAR support (cache as RAM) Add support for CAR so that we have memory to use prior to DRAM init. On link there is a total of 128KB of CAR available, although some is used for the memory reference code. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
8ef07571 |
|
12-Nov-2014 |
Simon Glass <sjg@chromium.org> |
x86: Add chromebook_link board This board is a 'bare' version of the existing 'link 'board. It does not require coreboot to run, but is intended to start directly from the reset vector. This initial commit has place holders for a wide range of features. These will be added in follow-on patches and series. So far it cannot be booted as there is no ROM image produced, but it does build without errors. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
7fe32b34 |
|
04-Mar-2022 |
Simon Glass <sjg@chromium.org> |
event: Convert arch_cpu_init_dm() to use events Instead of a special function, send an event after driver model is inited and adjust the boards which use this function. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
35b65dd8 |
|
15-Dec-2020 |
Harald Seiler <hws@denx.de> |
reset: Remove addr parameter from reset_cpu() Historically, the reset_cpu() function had an `addr` parameter which was meant to pass in an address of the reset vector location, where the CPU should reset to. This feature is no longer used anywhere in U-Boot as all reset_cpu() implementations now ignore the passed value. Generic code has been added which always calls reset_cpu() with `0` which means this feature can no longer be used easily anyway. Over time, many implementations seem to have "misunderstood" the existence of this parameter as a way to customize/parameterize the reset (e.g. COLD vs WARM resets). As this is not properly supported, the code will almost always not do what it is intended to (because all call-sites just call reset_cpu() with 0). To avoid confusion and to clean up the codebase from unused left-overs of the past, remove the `addr` parameter entirely. Code which intends to support different kinds of resets should be rewritten as a sysreset driver instead. This transformation was done with the following coccinelle patch: @@ expression argvalue; @@ - reset_cpu(argvalue) + reset_cpu() @@ identifier argname; type argtype; @@ - reset_cpu(argtype argname) + reset_cpu(void) { ... } Signed-off-by: Harald Seiler <hws@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
401d1c4f |
|
30-Oct-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop asm/global_data.h from common header Move this out of the common header and include it only where needed. In a number of cases this requires adding "struct udevice;" to avoid adding another large header or in other cases replacing / adding missing header files that had been pulled in, very indirectly. Finally, we have a few cases where we did not need to include <asm/global_data.h> at all, so remove that include. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Rini <trini@konsulko.com> |
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
691d719d |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop init.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
30c7c434 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move checkcpu() out of common.h This function belongs in cpu_func.h so move it over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com> |
#
a827ba91 |
|
31-Aug-2019 |
Simon Glass <sjg@chromium.org> |
x86: pci: Drop the first parameter in pci_x86_r/w_config() This parameter is needed by the PCI driver-mode interface but is always NULL on x86. There are a number of calls to this function so it makes sense to minimise the parameters. Adjust the x86 function to omit the first parameter, and introduce stub functions to handle the conversion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/next to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com> |
#
83d290c5 |
|
06-May-2018 |
Tom Rini <trini@konsulko.com> |
SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com> |
#
76d1d02f |
|
28-Mar-2017 |
Simon Glass <sjg@chromium.org> |
board_f: x86: Use checkcpu() for CPU init At present we misuse print_cpuinfo() do so CPU init on x86. This is done because it is the next available call after the console is enabled. But several arches use checkcpu() instead. Despite the horrible name (which we can fix), it seems a better choice. Adjust the various x86 CPU implementations to move their init code into checkcpu() and use print_cpuinfo() only for printing CPU info. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Stefan Roese <sr@denx.de> |
#
8d8f3acd |
|
16-Jan-2017 |
Simon Glass <sjg@chromium.org> |
x86: ivybridge: Add more debugging for failures Add various debug() messages in places where errors occur. This aids with debugging. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
4cc00f06 |
|
25-Jul-2016 |
Simon Glass <sjg@chromium.org> |
x86: Add debugging when cpu_common_init() fails Add a debug() at this point to help figure out what is wrong. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
7e4a6ae6 |
|
16-Mar-2016 |
Simon Glass <sjg@chromium.org> |
x86: Move common PCH code into a common place The SATA indexed register write functions are common to several Intel PCHs. Move this into a common location. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
50dd3da0 |
|
11-Mar-2016 |
Simon Glass <sjg@chromium.org> |
x86: Move common CPU code to its own place Some of the Intel CPU code is common to several Intel CPUs. Move it into a common location along with required declarations. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
06d336cc |
|
11-Mar-2016 |
Simon Glass <sjg@chromium.org> |
x86: Create a common header for Intel register access There are several blocks of registers that are accessed from all over the code on Intel CPUs. These don't currently have their own driver and it is not clear whether having a driver makes sense. An example is the Memory Controller Hub (MCH). We map it to a known location on some Intel chips (mostly those without FSP - Firmware Support Package). Add a new header file for these registers, and move MCH into it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
9e66506d |
|
11-Mar-2016 |
Simon Glass <sjg@chromium.org> |
x86: Move microcode code to a common location This code is used on several Intel CPUs. Move it into a common location. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
3f603cbb |
|
11-Feb-2016 |
Simon Glass <sjg@chromium.org> |
dm: Use uclass_first_device_err() where it is useful Use this new function in places where it simplifies the code. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
5213f280 |
|
17-Jan-2016 |
Simon Glass <sjg@chromium.org> |
x86: ivybridge: Convert enable_usb_bar() to use DM PCI API Convert this function over to use the driver model PCI API. In this case we want to avoid using the real PCI devices since they have not yet been probed. Instead, write directly to their PCI configuration address. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
0c7645bd |
|
17-Jan-2016 |
Simon Glass <sjg@chromium.org> |
x86: ivybridge: Use the I2C driver to perform SMbus init Move the init code into the I2C driver. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Heiko Schocher <hs@denx.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
d46f2a68 |
|
17-Jan-2016 |
Simon Glass <sjg@chromium.org> |
x86: ivybridge: Do the SATA init before relocation The SATA device needs to set itself up so that it appears correctly on the PCI bus. The easiest way to do this is to set it up to probe before relocation. This can do the early setup. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
9fd11c7a |
|
17-Jan-2016 |
Simon Glass <sjg@chromium.org> |
x86: ivybridge: Move GPIO init to the LPC init() method This init can happen in the driver also. Move it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
17e0a9ab |
|
17-Jan-2016 |
Simon Glass <sjg@chromium.org> |
x86: ivybridge: Move graphics init much later We don't need to init the graphics controller so early. Move it alongside the other graphics setup, just before we run the ROM. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
f633efa3 |
|
17-Jan-2016 |
Simon Glass <sjg@chromium.org> |
x86: ivybridge: Probe the LPC in CPU init We can drop the explicit probe of the PCH since the LPC is a child device and this will happen automatically. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
655925a9 |
|
17-Jan-2016 |
Simon Glass <sjg@chromium.org> |
x86: ivybridge: Move northbridge init into the probe() method Now that we have a proper driver for the nortbridge, set it up in by probing it, and move the early init code into the probe() method. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
858361b1 |
|
17-Jan-2016 |
Simon Glass <sjg@chromium.org> |
x86: ivybridge: Rename bd82x6x_init() Rename the existing bd82x6x_init() to bd82x6x_init_extra(). We will remove this in a later patch. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
fe40bd4d |
|
17-Jan-2016 |
Simon Glass <sjg@chromium.org> |
x86: ivybridge: Move more init to the probe() function Move SPI and port80 init to lpc_early_init(), called from the LPC's probe() method. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
788cd908 |
|
17-Jan-2016 |
Simon Glass <sjg@chromium.org> |
x86: ivybridge: Move lpc_early_init() to probe() Move this code to the LPC's probe() method so that it will happen automatically when the LPC is probed before relocation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
4acc83d4 |
|
17-Jan-2016 |
Simon Glass <sjg@chromium.org> |
x86: ivybridge: Set up the LPC device using driver model Find the LPC device in arch_cpu_init_dm() as a first step to converting this code to use driver model. Probing the LPC will probe its parent (the PCH) automatically, so make sure that probing the PCH does nothing before relocation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
789fa275 |
|
25-Nov-2015 |
Bin Meng <bmeng.cn@gmail.com> |
x86: Remove HAVE_ACPI_RESUME These are currently dead codes. Until we have complete ACPI support, we don't know if it works or not. Remove to avoid confusion. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> |
#
80af3984 |
|
13-Nov-2015 |
Bin Meng <bmeng.cn@gmail.com> |
x86: Convert to use driver model timer Convert all x86 boards to use driver model tsc timer. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> |
#
7b95252d |
|
18-Oct-2015 |
Simon Glass <sjg@chromium.org> |
x86: chromebook_link: Enable the debug UART Add support for the debug UART on link. This is useful for early debugging. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
5021c81f |
|
28-Apr-2015 |
Simon Glass <sjg@chromium.org> |
x86: ivybridge: Use reset_cpu() Now that reset_cpu() functions correctly, use it instead of directly accessing the port. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
90b16d14 |
|
26-Mar-2015 |
Simon Glass <sjg@chromium.org> |
x86: chromebook_link: dts: Add PCH and LPC devices The PCH (Platform Controller Hub) is on the PCI bus, so show it as such. The LPC (Low Pin Count) and SPI bus are inside the PCH, so put these in the right place also. Rename the compatible strings to be more descriptive since this board is the only user. Once we are using driver model fully on x86, these will be dropped. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
aad78d27 |
|
05-Mar-2015 |
Simon Glass <sjg@chromium.org> |
dm: x86: pci: Convert chromebook_link to use driver model for pci Move chromebook_link over to driver model for PCI. This involves: - adding a uclass for platform controller hub - removing most of the existing PCI driver - adjusting how CPU init works to use driver model instead - rename the lpc compatible string (it will be removed later) This does not really take advantage of driver model fully, but it does work. Furture work will improve the code structure to remove many of the explicit calls to init the board. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
161d2e4e |
|
05-Mar-2015 |
Simon Glass <sjg@chromium.org> |
x86: Split up arch_cpu_init() At present we do more in this function than we should. Split out the post-driver-model part into a separate function. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
31f57c28 |
|
05-Mar-2015 |
Simon Glass <sjg@chromium.org> |
x86: Add a x86_ prefix to the x86-specific PCI functions These functions currently use a generic name, but they are for x86 only. This may introduce confusion and prevents U-Boot from using these names more widely. In fact it should be possible to remove these at some point and use generic functions, but for now, rename them. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
c72f74e2 |
|
01-Jan-2015 |
Simon Glass <sjg@chromium.org> |
x86: ivybridge: Update microcode early in boot At present the normal update (which happens much later) does not work. This seems to have something to do with the 'no eviction' mode in the CAR, or at least moving the microcode update after that causes it not to work. For now, do an update early on so that it definitely works. Also refuse to continue unless the microcode update check (later in boot) is successful. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
3a5659f7 |
|
01-Jan-2015 |
Simon Glass <sjg@chromium.org> |
x86: ivybridge: Drop support for ROM caching This is set up along with CAR (Cache-as-RAM) anyway. When we relocate we don't really need ROM caching (we read the VGA BIOS from ROM but that is about it) Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
95a5a474 |
|
12-Dec-2014 |
Bin Meng <bmeng.cn@gmail.com> |
x86: Add post failure codes for bist and car Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> |
#
3eafce05 |
|
12-Nov-2014 |
Simon Glass <sjg@chromium.org> |
x86: ivybridge: Add LAPIC support The local advanced programmable interrupt controller is not used much in U-Boot but we do need to set it up. Add basic support for this, which will be extended as needed. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
8e0df066 |
|
12-Nov-2014 |
Simon Glass <sjg@chromium.org> |
x86: ivybridge: Add early init for PCH devices Many PCH devices are hard-coded to a particular PCI address. Set these up early in case they are needed. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
77f9b1fb |
|
12-Nov-2014 |
Simon Glass <sjg@chromium.org> |
x86: ivybridge: Perform Intel microcode update on boot Microcode updates are stored in the device tree. Work through these and apply any that are needed. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
94060ff2 |
|
12-Nov-2014 |
Simon Glass <sjg@chromium.org> |
x86: ivybridge: Check BIST value on boot The built-in self test value should be checked before we continue booting. Refuse to continue if there is something wrong. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
f5fbbe95 |
|
12-Nov-2014 |
Simon Glass <sjg@chromium.org> |
x86: ivybridge: Perform initial CPU setup Set up the flex ratio (controls speed versus heat output) and a few other very early things. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
2b605154 |
|
12-Nov-2014 |
Simon Glass <sjg@chromium.org> |
x86: ivybridge: Add early LPC init so that serial works The PCH (Platform Controller Hub) includes an LPC (Low Pin Count) device which provides a serial port. This is accessible on Chromebooks, so enable it early in the boot process. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
6e5b12b6 |
|
12-Nov-2014 |
Simon Glass <sjg@chromium.org> |
x86: ivybridge: Enable PCI in early init Enable PCI so we can access devices that need to be set up before relocation. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
70a09c6c |
|
12-Nov-2014 |
Simon Glass <sjg@chromium.org> |
x86: chromebook_link: Implement CAR support (cache as RAM) Add support for CAR so that we have memory to use prior to DRAM init. On link there is a total of 128KB of CAR available, although some is used for the memory reference code. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
8ef07571 |
|
12-Nov-2014 |
Simon Glass <sjg@chromium.org> |
x86: Add chromebook_link board This board is a 'bare' version of the existing 'link 'board. It does not require coreboot to run, but is intended to start directly from the reset vector. This initial commit has place holders for a wide range of features. These will be added in follow-on patches and series. So far it cannot be booted as there is no ROM image produced, but it does build without errors. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
35b65dd8 |
|
15-Dec-2020 |
Harald Seiler <hws@denx.de> |
reset: Remove addr parameter from reset_cpu() Historically, the reset_cpu() function had an `addr` parameter which was meant to pass in an address of the reset vector location, where the CPU should reset to. This feature is no longer used anywhere in U-Boot as all reset_cpu() implementations now ignore the passed value. Generic code has been added which always calls reset_cpu() with `0` which means this feature can no longer be used easily anyway. Over time, many implementations seem to have "misunderstood" the existence of this parameter as a way to customize/parameterize the reset (e.g. COLD vs WARM resets). As this is not properly supported, the code will almost always not do what it is intended to (because all call-sites just call reset_cpu() with 0). To avoid confusion and to clean up the codebase from unused left-overs of the past, remove the `addr` parameter entirely. Code which intends to support different kinds of resets should be rewritten as a sysreset driver instead. This transformation was done with the following coccinelle patch: @@ expression argvalue; @@ - reset_cpu(argvalue) + reset_cpu() @@ identifier argname; type argtype; @@ - reset_cpu(argtype argname) + reset_cpu(void) { ... } Signed-off-by: Harald Seiler <hws@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
401d1c4f |
|
30-Oct-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop asm/global_data.h from common header Move this out of the common header and include it only where needed. In a number of cases this requires adding "struct udevice;" to avoid adding another large header or in other cases replacing / adding missing header files that had been pulled in, very indirectly. Finally, we have a few cases where we did not need to include <asm/global_data.h> at all, so remove that include. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Rini <trini@konsulko.com> |
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
691d719d |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop init.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
30c7c434 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move checkcpu() out of common.h This function belongs in cpu_func.h so move it over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com> |
#
a827ba91 |
|
31-Aug-2019 |
Simon Glass <sjg@chromium.org> |
x86: pci: Drop the first parameter in pci_x86_r/w_config() This parameter is needed by the PCI driver-mode interface but is always NULL on x86. There are a number of calls to this function so it makes sense to minimise the parameters. Adjust the x86 function to omit the first parameter, and introduce stub functions to handle the conversion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/next to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com> |
#
83d290c5 |
|
06-May-2018 |
Tom Rini <trini@konsulko.com> |
SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com> |
#
76d1d02f |
|
28-Mar-2017 |
Simon Glass <sjg@chromium.org> |
board_f: x86: Use checkcpu() for CPU init At present we misuse print_cpuinfo() do so CPU init on x86. This is done because it is the next available call after the console is enabled. But several arches use checkcpu() instead. Despite the horrible name (which we can fix), it seems a better choice. Adjust the various x86 CPU implementations to move their init code into checkcpu() and use print_cpuinfo() only for printing CPU info. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Stefan Roese <sr@denx.de> |
#
8d8f3acd |
|
16-Jan-2017 |
Simon Glass <sjg@chromium.org> |
x86: ivybridge: Add more debugging for failures Add various debug() messages in places where errors occur. This aids with debugging. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
4cc00f06 |
|
25-Jul-2016 |
Simon Glass <sjg@chromium.org> |
x86: Add debugging when cpu_common_init() fails Add a debug() at this point to help figure out what is wrong. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
7e4a6ae6 |
|
16-Mar-2016 |
Simon Glass <sjg@chromium.org> |
x86: Move common PCH code into a common place The SATA indexed register write functions are common to several Intel PCHs. Move this into a common location. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
50dd3da0 |
|
11-Mar-2016 |
Simon Glass <sjg@chromium.org> |
x86: Move common CPU code to its own place Some of the Intel CPU code is common to several Intel CPUs. Move it into a common location along with required declarations. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
06d336cc |
|
11-Mar-2016 |
Simon Glass <sjg@chromium.org> |
x86: Create a common header for Intel register access There are several blocks of registers that are accessed from all over the code on Intel CPUs. These don't currently have their own driver and it is not clear whether having a driver makes sense. An example is the Memory Controller Hub (MCH). We map it to a known location on some Intel chips (mostly those without FSP - Firmware Support Package). Add a new header file for these registers, and move MCH into it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
9e66506d |
|
11-Mar-2016 |
Simon Glass <sjg@chromium.org> |
x86: Move microcode code to a common location This code is used on several Intel CPUs. Move it into a common location. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
3f603cbb |
|
11-Feb-2016 |
Simon Glass <sjg@chromium.org> |
dm: Use uclass_first_device_err() where it is useful Use this new function in places where it simplifies the code. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
5213f280 |
|
17-Jan-2016 |
Simon Glass <sjg@chromium.org> |
x86: ivybridge: Convert enable_usb_bar() to use DM PCI API Convert this function over to use the driver model PCI API. In this case we want to avoid using the real PCI devices since they have not yet been probed. Instead, write directly to their PCI configuration address. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
0c7645bd |
|
17-Jan-2016 |
Simon Glass <sjg@chromium.org> |
x86: ivybridge: Use the I2C driver to perform SMbus init Move the init code into the I2C driver. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Heiko Schocher <hs@denx.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
d46f2a68 |
|
17-Jan-2016 |
Simon Glass <sjg@chromium.org> |
x86: ivybridge: Do the SATA init before relocation The SATA device needs to set itself up so that it appears correctly on the PCI bus. The easiest way to do this is to set it up to probe before relocation. This can do the early setup. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
9fd11c7a |
|
17-Jan-2016 |
Simon Glass <sjg@chromium.org> |
x86: ivybridge: Move GPIO init to the LPC init() method This init can happen in the driver also. Move it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
17e0a9ab |
|
17-Jan-2016 |
Simon Glass <sjg@chromium.org> |
x86: ivybridge: Move graphics init much later We don't need to init the graphics controller so early. Move it alongside the other graphics setup, just before we run the ROM. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
f633efa3 |
|
17-Jan-2016 |
Simon Glass <sjg@chromium.org> |
x86: ivybridge: Probe the LPC in CPU init We can drop the explicit probe of the PCH since the LPC is a child device and this will happen automatically. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
655925a9 |
|
17-Jan-2016 |
Simon Glass <sjg@chromium.org> |
x86: ivybridge: Move northbridge init into the probe() method Now that we have a proper driver for the nortbridge, set it up in by probing it, and move the early init code into the probe() method. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
858361b1 |
|
17-Jan-2016 |
Simon Glass <sjg@chromium.org> |
x86: ivybridge: Rename bd82x6x_init() Rename the existing bd82x6x_init() to bd82x6x_init_extra(). We will remove this in a later patch. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
fe40bd4d |
|
17-Jan-2016 |
Simon Glass <sjg@chromium.org> |
x86: ivybridge: Move more init to the probe() function Move SPI and port80 init to lpc_early_init(), called from the LPC's probe() method. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
788cd908 |
|
17-Jan-2016 |
Simon Glass <sjg@chromium.org> |
x86: ivybridge: Move lpc_early_init() to probe() Move this code to the LPC's probe() method so that it will happen automatically when the LPC is probed before relocation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
4acc83d4 |
|
17-Jan-2016 |
Simon Glass <sjg@chromium.org> |
x86: ivybridge: Set up the LPC device using driver model Find the LPC device in arch_cpu_init_dm() as a first step to converting this code to use driver model. Probing the LPC will probe its parent (the PCH) automatically, so make sure that probing the PCH does nothing before relocation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
789fa275 |
|
25-Nov-2015 |
Bin Meng <bmeng.cn@gmail.com> |
x86: Remove HAVE_ACPI_RESUME These are currently dead codes. Until we have complete ACPI support, we don't know if it works or not. Remove to avoid confusion. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> |
#
80af3984 |
|
13-Nov-2015 |
Bin Meng <bmeng.cn@gmail.com> |
x86: Convert to use driver model timer Convert all x86 boards to use driver model tsc timer. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> |
#
7b95252d |
|
18-Oct-2015 |
Simon Glass <sjg@chromium.org> |
x86: chromebook_link: Enable the debug UART Add support for the debug UART on link. This is useful for early debugging. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
5021c81f |
|
28-Apr-2015 |
Simon Glass <sjg@chromium.org> |
x86: ivybridge: Use reset_cpu() Now that reset_cpu() functions correctly, use it instead of directly accessing the port. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
90b16d14 |
|
26-Mar-2015 |
Simon Glass <sjg@chromium.org> |
x86: chromebook_link: dts: Add PCH and LPC devices The PCH (Platform Controller Hub) is on the PCI bus, so show it as such. The LPC (Low Pin Count) and SPI bus are inside the PCH, so put these in the right place also. Rename the compatible strings to be more descriptive since this board is the only user. Once we are using driver model fully on x86, these will be dropped. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
aad78d27 |
|
05-Mar-2015 |
Simon Glass <sjg@chromium.org> |
dm: x86: pci: Convert chromebook_link to use driver model for pci Move chromebook_link over to driver model for PCI. This involves: - adding a uclass for platform controller hub - removing most of the existing PCI driver - adjusting how CPU init works to use driver model instead - rename the lpc compatible string (it will be removed later) This does not really take advantage of driver model fully, but it does work. Furture work will improve the code structure to remove many of the explicit calls to init the board. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
161d2e4e |
|
05-Mar-2015 |
Simon Glass <sjg@chromium.org> |
x86: Split up arch_cpu_init() At present we do more in this function than we should. Split out the post-driver-model part into a separate function. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
31f57c28 |
|
05-Mar-2015 |
Simon Glass <sjg@chromium.org> |
x86: Add a x86_ prefix to the x86-specific PCI functions These functions currently use a generic name, but they are for x86 only. This may introduce confusion and prevents U-Boot from using these names more widely. In fact it should be possible to remove these at some point and use generic functions, but for now, rename them. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
c72f74e2 |
|
01-Jan-2015 |
Simon Glass <sjg@chromium.org> |
x86: ivybridge: Update microcode early in boot At present the normal update (which happens much later) does not work. This seems to have something to do with the 'no eviction' mode in the CAR, or at least moving the microcode update after that causes it not to work. For now, do an update early on so that it definitely works. Also refuse to continue unless the microcode update check (later in boot) is successful. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
3a5659f7 |
|
01-Jan-2015 |
Simon Glass <sjg@chromium.org> |
x86: ivybridge: Drop support for ROM caching This is set up along with CAR (Cache-as-RAM) anyway. When we relocate we don't really need ROM caching (we read the VGA BIOS from ROM but that is about it) Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
95a5a474 |
|
12-Dec-2014 |
Bin Meng <bmeng.cn@gmail.com> |
x86: Add post failure codes for bist and car Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> |
#
3eafce05 |
|
12-Nov-2014 |
Simon Glass <sjg@chromium.org> |
x86: ivybridge: Add LAPIC support The local advanced programmable interrupt controller is not used much in U-Boot but we do need to set it up. Add basic support for this, which will be extended as needed. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
8e0df066 |
|
12-Nov-2014 |
Simon Glass <sjg@chromium.org> |
x86: ivybridge: Add early init for PCH devices Many PCH devices are hard-coded to a particular PCI address. Set these up early in case they are needed. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
77f9b1fb |
|
12-Nov-2014 |
Simon Glass <sjg@chromium.org> |
x86: ivybridge: Perform Intel microcode update on boot Microcode updates are stored in the device tree. Work through these and apply any that are needed. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
94060ff2 |
|
12-Nov-2014 |
Simon Glass <sjg@chromium.org> |
x86: ivybridge: Check BIST value on boot The built-in self test value should be checked before we continue booting. Refuse to continue if there is something wrong. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
f5fbbe95 |
|
12-Nov-2014 |
Simon Glass <sjg@chromium.org> |
x86: ivybridge: Perform initial CPU setup Set up the flex ratio (controls speed versus heat output) and a few other very early things. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
2b605154 |
|
12-Nov-2014 |
Simon Glass <sjg@chromium.org> |
x86: ivybridge: Add early LPC init so that serial works The PCH (Platform Controller Hub) includes an LPC (Low Pin Count) device which provides a serial port. This is accessible on Chromebooks, so enable it early in the boot process. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
6e5b12b6 |
|
12-Nov-2014 |
Simon Glass <sjg@chromium.org> |
x86: ivybridge: Enable PCI in early init Enable PCI so we can access devices that need to be set up before relocation. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
70a09c6c |
|
12-Nov-2014 |
Simon Glass <sjg@chromium.org> |
x86: chromebook_link: Implement CAR support (cache as RAM) Add support for CAR so that we have memory to use prior to DRAM init. On link there is a total of 128KB of CAR available, although some is used for the memory reference code. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
8ef07571 |
|
12-Nov-2014 |
Simon Glass <sjg@chromium.org> |
x86: Add chromebook_link board This board is a 'bare' version of the existing 'link 'board. It does not require coreboot to run, but is intended to start directly from the reset vector. This initial commit has place holders for a wide range of features. These will be added in follow-on patches and series. So far it cannot be booted as there is no ROM image produced, but it does build without errors. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
401d1c4f |
|
30-Oct-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop asm/global_data.h from common header Move this out of the common header and include it only where needed. In a number of cases this requires adding "struct udevice;" to avoid adding another large header or in other cases replacing / adding missing header files that had been pulled in, very indirectly. Finally, we have a few cases where we did not need to include <asm/global_data.h> at all, so remove that include. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Rini <trini@konsulko.com> |
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
691d719d |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop init.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
30c7c434 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move checkcpu() out of common.h This function belongs in cpu_func.h so move it over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com> |
#
a827ba91 |
|
31-Aug-2019 |
Simon Glass <sjg@chromium.org> |
x86: pci: Drop the first parameter in pci_x86_r/w_config() This parameter is needed by the PCI driver-mode interface but is always NULL on x86. There are a number of calls to this function so it makes sense to minimise the parameters. Adjust the x86 function to omit the first parameter, and introduce stub functions to handle the conversion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/next to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com> |
#
83d290c5 |
|
06-May-2018 |
Tom Rini <trini@konsulko.com> |
SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com> |
#
76d1d02f |
|
28-Mar-2017 |
Simon Glass <sjg@chromium.org> |
board_f: x86: Use checkcpu() for CPU init At present we misuse print_cpuinfo() do so CPU init on x86. This is done because it is the next available call after the console is enabled. But several arches use checkcpu() instead. Despite the horrible name (which we can fix), it seems a better choice. Adjust the various x86 CPU implementations to move their init code into checkcpu() and use print_cpuinfo() only for printing CPU info. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Stefan Roese <sr@denx.de> |
#
8d8f3acd |
|
16-Jan-2017 |
Simon Glass <sjg@chromium.org> |
x86: ivybridge: Add more debugging for failures Add various debug() messages in places where errors occur. This aids with debugging. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
4cc00f06 |
|
25-Jul-2016 |
Simon Glass <sjg@chromium.org> |
x86: Add debugging when cpu_common_init() fails Add a debug() at this point to help figure out what is wrong. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
7e4a6ae6 |
|
16-Mar-2016 |
Simon Glass <sjg@chromium.org> |
x86: Move common PCH code into a common place The SATA indexed register write functions are common to several Intel PCHs. Move this into a common location. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
50dd3da0 |
|
11-Mar-2016 |
Simon Glass <sjg@chromium.org> |
x86: Move common CPU code to its own place Some of the Intel CPU code is common to several Intel CPUs. Move it into a common location along with required declarations. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
06d336cc |
|
11-Mar-2016 |
Simon Glass <sjg@chromium.org> |
x86: Create a common header for Intel register access There are several blocks of registers that are accessed from all over the code on Intel CPUs. These don't currently have their own driver and it is not clear whether having a driver makes sense. An example is the Memory Controller Hub (MCH). We map it to a known location on some Intel chips (mostly those without FSP - Firmware Support Package). Add a new header file for these registers, and move MCH into it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
9e66506d |
|
11-Mar-2016 |
Simon Glass <sjg@chromium.org> |
x86: Move microcode code to a common location This code is used on several Intel CPUs. Move it into a common location. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
3f603cbb |
|
11-Feb-2016 |
Simon Glass <sjg@chromium.org> |
dm: Use uclass_first_device_err() where it is useful Use this new function in places where it simplifies the code. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
5213f280 |
|
17-Jan-2016 |
Simon Glass <sjg@chromium.org> |
x86: ivybridge: Convert enable_usb_bar() to use DM PCI API Convert this function over to use the driver model PCI API. In this case we want to avoid using the real PCI devices since they have not yet been probed. Instead, write directly to their PCI configuration address. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
0c7645bd |
|
17-Jan-2016 |
Simon Glass <sjg@chromium.org> |
x86: ivybridge: Use the I2C driver to perform SMbus init Move the init code into the I2C driver. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Heiko Schocher <hs@denx.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
d46f2a68 |
|
17-Jan-2016 |
Simon Glass <sjg@chromium.org> |
x86: ivybridge: Do the SATA init before relocation The SATA device needs to set itself up so that it appears correctly on the PCI bus. The easiest way to do this is to set it up to probe before relocation. This can do the early setup. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
9fd11c7a |
|
17-Jan-2016 |
Simon Glass <sjg@chromium.org> |
x86: ivybridge: Move GPIO init to the LPC init() method This init can happen in the driver also. Move it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
17e0a9ab |
|
17-Jan-2016 |
Simon Glass <sjg@chromium.org> |
x86: ivybridge: Move graphics init much later We don't need to init the graphics controller so early. Move it alongside the other graphics setup, just before we run the ROM. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
f633efa3 |
|
17-Jan-2016 |
Simon Glass <sjg@chromium.org> |
x86: ivybridge: Probe the LPC in CPU init We can drop the explicit probe of the PCH since the LPC is a child device and this will happen automatically. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
655925a9 |
|
17-Jan-2016 |
Simon Glass <sjg@chromium.org> |
x86: ivybridge: Move northbridge init into the probe() method Now that we have a proper driver for the nortbridge, set it up in by probing it, and move the early init code into the probe() method. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
858361b1 |
|
17-Jan-2016 |
Simon Glass <sjg@chromium.org> |
x86: ivybridge: Rename bd82x6x_init() Rename the existing bd82x6x_init() to bd82x6x_init_extra(). We will remove this in a later patch. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
fe40bd4d |
|
17-Jan-2016 |
Simon Glass <sjg@chromium.org> |
x86: ivybridge: Move more init to the probe() function Move SPI and port80 init to lpc_early_init(), called from the LPC's probe() method. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
788cd908 |
|
17-Jan-2016 |
Simon Glass <sjg@chromium.org> |
x86: ivybridge: Move lpc_early_init() to probe() Move this code to the LPC's probe() method so that it will happen automatically when the LPC is probed before relocation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
4acc83d4 |
|
17-Jan-2016 |
Simon Glass <sjg@chromium.org> |
x86: ivybridge: Set up the LPC device using driver model Find the LPC device in arch_cpu_init_dm() as a first step to converting this code to use driver model. Probing the LPC will probe its parent (the PCH) automatically, so make sure that probing the PCH does nothing before relocation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
789fa275 |
|
25-Nov-2015 |
Bin Meng <bmeng.cn@gmail.com> |
x86: Remove HAVE_ACPI_RESUME These are currently dead codes. Until we have complete ACPI support, we don't know if it works or not. Remove to avoid confusion. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> |
#
80af3984 |
|
13-Nov-2015 |
Bin Meng <bmeng.cn@gmail.com> |
x86: Convert to use driver model timer Convert all x86 boards to use driver model tsc timer. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> |
#
7b95252d |
|
18-Oct-2015 |
Simon Glass <sjg@chromium.org> |
x86: chromebook_link: Enable the debug UART Add support for the debug UART on link. This is useful for early debugging. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
5021c81f |
|
28-Apr-2015 |
Simon Glass <sjg@chromium.org> |
x86: ivybridge: Use reset_cpu() Now that reset_cpu() functions correctly, use it instead of directly accessing the port. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
90b16d14 |
|
26-Mar-2015 |
Simon Glass <sjg@chromium.org> |
x86: chromebook_link: dts: Add PCH and LPC devices The PCH (Platform Controller Hub) is on the PCI bus, so show it as such. The LPC (Low Pin Count) and SPI bus are inside the PCH, so put these in the right place also. Rename the compatible strings to be more descriptive since this board is the only user. Once we are using driver model fully on x86, these will be dropped. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
aad78d27 |
|
05-Mar-2015 |
Simon Glass <sjg@chromium.org> |
dm: x86: pci: Convert chromebook_link to use driver model for pci Move chromebook_link over to driver model for PCI. This involves: - adding a uclass for platform controller hub - removing most of the existing PCI driver - adjusting how CPU init works to use driver model instead - rename the lpc compatible string (it will be removed later) This does not really take advantage of driver model fully, but it does work. Furture work will improve the code structure to remove many of the explicit calls to init the board. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
161d2e4e |
|
05-Mar-2015 |
Simon Glass <sjg@chromium.org> |
x86: Split up arch_cpu_init() At present we do more in this function than we should. Split out the post-driver-model part into a separate function. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
31f57c28 |
|
05-Mar-2015 |
Simon Glass <sjg@chromium.org> |
x86: Add a x86_ prefix to the x86-specific PCI functions These functions currently use a generic name, but they are for x86 only. This may introduce confusion and prevents U-Boot from using these names more widely. In fact it should be possible to remove these at some point and use generic functions, but for now, rename them. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
c72f74e2 |
|
01-Jan-2015 |
Simon Glass <sjg@chromium.org> |
x86: ivybridge: Update microcode early in boot At present the normal update (which happens much later) does not work. This seems to have something to do with the 'no eviction' mode in the CAR, or at least moving the microcode update after that causes it not to work. For now, do an update early on so that it definitely works. Also refuse to continue unless the microcode update check (later in boot) is successful. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
3a5659f7 |
|
01-Jan-2015 |
Simon Glass <sjg@chromium.org> |
x86: ivybridge: Drop support for ROM caching This is set up along with CAR (Cache-as-RAM) anyway. When we relocate we don't really need ROM caching (we read the VGA BIOS from ROM but that is about it) Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
95a5a474 |
|
12-Dec-2014 |
Bin Meng <bmeng.cn@gmail.com> |
x86: Add post failure codes for bist and car Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> |
#
3eafce05 |
|
12-Nov-2014 |
Simon Glass <sjg@chromium.org> |
x86: ivybridge: Add LAPIC support The local advanced programmable interrupt controller is not used much in U-Boot but we do need to set it up. Add basic support for this, which will be extended as needed. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
8e0df066 |
|
12-Nov-2014 |
Simon Glass <sjg@chromium.org> |
x86: ivybridge: Add early init for PCH devices Many PCH devices are hard-coded to a particular PCI address. Set these up early in case they are needed. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
77f9b1fb |
|
12-Nov-2014 |
Simon Glass <sjg@chromium.org> |
x86: ivybridge: Perform Intel microcode update on boot Microcode updates are stored in the device tree. Work through these and apply any that are needed. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
94060ff2 |
|
12-Nov-2014 |
Simon Glass <sjg@chromium.org> |
x86: ivybridge: Check BIST value on boot The built-in self test value should be checked before we continue booting. Refuse to continue if there is something wrong. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
f5fbbe95 |
|
12-Nov-2014 |
Simon Glass <sjg@chromium.org> |
x86: ivybridge: Perform initial CPU setup Set up the flex ratio (controls speed versus heat output) and a few other very early things. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
2b605154 |
|
12-Nov-2014 |
Simon Glass <sjg@chromium.org> |
x86: ivybridge: Add early LPC init so that serial works The PCH (Platform Controller Hub) includes an LPC (Low Pin Count) device which provides a serial port. This is accessible on Chromebooks, so enable it early in the boot process. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
6e5b12b6 |
|
12-Nov-2014 |
Simon Glass <sjg@chromium.org> |
x86: ivybridge: Enable PCI in early init Enable PCI so we can access devices that need to be set up before relocation. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
70a09c6c |
|
12-Nov-2014 |
Simon Glass <sjg@chromium.org> |
x86: chromebook_link: Implement CAR support (cache as RAM) Add support for CAR so that we have memory to use prior to DRAM init. On link there is a total of 128KB of CAR available, although some is used for the memory reference code. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
8ef07571 |
|
12-Nov-2014 |
Simon Glass <sjg@chromium.org> |
x86: Add chromebook_link board This board is a 'bare' version of the existing 'link 'board. It does not require coreboot to run, but is intended to start directly from the reset vector. This initial commit has place holders for a wide range of features. These will be added in follow-on patches and series. So far it cannot be booted as there is no ROM image produced, but it does build without errors. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
691d719d |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop init.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
30c7c434 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move checkcpu() out of common.h This function belongs in cpu_func.h so move it over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com> |
#
a827ba91 |
|
31-Aug-2019 |
Simon Glass <sjg@chromium.org> |
x86: pci: Drop the first parameter in pci_x86_r/w_config() This parameter is needed by the PCI driver-mode interface but is always NULL on x86. There are a number of calls to this function so it makes sense to minimise the parameters. Adjust the x86 function to omit the first parameter, and introduce stub functions to handle the conversion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/next to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com> |
#
83d290c5 |
|
06-May-2018 |
Tom Rini <trini@konsulko.com> |
SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com> |
#
76d1d02f |
|
28-Mar-2017 |
Simon Glass <sjg@chromium.org> |
board_f: x86: Use checkcpu() for CPU init At present we misuse print_cpuinfo() do so CPU init on x86. This is done because it is the next available call after the console is enabled. But several arches use checkcpu() instead. Despite the horrible name (which we can fix), it seems a better choice. Adjust the various x86 CPU implementations to move their init code into checkcpu() and use print_cpuinfo() only for printing CPU info. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Stefan Roese <sr@denx.de> |
#
8d8f3acd |
|
16-Jan-2017 |
Simon Glass <sjg@chromium.org> |
x86: ivybridge: Add more debugging for failures Add various debug() messages in places where errors occur. This aids with debugging. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
4cc00f06 |
|
25-Jul-2016 |
Simon Glass <sjg@chromium.org> |
x86: Add debugging when cpu_common_init() fails Add a debug() at this point to help figure out what is wrong. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
7e4a6ae6 |
|
16-Mar-2016 |
Simon Glass <sjg@chromium.org> |
x86: Move common PCH code into a common place The SATA indexed register write functions are common to several Intel PCHs. Move this into a common location. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
50dd3da0 |
|
11-Mar-2016 |
Simon Glass <sjg@chromium.org> |
x86: Move common CPU code to its own place Some of the Intel CPU code is common to several Intel CPUs. Move it into a common location along with required declarations. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
06d336cc |
|
11-Mar-2016 |
Simon Glass <sjg@chromium.org> |
x86: Create a common header for Intel register access There are several blocks of registers that are accessed from all over the code on Intel CPUs. These don't currently have their own driver and it is not clear whether having a driver makes sense. An example is the Memory Controller Hub (MCH). We map it to a known location on some Intel chips (mostly those without FSP - Firmware Support Package). Add a new header file for these registers, and move MCH into it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
9e66506d |
|
11-Mar-2016 |
Simon Glass <sjg@chromium.org> |
x86: Move microcode code to a common location This code is used on several Intel CPUs. Move it into a common location. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
3f603cbb |
|
11-Feb-2016 |
Simon Glass <sjg@chromium.org> |
dm: Use uclass_first_device_err() where it is useful Use this new function in places where it simplifies the code. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
5213f280 |
|
17-Jan-2016 |
Simon Glass <sjg@chromium.org> |
x86: ivybridge: Convert enable_usb_bar() to use DM PCI API Convert this function over to use the driver model PCI API. In this case we want to avoid using the real PCI devices since they have not yet been probed. Instead, write directly to their PCI configuration address. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
0c7645bd |
|
17-Jan-2016 |
Simon Glass <sjg@chromium.org> |
x86: ivybridge: Use the I2C driver to perform SMbus init Move the init code into the I2C driver. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Heiko Schocher <hs@denx.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
d46f2a68 |
|
17-Jan-2016 |
Simon Glass <sjg@chromium.org> |
x86: ivybridge: Do the SATA init before relocation The SATA device needs to set itself up so that it appears correctly on the PCI bus. The easiest way to do this is to set it up to probe before relocation. This can do the early setup. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
9fd11c7a |
|
17-Jan-2016 |
Simon Glass <sjg@chromium.org> |
x86: ivybridge: Move GPIO init to the LPC init() method This init can happen in the driver also. Move it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
17e0a9ab |
|
17-Jan-2016 |
Simon Glass <sjg@chromium.org> |
x86: ivybridge: Move graphics init much later We don't need to init the graphics controller so early. Move it alongside the other graphics setup, just before we run the ROM. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
f633efa3 |
|
17-Jan-2016 |
Simon Glass <sjg@chromium.org> |
x86: ivybridge: Probe the LPC in CPU init We can drop the explicit probe of the PCH since the LPC is a child device and this will happen automatically. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
655925a9 |
|
17-Jan-2016 |
Simon Glass <sjg@chromium.org> |
x86: ivybridge: Move northbridge init into the probe() method Now that we have a proper driver for the nortbridge, set it up in by probing it, and move the early init code into the probe() method. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
858361b1 |
|
17-Jan-2016 |
Simon Glass <sjg@chromium.org> |
x86: ivybridge: Rename bd82x6x_init() Rename the existing bd82x6x_init() to bd82x6x_init_extra(). We will remove this in a later patch. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
fe40bd4d |
|
17-Jan-2016 |
Simon Glass <sjg@chromium.org> |
x86: ivybridge: Move more init to the probe() function Move SPI and port80 init to lpc_early_init(), called from the LPC's probe() method. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
788cd908 |
|
17-Jan-2016 |
Simon Glass <sjg@chromium.org> |
x86: ivybridge: Move lpc_early_init() to probe() Move this code to the LPC's probe() method so that it will happen automatically when the LPC is probed before relocation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
4acc83d4 |
|
17-Jan-2016 |
Simon Glass <sjg@chromium.org> |
x86: ivybridge: Set up the LPC device using driver model Find the LPC device in arch_cpu_init_dm() as a first step to converting this code to use driver model. Probing the LPC will probe its parent (the PCH) automatically, so make sure that probing the PCH does nothing before relocation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
789fa275 |
|
25-Nov-2015 |
Bin Meng <bmeng.cn@gmail.com> |
x86: Remove HAVE_ACPI_RESUME These are currently dead codes. Until we have complete ACPI support, we don't know if it works or not. Remove to avoid confusion. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> |
#
80af3984 |
|
13-Nov-2015 |
Bin Meng <bmeng.cn@gmail.com> |
x86: Convert to use driver model timer Convert all x86 boards to use driver model tsc timer. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> |
#
7b95252d |
|
18-Oct-2015 |
Simon Glass <sjg@chromium.org> |
x86: chromebook_link: Enable the debug UART Add support for the debug UART on link. This is useful for early debugging. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
5021c81f |
|
28-Apr-2015 |
Simon Glass <sjg@chromium.org> |
x86: ivybridge: Use reset_cpu() Now that reset_cpu() functions correctly, use it instead of directly accessing the port. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
90b16d14 |
|
26-Mar-2015 |
Simon Glass <sjg@chromium.org> |
x86: chromebook_link: dts: Add PCH and LPC devices The PCH (Platform Controller Hub) is on the PCI bus, so show it as such. The LPC (Low Pin Count) and SPI bus are inside the PCH, so put these in the right place also. Rename the compatible strings to be more descriptive since this board is the only user. Once we are using driver model fully on x86, these will be dropped. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
aad78d27 |
|
05-Mar-2015 |
Simon Glass <sjg@chromium.org> |
dm: x86: pci: Convert chromebook_link to use driver model for pci Move chromebook_link over to driver model for PCI. This involves: - adding a uclass for platform controller hub - removing most of the existing PCI driver - adjusting how CPU init works to use driver model instead - rename the lpc compatible string (it will be removed later) This does not really take advantage of driver model fully, but it does work. Furture work will improve the code structure to remove many of the explicit calls to init the board. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
161d2e4e |
|
05-Mar-2015 |
Simon Glass <sjg@chromium.org> |
x86: Split up arch_cpu_init() At present we do more in this function than we should. Split out the post-driver-model part into a separate function. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
31f57c28 |
|
05-Mar-2015 |
Simon Glass <sjg@chromium.org> |
x86: Add a x86_ prefix to the x86-specific PCI functions These functions currently use a generic name, but they are for x86 only. This may introduce confusion and prevents U-Boot from using these names more widely. In fact it should be possible to remove these at some point and use generic functions, but for now, rename them. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
c72f74e2 |
|
01-Jan-2015 |
Simon Glass <sjg@chromium.org> |
x86: ivybridge: Update microcode early in boot At present the normal update (which happens much later) does not work. This seems to have something to do with the 'no eviction' mode in the CAR, or at least moving the microcode update after that causes it not to work. For now, do an update early on so that it definitely works. Also refuse to continue unless the microcode update check (later in boot) is successful. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
3a5659f7 |
|
01-Jan-2015 |
Simon Glass <sjg@chromium.org> |
x86: ivybridge: Drop support for ROM caching This is set up along with CAR (Cache-as-RAM) anyway. When we relocate we don't really need ROM caching (we read the VGA BIOS from ROM but that is about it) Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
95a5a474 |
|
12-Dec-2014 |
Bin Meng <bmeng.cn@gmail.com> |
x86: Add post failure codes for bist and car Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> |
#
3eafce05 |
|
12-Nov-2014 |
Simon Glass <sjg@chromium.org> |
x86: ivybridge: Add LAPIC support The local advanced programmable interrupt controller is not used much in U-Boot but we do need to set it up. Add basic support for this, which will be extended as needed. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
8e0df066 |
|
12-Nov-2014 |
Simon Glass <sjg@chromium.org> |
x86: ivybridge: Add early init for PCH devices Many PCH devices are hard-coded to a particular PCI address. Set these up early in case they are needed. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
77f9b1fb |
|
12-Nov-2014 |
Simon Glass <sjg@chromium.org> |
x86: ivybridge: Perform Intel microcode update on boot Microcode updates are stored in the device tree. Work through these and apply any that are needed. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
94060ff2 |
|
12-Nov-2014 |
Simon Glass <sjg@chromium.org> |
x86: ivybridge: Check BIST value on boot The built-in self test value should be checked before we continue booting. Refuse to continue if there is something wrong. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
f5fbbe95 |
|
12-Nov-2014 |
Simon Glass <sjg@chromium.org> |
x86: ivybridge: Perform initial CPU setup Set up the flex ratio (controls speed versus heat output) and a few other very early things. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
2b605154 |
|
12-Nov-2014 |
Simon Glass <sjg@chromium.org> |
x86: ivybridge: Add early LPC init so that serial works The PCH (Platform Controller Hub) includes an LPC (Low Pin Count) device which provides a serial port. This is accessible on Chromebooks, so enable it early in the boot process. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
6e5b12b6 |
|
12-Nov-2014 |
Simon Glass <sjg@chromium.org> |
x86: ivybridge: Enable PCI in early init Enable PCI so we can access devices that need to be set up before relocation. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
70a09c6c |
|
12-Nov-2014 |
Simon Glass <sjg@chromium.org> |
x86: chromebook_link: Implement CAR support (cache as RAM) Add support for CAR so that we have memory to use prior to DRAM init. On link there is a total of 128KB of CAR available, although some is used for the memory reference code. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
8ef07571 |
|
12-Nov-2014 |
Simon Glass <sjg@chromium.org> |
x86: Add chromebook_link board This board is a 'bare' version of the existing 'link 'board. It does not require coreboot to run, but is intended to start directly from the reset vector. This initial commit has place holders for a wide range of features. These will be added in follow-on patches and series. So far it cannot be booted as there is no ROM image produced, but it does build without errors. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
30c7c434 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move checkcpu() out of common.h This function belongs in cpu_func.h so move it over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com> |
#
a827ba91 |
|
31-Aug-2019 |
Simon Glass <sjg@chromium.org> |
x86: pci: Drop the first parameter in pci_x86_r/w_config() This parameter is needed by the PCI driver-mode interface but is always NULL on x86. There are a number of calls to this function so it makes sense to minimise the parameters. Adjust the x86 function to omit the first parameter, and introduce stub functions to handle the conversion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/next to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com> |
#
83d290c5 |
|
06-May-2018 |
Tom Rini <trini@konsulko.com> |
SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com> |
#
76d1d02f |
|
28-Mar-2017 |
Simon Glass <sjg@chromium.org> |
board_f: x86: Use checkcpu() for CPU init At present we misuse print_cpuinfo() do so CPU init on x86. This is done because it is the next available call after the console is enabled. But several arches use checkcpu() instead. Despite the horrible name (which we can fix), it seems a better choice. Adjust the various x86 CPU implementations to move their init code into checkcpu() and use print_cpuinfo() only for printing CPU info. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Stefan Roese <sr@denx.de> |
#
8d8f3acd |
|
16-Jan-2017 |
Simon Glass <sjg@chromium.org> |
x86: ivybridge: Add more debugging for failures Add various debug() messages in places where errors occur. This aids with debugging. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
4cc00f06 |
|
25-Jul-2016 |
Simon Glass <sjg@chromium.org> |
x86: Add debugging when cpu_common_init() fails Add a debug() at this point to help figure out what is wrong. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
7e4a6ae6 |
|
16-Mar-2016 |
Simon Glass <sjg@chromium.org> |
x86: Move common PCH code into a common place The SATA indexed register write functions are common to several Intel PCHs. Move this into a common location. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
50dd3da0 |
|
11-Mar-2016 |
Simon Glass <sjg@chromium.org> |
x86: Move common CPU code to its own place Some of the Intel CPU code is common to several Intel CPUs. Move it into a common location along with required declarations. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
06d336cc |
|
11-Mar-2016 |
Simon Glass <sjg@chromium.org> |
x86: Create a common header for Intel register access There are several blocks of registers that are accessed from all over the code on Intel CPUs. These don't currently have their own driver and it is not clear whether having a driver makes sense. An example is the Memory Controller Hub (MCH). We map it to a known location on some Intel chips (mostly those without FSP - Firmware Support Package). Add a new header file for these registers, and move MCH into it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
9e66506d |
|
11-Mar-2016 |
Simon Glass <sjg@chromium.org> |
x86: Move microcode code to a common location This code is used on several Intel CPUs. Move it into a common location. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
3f603cbb |
|
11-Feb-2016 |
Simon Glass <sjg@chromium.org> |
dm: Use uclass_first_device_err() where it is useful Use this new function in places where it simplifies the code. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
5213f280 |
|
17-Jan-2016 |
Simon Glass <sjg@chromium.org> |
x86: ivybridge: Convert enable_usb_bar() to use DM PCI API Convert this function over to use the driver model PCI API. In this case we want to avoid using the real PCI devices since they have not yet been probed. Instead, write directly to their PCI configuration address. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
0c7645bd |
|
17-Jan-2016 |
Simon Glass <sjg@chromium.org> |
x86: ivybridge: Use the I2C driver to perform SMbus init Move the init code into the I2C driver. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Heiko Schocher <hs@denx.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
d46f2a68 |
|
17-Jan-2016 |
Simon Glass <sjg@chromium.org> |
x86: ivybridge: Do the SATA init before relocation The SATA device needs to set itself up so that it appears correctly on the PCI bus. The easiest way to do this is to set it up to probe before relocation. This can do the early setup. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
9fd11c7a |
|
17-Jan-2016 |
Simon Glass <sjg@chromium.org> |
x86: ivybridge: Move GPIO init to the LPC init() method This init can happen in the driver also. Move it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
17e0a9ab |
|
17-Jan-2016 |
Simon Glass <sjg@chromium.org> |
x86: ivybridge: Move graphics init much later We don't need to init the graphics controller so early. Move it alongside the other graphics setup, just before we run the ROM. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
f633efa3 |
|
17-Jan-2016 |
Simon Glass <sjg@chromium.org> |
x86: ivybridge: Probe the LPC in CPU init We can drop the explicit probe of the PCH since the LPC is a child device and this will happen automatically. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
655925a9 |
|
17-Jan-2016 |
Simon Glass <sjg@chromium.org> |
x86: ivybridge: Move northbridge init into the probe() method Now that we have a proper driver for the nortbridge, set it up in by probing it, and move the early init code into the probe() method. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
858361b1 |
|
17-Jan-2016 |
Simon Glass <sjg@chromium.org> |
x86: ivybridge: Rename bd82x6x_init() Rename the existing bd82x6x_init() to bd82x6x_init_extra(). We will remove this in a later patch. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
fe40bd4d |
|
17-Jan-2016 |
Simon Glass <sjg@chromium.org> |
x86: ivybridge: Move more init to the probe() function Move SPI and port80 init to lpc_early_init(), called from the LPC's probe() method. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
788cd908 |
|
17-Jan-2016 |
Simon Glass <sjg@chromium.org> |
x86: ivybridge: Move lpc_early_init() to probe() Move this code to the LPC's probe() method so that it will happen automatically when the LPC is probed before relocation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
4acc83d4 |
|
17-Jan-2016 |
Simon Glass <sjg@chromium.org> |
x86: ivybridge: Set up the LPC device using driver model Find the LPC device in arch_cpu_init_dm() as a first step to converting this code to use driver model. Probing the LPC will probe its parent (the PCH) automatically, so make sure that probing the PCH does nothing before relocation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
789fa275 |
|
25-Nov-2015 |
Bin Meng <bmeng.cn@gmail.com> |
x86: Remove HAVE_ACPI_RESUME These are currently dead codes. Until we have complete ACPI support, we don't know if it works or not. Remove to avoid confusion. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> |
#
80af3984 |
|
13-Nov-2015 |
Bin Meng <bmeng.cn@gmail.com> |
x86: Convert to use driver model timer Convert all x86 boards to use driver model tsc timer. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> |
#
7b95252d |
|
18-Oct-2015 |
Simon Glass <sjg@chromium.org> |
x86: chromebook_link: Enable the debug UART Add support for the debug UART on link. This is useful for early debugging. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
5021c81f |
|
28-Apr-2015 |
Simon Glass <sjg@chromium.org> |
x86: ivybridge: Use reset_cpu() Now that reset_cpu() functions correctly, use it instead of directly accessing the port. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
90b16d14 |
|
26-Mar-2015 |
Simon Glass <sjg@chromium.org> |
x86: chromebook_link: dts: Add PCH and LPC devices The PCH (Platform Controller Hub) is on the PCI bus, so show it as such. The LPC (Low Pin Count) and SPI bus are inside the PCH, so put these in the right place also. Rename the compatible strings to be more descriptive since this board is the only user. Once we are using driver model fully on x86, these will be dropped. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
aad78d27 |
|
05-Mar-2015 |
Simon Glass <sjg@chromium.org> |
dm: x86: pci: Convert chromebook_link to use driver model for pci Move chromebook_link over to driver model for PCI. This involves: - adding a uclass for platform controller hub - removing most of the existing PCI driver - adjusting how CPU init works to use driver model instead - rename the lpc compatible string (it will be removed later) This does not really take advantage of driver model fully, but it does work. Furture work will improve the code structure to remove many of the explicit calls to init the board. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
161d2e4e |
|
05-Mar-2015 |
Simon Glass <sjg@chromium.org> |
x86: Split up arch_cpu_init() At present we do more in this function than we should. Split out the post-driver-model part into a separate function. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
31f57c28 |
|
05-Mar-2015 |
Simon Glass <sjg@chromium.org> |
x86: Add a x86_ prefix to the x86-specific PCI functions These functions currently use a generic name, but they are for x86 only. This may introduce confusion and prevents U-Boot from using these names more widely. In fact it should be possible to remove these at some point and use generic functions, but for now, rename them. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
c72f74e2 |
|
01-Jan-2015 |
Simon Glass <sjg@chromium.org> |
x86: ivybridge: Update microcode early in boot At present the normal update (which happens much later) does not work. This seems to have something to do with the 'no eviction' mode in the CAR, or at least moving the microcode update after that causes it not to work. For now, do an update early on so that it definitely works. Also refuse to continue unless the microcode update check (later in boot) is successful. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
3a5659f7 |
|
01-Jan-2015 |
Simon Glass <sjg@chromium.org> |
x86: ivybridge: Drop support for ROM caching This is set up along with CAR (Cache-as-RAM) anyway. When we relocate we don't really need ROM caching (we read the VGA BIOS from ROM but that is about it) Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
95a5a474 |
|
12-Dec-2014 |
Bin Meng <bmeng.cn@gmail.com> |
x86: Add post failure codes for bist and car Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> |
#
3eafce05 |
|
12-Nov-2014 |
Simon Glass <sjg@chromium.org> |
x86: ivybridge: Add LAPIC support The local advanced programmable interrupt controller is not used much in U-Boot but we do need to set it up. Add basic support for this, which will be extended as needed. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
8e0df066 |
|
12-Nov-2014 |
Simon Glass <sjg@chromium.org> |
x86: ivybridge: Add early init for PCH devices Many PCH devices are hard-coded to a particular PCI address. Set these up early in case they are needed. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
77f9b1fb |
|
12-Nov-2014 |
Simon Glass <sjg@chromium.org> |
x86: ivybridge: Perform Intel microcode update on boot Microcode updates are stored in the device tree. Work through these and apply any that are needed. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
94060ff2 |
|
12-Nov-2014 |
Simon Glass <sjg@chromium.org> |
x86: ivybridge: Check BIST value on boot The built-in self test value should be checked before we continue booting. Refuse to continue if there is something wrong. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
f5fbbe95 |
|
12-Nov-2014 |
Simon Glass <sjg@chromium.org> |
x86: ivybridge: Perform initial CPU setup Set up the flex ratio (controls speed versus heat output) and a few other very early things. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
2b605154 |
|
12-Nov-2014 |
Simon Glass <sjg@chromium.org> |
x86: ivybridge: Add early LPC init so that serial works The PCH (Platform Controller Hub) includes an LPC (Low Pin Count) device which provides a serial port. This is accessible on Chromebooks, so enable it early in the boot process. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
6e5b12b6 |
|
12-Nov-2014 |
Simon Glass <sjg@chromium.org> |
x86: ivybridge: Enable PCI in early init Enable PCI so we can access devices that need to be set up before relocation. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
70a09c6c |
|
12-Nov-2014 |
Simon Glass <sjg@chromium.org> |
x86: chromebook_link: Implement CAR support (cache as RAM) Add support for CAR so that we have memory to use prior to DRAM init. On link there is a total of 128KB of CAR available, although some is used for the memory reference code. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
8ef07571 |
|
12-Nov-2014 |
Simon Glass <sjg@chromium.org> |
x86: Add chromebook_link board This board is a 'bare' version of the existing 'link 'board. It does not require coreboot to run, but is intended to start directly from the reset vector. This initial commit has place holders for a wide range of features. These will be added in follow-on patches and series. So far it cannot be booted as there is no ROM image produced, but it does build without errors. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
a827ba91 |
|
31-Aug-2019 |
Simon Glass <sjg@chromium.org> |
x86: pci: Drop the first parameter in pci_x86_r/w_config() This parameter is needed by the PCI driver-mode interface but is always NULL on x86. There are a number of calls to this function so it makes sense to minimise the parameters. Adjust the x86 function to omit the first parameter, and introduce stub functions to handle the conversion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/next to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com> |
#
83d290c5 |
|
06-May-2018 |
Tom Rini <trini@konsulko.com> |
SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com> |
#
76d1d02f |
|
28-Mar-2017 |
Simon Glass <sjg@chromium.org> |
board_f: x86: Use checkcpu() for CPU init At present we misuse print_cpuinfo() do so CPU init on x86. This is done because it is the next available call after the console is enabled. But several arches use checkcpu() instead. Despite the horrible name (which we can fix), it seems a better choice. Adjust the various x86 CPU implementations to move their init code into checkcpu() and use print_cpuinfo() only for printing CPU info. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Stefan Roese <sr@denx.de> |
#
8d8f3acd |
|
16-Jan-2017 |
Simon Glass <sjg@chromium.org> |
x86: ivybridge: Add more debugging for failures Add various debug() messages in places where errors occur. This aids with debugging. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
4cc00f06 |
|
25-Jul-2016 |
Simon Glass <sjg@chromium.org> |
x86: Add debugging when cpu_common_init() fails Add a debug() at this point to help figure out what is wrong. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
7e4a6ae6 |
|
16-Mar-2016 |
Simon Glass <sjg@chromium.org> |
x86: Move common PCH code into a common place The SATA indexed register write functions are common to several Intel PCHs. Move this into a common location. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
50dd3da0 |
|
11-Mar-2016 |
Simon Glass <sjg@chromium.org> |
x86: Move common CPU code to its own place Some of the Intel CPU code is common to several Intel CPUs. Move it into a common location along with required declarations. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
06d336cc |
|
11-Mar-2016 |
Simon Glass <sjg@chromium.org> |
x86: Create a common header for Intel register access There are several blocks of registers that are accessed from all over the code on Intel CPUs. These don't currently have their own driver and it is not clear whether having a driver makes sense. An example is the Memory Controller Hub (MCH). We map it to a known location on some Intel chips (mostly those without FSP - Firmware Support Package). Add a new header file for these registers, and move MCH into it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
9e66506d |
|
11-Mar-2016 |
Simon Glass <sjg@chromium.org> |
x86: Move microcode code to a common location This code is used on several Intel CPUs. Move it into a common location. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
3f603cbb |
|
11-Feb-2016 |
Simon Glass <sjg@chromium.org> |
dm: Use uclass_first_device_err() where it is useful Use this new function in places where it simplifies the code. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
5213f280 |
|
17-Jan-2016 |
Simon Glass <sjg@chromium.org> |
x86: ivybridge: Convert enable_usb_bar() to use DM PCI API Convert this function over to use the driver model PCI API. In this case we want to avoid using the real PCI devices since they have not yet been probed. Instead, write directly to their PCI configuration address. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
0c7645bd |
|
17-Jan-2016 |
Simon Glass <sjg@chromium.org> |
x86: ivybridge: Use the I2C driver to perform SMbus init Move the init code into the I2C driver. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Heiko Schocher <hs@denx.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
d46f2a68 |
|
17-Jan-2016 |
Simon Glass <sjg@chromium.org> |
x86: ivybridge: Do the SATA init before relocation The SATA device needs to set itself up so that it appears correctly on the PCI bus. The easiest way to do this is to set it up to probe before relocation. This can do the early setup. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
9fd11c7a |
|
17-Jan-2016 |
Simon Glass <sjg@chromium.org> |
x86: ivybridge: Move GPIO init to the LPC init() method This init can happen in the driver also. Move it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
17e0a9ab |
|
17-Jan-2016 |
Simon Glass <sjg@chromium.org> |
x86: ivybridge: Move graphics init much later We don't need to init the graphics controller so early. Move it alongside the other graphics setup, just before we run the ROM. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
f633efa3 |
|
17-Jan-2016 |
Simon Glass <sjg@chromium.org> |
x86: ivybridge: Probe the LPC in CPU init We can drop the explicit probe of the PCH since the LPC is a child device and this will happen automatically. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
655925a9 |
|
17-Jan-2016 |
Simon Glass <sjg@chromium.org> |
x86: ivybridge: Move northbridge init into the probe() method Now that we have a proper driver for the nortbridge, set it up in by probing it, and move the early init code into the probe() method. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
858361b1 |
|
17-Jan-2016 |
Simon Glass <sjg@chromium.org> |
x86: ivybridge: Rename bd82x6x_init() Rename the existing bd82x6x_init() to bd82x6x_init_extra(). We will remove this in a later patch. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
fe40bd4d |
|
17-Jan-2016 |
Simon Glass <sjg@chromium.org> |
x86: ivybridge: Move more init to the probe() function Move SPI and port80 init to lpc_early_init(), called from the LPC's probe() method. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
788cd908 |
|
17-Jan-2016 |
Simon Glass <sjg@chromium.org> |
x86: ivybridge: Move lpc_early_init() to probe() Move this code to the LPC's probe() method so that it will happen automatically when the LPC is probed before relocation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
4acc83d4 |
|
17-Jan-2016 |
Simon Glass <sjg@chromium.org> |
x86: ivybridge: Set up the LPC device using driver model Find the LPC device in arch_cpu_init_dm() as a first step to converting this code to use driver model. Probing the LPC will probe its parent (the PCH) automatically, so make sure that probing the PCH does nothing before relocation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
789fa275 |
|
25-Nov-2015 |
Bin Meng <bmeng.cn@gmail.com> |
x86: Remove HAVE_ACPI_RESUME These are currently dead codes. Until we have complete ACPI support, we don't know if it works or not. Remove to avoid confusion. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> |
#
80af3984 |
|
13-Nov-2015 |
Bin Meng <bmeng.cn@gmail.com> |
x86: Convert to use driver model timer Convert all x86 boards to use driver model tsc timer. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> |
#
7b95252d |
|
18-Oct-2015 |
Simon Glass <sjg@chromium.org> |
x86: chromebook_link: Enable the debug UART Add support for the debug UART on link. This is useful for early debugging. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
5021c81f |
|
28-Apr-2015 |
Simon Glass <sjg@chromium.org> |
x86: ivybridge: Use reset_cpu() Now that reset_cpu() functions correctly, use it instead of directly accessing the port. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
90b16d14 |
|
26-Mar-2015 |
Simon Glass <sjg@chromium.org> |
x86: chromebook_link: dts: Add PCH and LPC devices The PCH (Platform Controller Hub) is on the PCI bus, so show it as such. The LPC (Low Pin Count) and SPI bus are inside the PCH, so put these in the right place also. Rename the compatible strings to be more descriptive since this board is the only user. Once we are using driver model fully on x86, these will be dropped. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
aad78d27 |
|
05-Mar-2015 |
Simon Glass <sjg@chromium.org> |
dm: x86: pci: Convert chromebook_link to use driver model for pci Move chromebook_link over to driver model for PCI. This involves: - adding a uclass for platform controller hub - removing most of the existing PCI driver - adjusting how CPU init works to use driver model instead - rename the lpc compatible string (it will be removed later) This does not really take advantage of driver model fully, but it does work. Furture work will improve the code structure to remove many of the explicit calls to init the board. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
161d2e4e |
|
05-Mar-2015 |
Simon Glass <sjg@chromium.org> |
x86: Split up arch_cpu_init() At present we do more in this function than we should. Split out the post-driver-model part into a separate function. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
31f57c28 |
|
05-Mar-2015 |
Simon Glass <sjg@chromium.org> |
x86: Add a x86_ prefix to the x86-specific PCI functions These functions currently use a generic name, but they are for x86 only. This may introduce confusion and prevents U-Boot from using these names more widely. In fact it should be possible to remove these at some point and use generic functions, but for now, rename them. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
#
c72f74e2 |
|
01-Jan-2015 |
Simon Glass <sjg@chromium.org> |
x86: ivybridge: Update microcode early in boot At present the normal update (which happens much later) does not work. This seems to have something to do with the 'no eviction' mode in the CAR, or at least moving the microcode update after that causes it not to work. For now, do an update early on so that it definitely works. Also refuse to continue unless the microcode update check (later in boot) is successful. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
3a5659f7 |
|
01-Jan-2015 |
Simon Glass <sjg@chromium.org> |
x86: ivybridge: Drop support for ROM caching This is set up along with CAR (Cache-as-RAM) anyway. When we relocate we don't really need ROM caching (we read the VGA BIOS from ROM but that is about it) Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
95a5a474 |
|
12-Dec-2014 |
Bin Meng <bmeng.cn@gmail.com> |
x86: Add post failure codes for bist and car Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> |
#
3eafce05 |
|
12-Nov-2014 |
Simon Glass <sjg@chromium.org> |
x86: ivybridge: Add LAPIC support The local advanced programmable interrupt controller is not used much in U-Boot but we do need to set it up. Add basic support for this, which will be extended as needed. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
8e0df066 |
|
12-Nov-2014 |
Simon Glass <sjg@chromium.org> |
x86: ivybridge: Add early init for PCH devices Many PCH devices are hard-coded to a particular PCI address. Set these up early in case they are needed. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
77f9b1fb |
|
12-Nov-2014 |
Simon Glass <sjg@chromium.org> |
x86: ivybridge: Perform Intel microcode update on boot Microcode updates are stored in the device tree. Work through these and apply any that are needed. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
94060ff2 |
|
12-Nov-2014 |
Simon Glass <sjg@chromium.org> |
x86: ivybridge: Check BIST value on boot The built-in self test value should be checked before we continue booting. Refuse to continue if there is something wrong. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
f5fbbe95 |
|
12-Nov-2014 |
Simon Glass <sjg@chromium.org> |
x86: ivybridge: Perform initial CPU setup Set up the flex ratio (controls speed versus heat output) and a few other very early things. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
2b605154 |
|
12-Nov-2014 |
Simon Glass <sjg@chromium.org> |
x86: ivybridge: Add early LPC init so that serial works The PCH (Platform Controller Hub) includes an LPC (Low Pin Count) device which provides a serial port. This is accessible on Chromebooks, so enable it early in the boot process. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
6e5b12b6 |
|
12-Nov-2014 |
Simon Glass <sjg@chromium.org> |
x86: ivybridge: Enable PCI in early init Enable PCI so we can access devices that need to be set up before relocation. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
70a09c6c |
|
12-Nov-2014 |
Simon Glass <sjg@chromium.org> |
x86: chromebook_link: Implement CAR support (cache as RAM) Add support for CAR so that we have memory to use prior to DRAM init. On link there is a total of 128KB of CAR available, although some is used for the memory reference code. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
8ef07571 |
|
12-Nov-2014 |
Simon Glass <sjg@chromium.org> |
x86: Add chromebook_link board This board is a 'bare' version of the existing 'link 'board. It does not require coreboot to run, but is intended to start directly from the reset vector. This initial commit has place holders for a wide range of features. These will be added in follow-on patches and series. So far it cannot be booted as there is no ROM image produced, but it does build without errors. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
83d290c5 |
|
06-May-2018 |
Tom Rini <trini@konsulko.com> |
SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
76d1d02f |
|
28-Mar-2017 |
Simon Glass <sjg@chromium.org> |
board_f: x86: Use checkcpu() for CPU init At present we misuse print_cpuinfo() do so CPU init on x86. This is done because it is the next available call after the console is enabled. But several arches use checkcpu() instead. Despite the horrible name (which we can fix), it seems a better choice. Adjust the various x86 CPU implementations to move their init code into checkcpu() and use print_cpuinfo() only for printing CPU info. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Stefan Roese <sr@denx.de>
|
#
8d8f3acd |
|
16-Jan-2017 |
Simon Glass <sjg@chromium.org> |
x86: ivybridge: Add more debugging for failures Add various debug() messages in places where errors occur. This aids with debugging. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
4cc00f06 |
|
25-Jul-2016 |
Simon Glass <sjg@chromium.org> |
x86: Add debugging when cpu_common_init() fails Add a debug() at this point to help figure out what is wrong. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
7e4a6ae6 |
|
16-Mar-2016 |
Simon Glass <sjg@chromium.org> |
x86: Move common PCH code into a common place The SATA indexed register write functions are common to several Intel PCHs. Move this into a common location. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
50dd3da0 |
|
11-Mar-2016 |
Simon Glass <sjg@chromium.org> |
x86: Move common CPU code to its own place Some of the Intel CPU code is common to several Intel CPUs. Move it into a common location along with required declarations. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
06d336cc |
|
11-Mar-2016 |
Simon Glass <sjg@chromium.org> |
x86: Create a common header for Intel register access There are several blocks of registers that are accessed from all over the code on Intel CPUs. These don't currently have their own driver and it is not clear whether having a driver makes sense. An example is the Memory Controller Hub (MCH). We map it to a known location on some Intel chips (mostly those without FSP - Firmware Support Package). Add a new header file for these registers, and move MCH into it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9e66506d |
|
11-Mar-2016 |
Simon Glass <sjg@chromium.org> |
x86: Move microcode code to a common location This code is used on several Intel CPUs. Move it into a common location. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
3f603cbb |
|
11-Feb-2016 |
Simon Glass <sjg@chromium.org> |
dm: Use uclass_first_device_err() where it is useful Use this new function in places where it simplifies the code. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
5213f280 |
|
17-Jan-2016 |
Simon Glass <sjg@chromium.org> |
x86: ivybridge: Convert enable_usb_bar() to use DM PCI API Convert this function over to use the driver model PCI API. In this case we want to avoid using the real PCI devices since they have not yet been probed. Instead, write directly to their PCI configuration address. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
0c7645bd |
|
17-Jan-2016 |
Simon Glass <sjg@chromium.org> |
x86: ivybridge: Use the I2C driver to perform SMbus init Move the init code into the I2C driver. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Heiko Schocher <hs@denx.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
d46f2a68 |
|
17-Jan-2016 |
Simon Glass <sjg@chromium.org> |
x86: ivybridge: Do the SATA init before relocation The SATA device needs to set itself up so that it appears correctly on the PCI bus. The easiest way to do this is to set it up to probe before relocation. This can do the early setup. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
9fd11c7a |
|
17-Jan-2016 |
Simon Glass <sjg@chromium.org> |
x86: ivybridge: Move GPIO init to the LPC init() method This init can happen in the driver also. Move it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
17e0a9ab |
|
17-Jan-2016 |
Simon Glass <sjg@chromium.org> |
x86: ivybridge: Move graphics init much later We don't need to init the graphics controller so early. Move it alongside the other graphics setup, just before we run the ROM. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
f633efa3 |
|
17-Jan-2016 |
Simon Glass <sjg@chromium.org> |
x86: ivybridge: Probe the LPC in CPU init We can drop the explicit probe of the PCH since the LPC is a child device and this will happen automatically. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
655925a9 |
|
17-Jan-2016 |
Simon Glass <sjg@chromium.org> |
x86: ivybridge: Move northbridge init into the probe() method Now that we have a proper driver for the nortbridge, set it up in by probing it, and move the early init code into the probe() method. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
858361b1 |
|
17-Jan-2016 |
Simon Glass <sjg@chromium.org> |
x86: ivybridge: Rename bd82x6x_init() Rename the existing bd82x6x_init() to bd82x6x_init_extra(). We will remove this in a later patch. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
fe40bd4d |
|
17-Jan-2016 |
Simon Glass <sjg@chromium.org> |
x86: ivybridge: Move more init to the probe() function Move SPI and port80 init to lpc_early_init(), called from the LPC's probe() method. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
788cd908 |
|
17-Jan-2016 |
Simon Glass <sjg@chromium.org> |
x86: ivybridge: Move lpc_early_init() to probe() Move this code to the LPC's probe() method so that it will happen automatically when the LPC is probed before relocation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
4acc83d4 |
|
17-Jan-2016 |
Simon Glass <sjg@chromium.org> |
x86: ivybridge: Set up the LPC device using driver model Find the LPC device in arch_cpu_init_dm() as a first step to converting this code to use driver model. Probing the LPC will probe its parent (the PCH) automatically, so make sure that probing the PCH does nothing before relocation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
789fa275 |
|
25-Nov-2015 |
Bin Meng <bmeng.cn@gmail.com> |
x86: Remove HAVE_ACPI_RESUME These are currently dead codes. Until we have complete ACPI support, we don't know if it works or not. Remove to avoid confusion. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
|
#
80af3984 |
|
13-Nov-2015 |
Bin Meng <bmeng.cn@gmail.com> |
x86: Convert to use driver model timer Convert all x86 boards to use driver model tsc timer. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
|
#
7b95252d |
|
18-Oct-2015 |
Simon Glass <sjg@chromium.org> |
x86: chromebook_link: Enable the debug UART Add support for the debug UART on link. This is useful for early debugging. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
5021c81f |
|
28-Apr-2015 |
Simon Glass <sjg@chromium.org> |
x86: ivybridge: Use reset_cpu() Now that reset_cpu() functions correctly, use it instead of directly accessing the port. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
90b16d14 |
|
26-Mar-2015 |
Simon Glass <sjg@chromium.org> |
x86: chromebook_link: dts: Add PCH and LPC devices The PCH (Platform Controller Hub) is on the PCI bus, so show it as such. The LPC (Low Pin Count) and SPI bus are inside the PCH, so put these in the right place also. Rename the compatible strings to be more descriptive since this board is the only user. Once we are using driver model fully on x86, these will be dropped. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
aad78d27 |
|
05-Mar-2015 |
Simon Glass <sjg@chromium.org> |
dm: x86: pci: Convert chromebook_link to use driver model for pci Move chromebook_link over to driver model for PCI. This involves: - adding a uclass for platform controller hub - removing most of the existing PCI driver - adjusting how CPU init works to use driver model instead - rename the lpc compatible string (it will be removed later) This does not really take advantage of driver model fully, but it does work. Furture work will improve the code structure to remove many of the explicit calls to init the board. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
161d2e4e |
|
05-Mar-2015 |
Simon Glass <sjg@chromium.org> |
x86: Split up arch_cpu_init() At present we do more in this function than we should. Split out the post-driver-model part into a separate function. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
31f57c28 |
|
05-Mar-2015 |
Simon Glass <sjg@chromium.org> |
x86: Add a x86_ prefix to the x86-specific PCI functions These functions currently use a generic name, but they are for x86 only. This may introduce confusion and prevents U-Boot from using these names more widely. In fact it should be possible to remove these at some point and use generic functions, but for now, rename them. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
#
c72f74e2 |
|
01-Jan-2015 |
Simon Glass <sjg@chromium.org> |
x86: ivybridge: Update microcode early in boot At present the normal update (which happens much later) does not work. This seems to have something to do with the 'no eviction' mode in the CAR, or at least moving the microcode update after that causes it not to work. For now, do an update early on so that it definitely works. Also refuse to continue unless the microcode update check (later in boot) is successful. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
3a5659f7 |
|
01-Jan-2015 |
Simon Glass <sjg@chromium.org> |
x86: ivybridge: Drop support for ROM caching This is set up along with CAR (Cache-as-RAM) anyway. When we relocate we don't really need ROM caching (we read the VGA BIOS from ROM but that is about it) Drop it. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
95a5a474 |
|
12-Dec-2014 |
Bin Meng <bmeng.cn@gmail.com> |
x86: Add post failure codes for bist and car Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
|
#
3eafce05 |
|
12-Nov-2014 |
Simon Glass <sjg@chromium.org> |
x86: ivybridge: Add LAPIC support The local advanced programmable interrupt controller is not used much in U-Boot but we do need to set it up. Add basic support for this, which will be extended as needed. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
8e0df066 |
|
12-Nov-2014 |
Simon Glass <sjg@chromium.org> |
x86: ivybridge: Add early init for PCH devices Many PCH devices are hard-coded to a particular PCI address. Set these up early in case they are needed. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
77f9b1fb |
|
12-Nov-2014 |
Simon Glass <sjg@chromium.org> |
x86: ivybridge: Perform Intel microcode update on boot Microcode updates are stored in the device tree. Work through these and apply any that are needed. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
94060ff2 |
|
12-Nov-2014 |
Simon Glass <sjg@chromium.org> |
x86: ivybridge: Check BIST value on boot The built-in self test value should be checked before we continue booting. Refuse to continue if there is something wrong. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
f5fbbe95 |
|
12-Nov-2014 |
Simon Glass <sjg@chromium.org> |
x86: ivybridge: Perform initial CPU setup Set up the flex ratio (controls speed versus heat output) and a few other very early things. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
2b605154 |
|
12-Nov-2014 |
Simon Glass <sjg@chromium.org> |
x86: ivybridge: Add early LPC init so that serial works The PCH (Platform Controller Hub) includes an LPC (Low Pin Count) device which provides a serial port. This is accessible on Chromebooks, so enable it early in the boot process. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
6e5b12b6 |
|
12-Nov-2014 |
Simon Glass <sjg@chromium.org> |
x86: ivybridge: Enable PCI in early init Enable PCI so we can access devices that need to be set up before relocation. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
70a09c6c |
|
12-Nov-2014 |
Simon Glass <sjg@chromium.org> |
x86: chromebook_link: Implement CAR support (cache as RAM) Add support for CAR so that we have memory to use prior to DRAM init. On link there is a total of 128KB of CAR available, although some is used for the memory reference code. Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
8ef07571 |
|
12-Nov-2014 |
Simon Glass <sjg@chromium.org> |
x86: Add chromebook_link board This board is a 'bare' version of the existing 'link 'board. It does not require coreboot to run, but is intended to start directly from the reset vector. This initial commit has place holders for a wide range of features. These will be added in follow-on patches and series. So far it cannot be booted as there is no ROM image produced, but it does build without errors. Signed-off-by: Simon Glass <sjg@chromium.org>
|