1/* SPDX-License-Identifier: GPL-2.0+ */ 2/* 3 * (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH <www.elinos.com> 4 * Andreas Heppel <aheppel@sysgo.de> 5 * 6 * (C) Copyright 2002 7 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 8 * Copyright (c) 2021 Maciej W. Rozycki <macro@orcam.me.uk> 9 */ 10 11#ifndef _PCI_H 12#define _PCI_H 13 14#define PCI_CFG_SPACE_SIZE 256 15#define PCI_CFG_SPACE_EXP_SIZE 4096 16 17/* 18 * Under PCI, each device has 256 bytes of configuration address space, 19 * of which the first 64 bytes are standardized as follows: 20 */ 21#define PCI_STD_HEADER_SIZEOF 64 22#define PCI_VENDOR_ID 0x00 /* 16 bits */ 23#define PCI_DEVICE_ID 0x02 /* 16 bits */ 24#define PCI_COMMAND 0x04 /* 16 bits */ 25#define PCI_COMMAND_IO 0x1 /* Enable response in I/O space */ 26#define PCI_COMMAND_MEMORY 0x2 /* Enable response in Memory space */ 27#define PCI_COMMAND_MASTER 0x4 /* Enable bus mastering */ 28#define PCI_COMMAND_SPECIAL 0x8 /* Enable response to special cycles */ 29#define PCI_COMMAND_INVALIDATE 0x10 /* Use memory write and invalidate */ 30#define PCI_COMMAND_VGA_PALETTE 0x20 /* Enable palette snooping */ 31#define PCI_COMMAND_PARITY 0x40 /* Enable parity checking */ 32#define PCI_COMMAND_WAIT 0x80 /* Enable address/data stepping */ 33#define PCI_COMMAND_SERR 0x100 /* Enable SERR */ 34#define PCI_COMMAND_FAST_BACK 0x200 /* Enable back-to-back writes */ 35 36#define PCI_STATUS 0x06 /* 16 bits */ 37#define PCI_STATUS_CAP_LIST 0x10 /* Support Capability List */ 38#define PCI_STATUS_66MHZ 0x20 /* Support 66 Mhz PCI 2.1 bus */ 39#define PCI_STATUS_UDF 0x40 /* Support User Definable Features [obsolete] */ 40#define PCI_STATUS_FAST_BACK 0x80 /* Accept fast-back to back */ 41#define PCI_STATUS_PARITY 0x100 /* Detected parity error */ 42#define PCI_STATUS_DEVSEL_MASK 0x600 /* DEVSEL timing */ 43#define PCI_STATUS_DEVSEL_FAST 0x000 44#define PCI_STATUS_DEVSEL_MEDIUM 0x200 45#define PCI_STATUS_DEVSEL_SLOW 0x400 46#define PCI_STATUS_SIG_TARGET_ABORT 0x800 /* Set on target abort */ 47#define PCI_STATUS_REC_TARGET_ABORT 0x1000 /* Master ack of " */ 48#define PCI_STATUS_REC_MASTER_ABORT 0x2000 /* Set on master abort */ 49#define PCI_STATUS_SIG_SYSTEM_ERROR 0x4000 /* Set when we drive SERR */ 50#define PCI_STATUS_DETECTED_PARITY 0x8000 /* Set on parity error */ 51 52#define PCI_CLASS_REVISION 0x08 /* High 24 bits are class, low 8 53 revision */ 54#define PCI_REVISION_ID 0x08 /* Revision ID */ 55#define PCI_CLASS_PROG 0x09 /* Reg. Level Programming Interface */ 56#define PCI_CLASS_DEVICE 0x0a /* Device class */ 57#define PCI_CLASS_CODE 0x0b /* Device class code */ 58#define PCI_CLASS_SUB_CODE 0x0a /* Device sub-class code */ 59 60#define PCI_CACHE_LINE_SIZE 0x0c /* 8 bits */ 61#define PCI_LATENCY_TIMER 0x0d /* 8 bits */ 62#define PCI_HEADER_TYPE 0x0e /* 8 bits */ 63#define PCI_HEADER_TYPE_NORMAL 0 64#define PCI_HEADER_TYPE_BRIDGE 1 65#define PCI_HEADER_TYPE_CARDBUS 2 66 67#define PCI_BIST 0x0f /* 8 bits */ 68#define PCI_BIST_CODE_MASK 0x0f /* Return result */ 69#define PCI_BIST_START 0x40 /* 1 to start BIST, 2 secs or less */ 70#define PCI_BIST_CAPABLE 0x80 /* 1 if BIST capable */ 71 72/* 73 * Base addresses specify locations in memory or I/O space. 74 * Decoded size can be determined by writing a value of 75 * 0xffffffff to the register, and reading it back. Only 76 * 1 bits are decoded. 77 */ 78#define PCI_BASE_ADDRESS_0 0x10 /* 32 bits */ 79#define PCI_BASE_ADDRESS_1 0x14 /* 32 bits [htype 0,1 only] */ 80#define PCI_BASE_ADDRESS_2 0x18 /* 32 bits [htype 0 only] */ 81#define PCI_BASE_ADDRESS_3 0x1c /* 32 bits */ 82#define PCI_BASE_ADDRESS_4 0x20 /* 32 bits */ 83#define PCI_BASE_ADDRESS_5 0x24 /* 32 bits */ 84#define PCI_BASE_ADDRESS_SPACE 0x01 /* 0 = memory, 1 = I/O */ 85#define PCI_BASE_ADDRESS_SPACE_IO 0x01 86#define PCI_BASE_ADDRESS_SPACE_MEMORY 0x00 87#define PCI_BASE_ADDRESS_MEM_TYPE_MASK 0x06 88#define PCI_BASE_ADDRESS_MEM_TYPE_32 0x00 /* 32 bit address */ 89#define PCI_BASE_ADDRESS_MEM_TYPE_1M 0x02 /* Below 1M [obsolete] */ 90#define PCI_BASE_ADDRESS_MEM_TYPE_64 0x04 /* 64 bit address */ 91#define PCI_BASE_ADDRESS_MEM_PREFETCH 0x08 /* prefetchable? */ 92#define PCI_BASE_ADDRESS_MEM_MASK (~0x0fULL) 93#define PCI_BASE_ADDRESS_IO_MASK (~0x03ULL) 94/* bit 1 is reserved if address_space = 1 */ 95 96/* Convert a regsister address (e.g. PCI_BASE_ADDRESS_1) to a bar # (e.g. 1) */ 97#define pci_offset_to_barnum(offset) \ 98 (((offset) - PCI_BASE_ADDRESS_0) / sizeof(u32)) 99 100/* Header type 0 (normal devices) */ 101#define PCI_CARDBUS_CIS 0x28 102#define PCI_SUBSYSTEM_VENDOR_ID 0x2c 103#define PCI_SUBSYSTEM_ID 0x2e 104#define PCI_ROM_ADDRESS 0x30 /* Bits 31..11 are address, 10..1 reserved */ 105#define PCI_ROM_ADDRESS_ENABLE 0x01 106#define PCI_ROM_ADDRESS_MASK (~0x7ffULL) 107 108#define PCI_CAPABILITY_LIST 0x34 /* Offset of first capability list entry */ 109 110/* 0x35-0x3b are reserved */ 111#define PCI_INTERRUPT_LINE 0x3c /* 8 bits */ 112#define PCI_INTERRUPT_PIN 0x3d /* 8 bits */ 113#define PCI_MIN_GNT 0x3e /* 8 bits */ 114#define PCI_MAX_LAT 0x3f /* 8 bits */ 115 116#define PCI_INTERRUPT_LINE_DISABLE 0xff 117 118/* Header type 1 (PCI-to-PCI bridges) */ 119#define PCI_PRIMARY_BUS 0x18 /* Primary bus number */ 120#define PCI_SECONDARY_BUS 0x19 /* Secondary bus number */ 121#define PCI_SUBORDINATE_BUS 0x1a /* Highest bus number behind the bridge */ 122#define PCI_SEC_LATENCY_TIMER 0x1b /* Latency timer for secondary interface */ 123#define PCI_IO_BASE 0x1c /* I/O range behind the bridge */ 124#define PCI_IO_LIMIT 0x1d 125#define PCI_IO_RANGE_TYPE_MASK 0x0f /* I/O bridging type */ 126#define PCI_IO_RANGE_TYPE_16 0x00 127#define PCI_IO_RANGE_TYPE_32 0x01 128#define PCI_IO_RANGE_MASK ~0x0f 129#define PCI_SEC_STATUS 0x1e /* Secondary status register, only bit 14 used */ 130#define PCI_MEMORY_BASE 0x20 /* Memory range behind */ 131#define PCI_MEMORY_LIMIT 0x22 132#define PCI_MEMORY_RANGE_TYPE_MASK 0x0f 133#define PCI_MEMORY_RANGE_MASK ~0x0f 134#define PCI_PREF_MEMORY_BASE 0x24 /* Prefetchable memory range behind */ 135#define PCI_PREF_MEMORY_LIMIT 0x26 136#define PCI_PREF_RANGE_TYPE_MASK 0x0f 137#define PCI_PREF_RANGE_TYPE_32 0x00 138#define PCI_PREF_RANGE_TYPE_64 0x01 139#define PCI_PREF_RANGE_MASK ~0x0f 140#define PCI_PREF_BASE_UPPER32 0x28 /* Upper half of prefetchable memory range */ 141#define PCI_PREF_LIMIT_UPPER32 0x2c 142#define PCI_IO_BASE_UPPER16 0x30 /* Upper half of I/O addresses */ 143#define PCI_IO_LIMIT_UPPER16 0x32 144/* 0x34 same as for htype 0 */ 145/* 0x35-0x3b is reserved */ 146#define PCI_ROM_ADDRESS1 0x38 /* Same as PCI_ROM_ADDRESS, but for htype 1 */ 147/* 0x3c-0x3d are same as for htype 0 */ 148#define PCI_BRIDGE_CONTROL 0x3e 149#define PCI_BRIDGE_CTL_PARITY 0x01 /* Enable parity detection on secondary interface */ 150#define PCI_BRIDGE_CTL_SERR 0x02 /* The same for SERR forwarding */ 151#define PCI_BRIDGE_CTL_NO_ISA 0x04 /* Disable bridging of ISA ports */ 152#define PCI_BRIDGE_CTL_VGA 0x08 /* Forward VGA addresses */ 153#define PCI_BRIDGE_CTL_MASTER_ABORT 0x20 /* Report master aborts */ 154#define PCI_BRIDGE_CTL_BUS_RESET 0x40 /* Secondary bus reset */ 155#define PCI_BRIDGE_CTL_FAST_BACK 0x80 /* Fast Back2Back enabled on secondary interface */ 156 157/* Header type 2 (CardBus bridges) */ 158#define PCI_CB_CAPABILITY_LIST 0x14 159/* 0x15 reserved */ 160#define PCI_CB_SEC_STATUS 0x16 /* Secondary status */ 161#define PCI_CB_PRIMARY_BUS 0x18 /* PCI bus number */ 162#define PCI_CB_CARD_BUS 0x19 /* CardBus bus number */ 163#define PCI_CB_SUBORDINATE_BUS 0x1a /* Subordinate bus number */ 164#define PCI_CB_LATENCY_TIMER 0x1b /* CardBus latency timer */ 165#define PCI_CB_MEMORY_BASE_0 0x1c 166#define PCI_CB_MEMORY_LIMIT_0 0x20 167#define PCI_CB_MEMORY_BASE_1 0x24 168#define PCI_CB_MEMORY_LIMIT_1 0x28 169#define PCI_CB_IO_BASE_0 0x2c 170#define PCI_CB_IO_BASE_0_HI 0x2e 171#define PCI_CB_IO_LIMIT_0 0x30 172#define PCI_CB_IO_LIMIT_0_HI 0x32 173#define PCI_CB_IO_BASE_1 0x34 174#define PCI_CB_IO_BASE_1_HI 0x36 175#define PCI_CB_IO_LIMIT_1 0x38 176#define PCI_CB_IO_LIMIT_1_HI 0x3a 177#define PCI_CB_IO_RANGE_MASK ~0x03 178/* 0x3c-0x3d are same as for htype 0 */ 179#define PCI_CB_BRIDGE_CONTROL 0x3e 180#define PCI_CB_BRIDGE_CTL_PARITY 0x01 /* Similar to standard bridge control register */ 181#define PCI_CB_BRIDGE_CTL_SERR 0x02 182#define PCI_CB_BRIDGE_CTL_ISA 0x04 183#define PCI_CB_BRIDGE_CTL_VGA 0x08 184#define PCI_CB_BRIDGE_CTL_MASTER_ABORT 0x20 185#define PCI_CB_BRIDGE_CTL_CB_RESET 0x40 /* CardBus reset */ 186#define PCI_CB_BRIDGE_CTL_16BIT_INT 0x80 /* Enable interrupt for 16-bit cards */ 187#define PCI_CB_BRIDGE_CTL_PREFETCH_MEM0 0x100 /* Prefetch enable for both memory regions */ 188#define PCI_CB_BRIDGE_CTL_PREFETCH_MEM1 0x200 189#define PCI_CB_BRIDGE_CTL_POST_WRITES 0x400 190#define PCI_CB_SUBSYSTEM_VENDOR_ID 0x40 191#define PCI_CB_SUBSYSTEM_ID 0x42 192#define PCI_CB_LEGACY_MODE_BASE 0x44 /* 16-bit PC Card legacy mode base address (ExCa) */ 193/* 0x48-0x7f reserved */ 194 195/* Capability lists */ 196 197#define PCI_CAP_LIST_ID 0 /* Capability ID */ 198#define PCI_CAP_ID_PM 0x01 /* Power Management */ 199#define PCI_CAP_ID_AGP 0x02 /* Accelerated Graphics Port */ 200#define PCI_CAP_ID_VPD 0x03 /* Vital Product Data */ 201#define PCI_CAP_ID_SLOTID 0x04 /* Slot Identification */ 202#define PCI_CAP_ID_MSI 0x05 /* Message Signalled Interrupts */ 203#define PCI_CAP_ID_CHSWP 0x06 /* CompactPCI HotSwap */ 204#define PCI_CAP_ID_PCIX 0x07 /* PCI-X */ 205#define PCI_CAP_ID_HT 0x08 /* HyperTransport */ 206#define PCI_CAP_ID_VNDR 0x09 /* Vendor-Specific */ 207#define PCI_CAP_ID_DBG 0x0A /* Debug port */ 208#define PCI_CAP_ID_CCRC 0x0B /* CompactPCI Central Resource Control */ 209#define PCI_CAP_ID_SHPC 0x0C /* PCI Standard Hot-Plug Controller */ 210#define PCI_CAP_ID_SSVID 0x0D /* Bridge subsystem vendor/device ID */ 211#define PCI_CAP_ID_AGP3 0x0E /* AGP Target PCI-PCI bridge */ 212#define PCI_CAP_ID_SECDEV 0x0F /* Secure Device */ 213#define PCI_CAP_ID_EXP 0x10 /* PCI Express */ 214#define PCI_CAP_ID_MSIX 0x11 /* MSI-X */ 215#define PCI_CAP_ID_SATA 0x12 /* SATA Data/Index Conf. */ 216#define PCI_CAP_ID_AF 0x13 /* PCI Advanced Features */ 217#define PCI_CAP_ID_EA 0x14 /* PCI Enhanced Allocation */ 218#define PCI_CAP_ID_MAX PCI_CAP_ID_EA 219#define PCI_CAP_LIST_NEXT 1 /* Next capability in the list */ 220#define PCI_CAP_FLAGS 2 /* Capability defined flags (16 bits) */ 221#define PCI_CAP_SIZEOF 4 222 223/* Power Management Registers */ 224 225#define PCI_PM_CAP_VER_MASK 0x0007 /* Version */ 226#define PCI_PM_CAP_PME_CLOCK 0x0008 /* PME clock required */ 227#define PCI_PM_CAP_AUX_POWER 0x0010 /* Auxilliary power support */ 228#define PCI_PM_CAP_DSI 0x0020 /* Device specific initialization */ 229#define PCI_PM_CAP_D1 0x0200 /* D1 power state support */ 230#define PCI_PM_CAP_D2 0x0400 /* D2 power state support */ 231#define PCI_PM_CAP_PME 0x0800 /* PME pin supported */ 232#define PCI_PM_CTRL 4 /* PM control and status register */ 233#define PCI_PM_CTRL_STATE_MASK 0x0003 /* Current power state (D0 to D3) */ 234#define PCI_PM_CTRL_PME_ENABLE 0x0100 /* PME pin enable */ 235#define PCI_PM_CTRL_DATA_SEL_MASK 0x1e00 /* Data select (??) */ 236#define PCI_PM_CTRL_DATA_SCALE_MASK 0x6000 /* Data scale (??) */ 237#define PCI_PM_CTRL_PME_STATUS 0x8000 /* PME pin status */ 238#define PCI_PM_PPB_EXTENSIONS 6 /* PPB support extensions (??) */ 239#define PCI_PM_PPB_B2_B3 0x40 /* Stop clock when in D3hot (??) */ 240#define PCI_PM_BPCC_ENABLE 0x80 /* Bus power/clock control enable (??) */ 241#define PCI_PM_DATA_REGISTER 7 /* (??) */ 242#define PCI_PM_SIZEOF 8 243 244/* AGP registers */ 245 246#define PCI_AGP_VERSION 2 /* BCD version number */ 247#define PCI_AGP_RFU 3 /* Rest of capability flags */ 248#define PCI_AGP_STATUS 4 /* Status register */ 249#define PCI_AGP_STATUS_RQ_MASK 0xff000000 /* Maximum number of requests - 1 */ 250#define PCI_AGP_STATUS_SBA 0x0200 /* Sideband addressing supported */ 251#define PCI_AGP_STATUS_64BIT 0x0020 /* 64-bit addressing supported */ 252#define PCI_AGP_STATUS_FW 0x0010 /* FW transfers supported */ 253#define PCI_AGP_STATUS_RATE4 0x0004 /* 4x transfer rate supported */ 254#define PCI_AGP_STATUS_RATE2 0x0002 /* 2x transfer rate supported */ 255#define PCI_AGP_STATUS_RATE1 0x0001 /* 1x transfer rate supported */ 256#define PCI_AGP_COMMAND 8 /* Control register */ 257#define PCI_AGP_COMMAND_RQ_MASK 0xff000000 /* Master: Maximum number of requests */ 258#define PCI_AGP_COMMAND_SBA 0x0200 /* Sideband addressing enabled */ 259#define PCI_AGP_COMMAND_AGP 0x0100 /* Allow processing of AGP transactions */ 260#define PCI_AGP_COMMAND_64BIT 0x0020 /* Allow processing of 64-bit addresses */ 261#define PCI_AGP_COMMAND_FW 0x0010 /* Force FW transfers */ 262#define PCI_AGP_COMMAND_RATE4 0x0004 /* Use 4x rate */ 263#define PCI_AGP_COMMAND_RATE2 0x0002 /* Use 4x rate */ 264#define PCI_AGP_COMMAND_RATE1 0x0001 /* Use 4x rate */ 265#define PCI_AGP_SIZEOF 12 266 267/* PCI-X registers */ 268 269#define PCI_X_CMD_DPERR_E 0x0001 /* Data Parity Error Recovery Enable */ 270#define PCI_X_CMD_ERO 0x0002 /* Enable Relaxed Ordering */ 271#define PCI_X_CMD_MAX_READ 0x0000 /* Max Memory Read Byte Count */ 272#define PCI_X_CMD_MAX_SPLIT 0x0030 /* Max Outstanding Split Transactions */ 273#define PCI_X_CMD_VERSION(x) (((x) >> 12) & 3) /* Version */ 274 275 276/* Slot Identification */ 277 278#define PCI_SID_ESR 2 /* Expansion Slot Register */ 279#define PCI_SID_ESR_NSLOTS 0x1f /* Number of expansion slots available */ 280#define PCI_SID_ESR_FIC 0x20 /* First In Chassis Flag */ 281#define PCI_SID_CHASSIS_NR 3 /* Chassis Number */ 282 283/* Message Signalled Interrupts registers */ 284 285#define PCI_MSI_FLAGS 2 /* Various flags */ 286#define PCI_MSI_FLAGS_64BIT 0x80 /* 64-bit addresses allowed */ 287#define PCI_MSI_FLAGS_QSIZE 0x70 /* Message queue size configured */ 288#define PCI_MSI_FLAGS_QMASK 0x0e /* Maximum queue size available */ 289#define PCI_MSI_FLAGS_ENABLE 0x01 /* MSI feature enabled */ 290#define PCI_MSI_FLAGS_MASKBIT 0x0100 /* Per-vector masking capable */ 291#define PCI_MSI_RFU 3 /* Rest of capability flags */ 292#define PCI_MSI_ADDRESS_LO 4 /* Lower 32 bits */ 293#define PCI_MSI_ADDRESS_HI 8 /* Upper 32 bits (if PCI_MSI_FLAGS_64BIT set) */ 294#define PCI_MSI_DATA_32 8 /* 16 bits of data for 32-bit devices */ 295#define PCI_MSI_DATA_64 12 /* 16 bits of data for 64-bit devices */ 296 297#define PCI_MAX_PCI_DEVICES 32 298#define PCI_MAX_PCI_FUNCTIONS 8 299 300#define PCI_FIND_CAP_TTL 0x48 301#define CAP_START_POS 0x40 302 303/* Extended Capabilities (PCI-X 2.0 and Express) */ 304#define PCI_EXT_CAP_ID(header) (header & 0x0000ffff) 305#define PCI_EXT_CAP_VER(header) ((header >> 16) & 0xf) 306#define PCI_EXT_CAP_NEXT(header) ((header >> 20) & 0xffc) 307 308#define PCI_EXT_CAP_ID_ERR 0x01 /* Advanced Error Reporting */ 309#define PCI_EXT_CAP_ID_VC 0x02 /* Virtual Channel Capability */ 310#define PCI_EXT_CAP_ID_DSN 0x03 /* Device Serial Number */ 311#define PCI_EXT_CAP_ID_PWR 0x04 /* Power Budgeting */ 312#define PCI_EXT_CAP_ID_RCLD 0x05 /* Root Complex Link Declaration */ 313#define PCI_EXT_CAP_ID_RCILC 0x06 /* Root Complex Internal Link Control */ 314#define PCI_EXT_CAP_ID_RCEC 0x07 /* Root Complex Event Collector */ 315#define PCI_EXT_CAP_ID_MFVC 0x08 /* Multi-Function VC Capability */ 316#define PCI_EXT_CAP_ID_VC9 0x09 /* same as _VC */ 317#define PCI_EXT_CAP_ID_RCRB 0x0A /* Root Complex RB? */ 318#define PCI_EXT_CAP_ID_VNDR 0x0B /* Vendor-Specific */ 319#define PCI_EXT_CAP_ID_CAC 0x0C /* Config Access - obsolete */ 320#define PCI_EXT_CAP_ID_ACS 0x0D /* Access Control Services */ 321#define PCI_EXT_CAP_ID_ARI 0x0E /* Alternate Routing ID */ 322#define PCI_EXT_CAP_ID_ATS 0x0F /* Address Translation Services */ 323#define PCI_EXT_CAP_ID_SRIOV 0x10 /* Single Root I/O Virtualization */ 324#define PCI_EXT_CAP_ID_MRIOV 0x11 /* Multi Root I/O Virtualization */ 325#define PCI_EXT_CAP_ID_MCAST 0x12 /* Multicast */ 326#define PCI_EXT_CAP_ID_PRI 0x13 /* Page Request Interface */ 327#define PCI_EXT_CAP_ID_AMD_XXX 0x14 /* Reserved for AMD */ 328#define PCI_EXT_CAP_ID_REBAR 0x15 /* Resizable BAR */ 329#define PCI_EXT_CAP_ID_DPA 0x16 /* Dynamic Power Allocation */ 330#define PCI_EXT_CAP_ID_TPH 0x17 /* TPH Requester */ 331#define PCI_EXT_CAP_ID_LTR 0x18 /* Latency Tolerance Reporting */ 332#define PCI_EXT_CAP_ID_SECPCI 0x19 /* Secondary PCIe Capability */ 333#define PCI_EXT_CAP_ID_PMUX 0x1A /* Protocol Multiplexing */ 334#define PCI_EXT_CAP_ID_PASID 0x1B /* Process Address Space ID */ 335#define PCI_EXT_CAP_ID_DPC 0x1D /* Downstream Port Containment */ 336#define PCI_EXT_CAP_ID_L1SS 0x1E /* L1 PM Substates */ 337#define PCI_EXT_CAP_ID_PTM 0x1F /* Precision Time Measurement */ 338#define PCI_EXT_CAP_ID_MAX PCI_EXT_CAP_ID_PTM 339 340/* Enhanced Allocation Registers */ 341#define PCI_EA_NUM_ENT 2 /* Number of Capability Entries */ 342#define PCI_EA_NUM_ENT_MASK 0x3f /* Num Entries Mask */ 343#define PCI_EA_FIRST_ENT 4 /* First EA Entry in List */ 344#define PCI_EA_ES 0x00000007 /* Entry Size */ 345#define PCI_EA_BEI 0x000000f0 /* BAR Equivalent Indicator */ 346/* 9-14 map to VF BARs 0-5 respectively */ 347#define PCI_EA_BEI_VF_BAR0 9 348#define PCI_EA_BEI_VF_BAR5 14 349/* Base, MaxOffset registers */ 350/* bit 0 is reserved */ 351#define PCI_EA_IS_64 0x00000002 /* 64-bit field flag */ 352#define PCI_EA_FIELD_MASK 0xfffffffc /* For Base & Max Offset */ 353 354/* PCI Express capabilities */ 355#define PCI_EXP_FLAGS 2 /* Capabilities register */ 356#define PCI_EXP_FLAGS_VERS 0x000f /* Capability Version */ 357#define PCI_EXP_FLAGS_TYPE 0x00f0 /* Device/Port type */ 358#define PCI_EXP_TYPE_ROOT_PORT 0x4 /* Root Port */ 359#define PCI_EXP_TYPE_DOWNSTREAM 0x6 /* Downstream Port */ 360#define PCI_EXP_TYPE_PCIE_BRIDGE 0x8 /* PCI/PCI-X to PCIe Bridge */ 361#define PCI_EXP_DEVCAP 4 /* Device capabilities */ 362#define PCI_EXP_DEVCAP_FLR 0x10000000 /* Function Level Reset */ 363#define PCI_EXP_DEVCAP_PAYLOAD 0x0007 /* Max payload size supported */ 364#define PCI_EXP_DEVCAP_PAYLOAD_128B 0x0000 /* 128 Bytes */ 365#define PCI_EXP_DEVCAP_PAYLOAD_256B 0x0001 /* 256 Bytes */ 366#define PCI_EXP_DEVCAP_PAYLOAD_512B 0x0002 /* 512 Bytes */ 367#define PCI_EXP_DEVCAP_PAYLOAD_1024B 0x0003 /* 1024 Bytes */ 368#define PCI_EXP_DEVCAP_PAYLOAD_2048B 0x0004 /* 2048 Bytes */ 369#define PCI_EXP_DEVCAP_PAYLOAD_4096B 0x0005 /* 4096 Bytes */ 370#define PCI_EXP_DEVCTL 8 /* Device Control */ 371#define PCI_EXP_DEVCTL_PAYLOAD 0x00e0 /* Max_Payload_Size */ 372#define PCI_EXP_DEVCTL_PAYLOAD_128B 0x0000 /* 128 Bytes */ 373#define PCI_EXP_DEVCTL_PAYLOAD_256B 0x0020 /* 256 Bytes */ 374#define PCI_EXP_DEVCTL_PAYLOAD_512B 0x0040 /* 512 Bytes */ 375#define PCI_EXP_DEVCTL_PAYLOAD_1024B 0x0060 /* 1024 Bytes */ 376#define PCI_EXP_DEVCTL_PAYLOAD_2048B 0x0080 /* 2048 Bytes */ 377#define PCI_EXP_DEVCTL_PAYLOAD_4096B 0x00a0 /* 4096 Bytes */ 378#define PCI_EXP_DEVCTL_RELAX_EN 0x0010 /* Enable relaxed ordering */ 379#define PCI_EXP_DEVCTL_NOSNOOP_EN 0x0800 /* Enable No Snoop */ 380#define PCI_EXP_DEVCTL_READRQ 0x7000 /* Max_Read_Request_Size */ 381#define PCI_EXP_DEVCTL_READRQ_128B 0x0000 /* 128 Bytes */ 382#define PCI_EXP_DEVCTL_READRQ_256B 0x1000 /* 256 Bytes */ 383#define PCI_EXP_DEVCTL_READRQ_512B 0x2000 /* 512 Bytes */ 384#define PCI_EXP_DEVCTL_READRQ_1024B 0x3000 /* 1024 Bytes */ 385#define PCI_EXP_DEVCTL_READRQ_2048B 0x4000 /* 2048 Bytes */ 386#define PCI_EXP_DEVCTL_READRQ_4096B 0x5000 /* 4096 Bytes */ 387#define PCI_EXP_DEVCTL_BCR_FLR 0x8000 /* Bridge Configuration Retry / FLR */ 388#define PCI_EXP_LNKCAP 12 /* Link Capabilities */ 389#define PCI_EXP_LNKCAP_SLS 0x0000000f /* Supported Link Speeds */ 390#define PCI_EXP_LNKCAP_SLS_2_5GB 0x00000001 /* LNKCAP2 SLS Vector bit 0 */ 391#define PCI_EXP_LNKCAP_SLS_5_0GB 0x00000002 /* LNKCAP2 SLS Vector bit 1 */ 392#define PCI_EXP_LNKCAP_SLS_8_0GB 0x00000003 /* LNKCAP2 SLS Vector bit 2 */ 393#define PCI_EXP_LNKCAP_MLW 0x000003f0 /* Maximum Link Width */ 394#define PCI_EXP_LNKCAP_DLLLARC 0x00100000 /* Data Link Layer Link Active Reporting Capable */ 395#define PCI_EXP_LNKCTL 16 /* Link Control */ 396#define PCI_EXP_LNKCTL_RL 0x0020 /* Retrain Link */ 397#define PCI_EXP_LNKSTA 18 /* Link Status */ 398#define PCI_EXP_LNKSTA_CLS 0x000f /* Current Link Speed */ 399#define PCI_EXP_LNKSTA_CLS_2_5GB 0x0001 /* Current Link Speed 2.5GT/s */ 400#define PCI_EXP_LNKSTA_CLS_5_0GB 0x0002 /* Current Link Speed 5.0GT/s */ 401#define PCI_EXP_LNKSTA_CLS_8_0GB 0x0003 /* Current Link Speed 8.0GT/s */ 402#define PCI_EXP_LNKSTA_NLW 0x03f0 /* Negotiated Link Width */ 403#define PCI_EXP_LNKSTA_NLW_SHIFT 4 /* start of NLW mask in link status */ 404#define PCI_EXP_LNKSTA_LT 0x0800 /* Link Training */ 405#define PCI_EXP_LNKSTA_DLLLA 0x2000 /* Data Link Layer Link Active */ 406#define PCI_EXP_LNKSTA_LBMS 0x4000 /* Link Bandwidth Management Status */ 407#define PCI_EXP_SLTCAP 20 /* Slot Capabilities */ 408#define PCI_EXP_SLTCAP_PSN 0xfff80000 /* Physical Slot Number */ 409#define PCI_EXP_RTCTL 28 /* Root Control */ 410#define PCI_EXP_RTCTL_CRSSVE 0x0010 /* CRS Software Visibility Enable */ 411#define PCI_EXP_RTCAP 30 /* Root Capabilities */ 412#define PCI_EXP_RTCAP_CRSVIS 0x0001 /* CRS Software Visibility capability */ 413#define PCI_EXP_DEVCAP2 36 /* Device Capabilities 2 */ 414#define PCI_EXP_DEVCAP2_ARI 0x00000020 /* ARI Forwarding Supported */ 415#define PCI_EXP_DEVCTL2 40 /* Device Control 2 */ 416#define PCI_EXP_DEVCTL2_ARI 0x0020 /* Alternative Routing-ID */ 417#define PCI_EXP_LNKCAP2 44 /* Link Capability 2 */ 418#define PCI_EXP_LNKCAP2_SLS 0x000000fe /* Supported Link Speeds Vector */ 419#define PCI_EXP_LNKCTL2 48 /* Link Control 2 */ 420#define PCI_EXP_LNKCTL2_TLS 0x000f /* Target Link Speed */ 421#define PCI_EXP_LNKCTL2_TLS_2_5GT 0x0001 /* Target Link Speed 2.5GT/s */ 422#define PCI_EXP_LNKCTL2_TLS_5_0GT 0x0002 /* Target Link Speed 5.0GT/s */ 423#define PCI_EXP_LNKCTL2_TLS_8_0GT 0x0003 /* Target Link Speed 8.0GT/s */ 424 425/* Advanced Error Reporting */ 426#define PCI_ERR_CAP 24 /* Advanced Error Capabilities */ 427#define PCI_ERR_CAP_FEP(x) ((x) & 31) /* First Error Pointer */ 428#define PCI_ERR_CAP_ECRC_GENC 0x00000020 /* ECRC Generation Capable */ 429#define PCI_ERR_CAP_ECRC_GENE 0x00000040 /* ECRC Generation Enable */ 430#define PCI_ERR_CAP_ECRC_CHKC 0x00000080 /* ECRC Check Capable */ 431#define PCI_ERR_CAP_ECRC_CHKE 0x00000100 /* ECRC Check Enable */ 432 433/* Single Root I/O Virtualization Registers */ 434#define PCI_SRIOV_CAP 0x04 /* SR-IOV Capabilities */ 435#define PCI_SRIOV_CTRL 0x08 /* SR-IOV Control */ 436#define PCI_SRIOV_CTRL_VFE 0x01 /* VF Enable */ 437#define PCI_SRIOV_CTRL_MSE 0x08 /* VF Memory Space Enable */ 438#define PCI_SRIOV_CTRL_ARI 0x10 /* ARI Capable Hierarchy */ 439#define PCI_SRIOV_INITIAL_VF 0x0c /* Initial VFs */ 440#define PCI_SRIOV_TOTAL_VF 0x0e /* Total VFs */ 441#define PCI_SRIOV_NUM_VF 0x10 /* Number of VFs */ 442#define PCI_SRIOV_VF_OFFSET 0x14 /* First VF Offset */ 443#define PCI_SRIOV_VF_STRIDE 0x16 /* Following VF Stride */ 444#define PCI_SRIOV_VF_DID 0x1a /* VF Device ID */ 445 446/* Include the ID list */ 447 448#include <pci_ids.h> 449 450/* 451 * Config Address for PCI Configuration Mechanism #1 452 * 453 * See PCI Local Bus Specification, Revision 3.0, 454 * Section 3.2.2.3.2, Figure 3-2, p. 50. 455 */ 456 457#define PCI_CONF1_BUS_SHIFT 16 /* Bus number */ 458#define PCI_CONF1_DEV_SHIFT 11 /* Device number */ 459#define PCI_CONF1_FUNC_SHIFT 8 /* Function number */ 460 461#define PCI_CONF1_BUS_MASK 0xff 462#define PCI_CONF1_DEV_MASK 0x1f 463#define PCI_CONF1_FUNC_MASK 0x7 464#define PCI_CONF1_REG_MASK 0xfc /* Limit aligned offset to a maximum of 256B */ 465 466#define PCI_CONF1_ENABLE BIT(31) 467#define PCI_CONF1_BUS(x) (((x) & PCI_CONF1_BUS_MASK) << PCI_CONF1_BUS_SHIFT) 468#define PCI_CONF1_DEV(x) (((x) & PCI_CONF1_DEV_MASK) << PCI_CONF1_DEV_SHIFT) 469#define PCI_CONF1_FUNC(x) (((x) & PCI_CONF1_FUNC_MASK) << PCI_CONF1_FUNC_SHIFT) 470#define PCI_CONF1_REG(x) ((x) & PCI_CONF1_REG_MASK) 471 472#define PCI_CONF1_ADDRESS(bus, dev, func, reg) \ 473 (PCI_CONF1_ENABLE | \ 474 PCI_CONF1_BUS(bus) | \ 475 PCI_CONF1_DEV(dev) | \ 476 PCI_CONF1_FUNC(func) | \ 477 PCI_CONF1_REG(reg)) 478 479/* 480 * Extension of PCI Config Address for accessing extended PCIe registers 481 * 482 * No standardized specification, but used on lot of non-ECAM-compliant ARM SoCs 483 * or on AMD Barcelona and new CPUs. Reserved bits [27:24] of PCI Config Address 484 * are used for specifying additional 4 high bits of PCI Express register. 485 */ 486 487#define PCI_CONF1_EXT_REG_SHIFT 16 488#define PCI_CONF1_EXT_REG_MASK 0xf00 489#define PCI_CONF1_EXT_REG(x) (((x) & PCI_CONF1_EXT_REG_MASK) << PCI_CONF1_EXT_REG_SHIFT) 490 491#define PCI_CONF1_EXT_ADDRESS(bus, dev, func, reg) \ 492 (PCI_CONF1_ADDRESS(bus, dev, func, reg) | \ 493 PCI_CONF1_EXT_REG(reg)) 494 495/* 496 * Enhanced Configuration Access Mechanism (ECAM) 497 * 498 * See PCI Express Base Specification, Revision 5.0, Version 1.0, 499 * Section 7.2.2, Table 7-1, p. 677. 500 */ 501#define PCIE_ECAM_BUS_SHIFT 20 /* Bus number */ 502#define PCIE_ECAM_DEV_SHIFT 15 /* Device number */ 503#define PCIE_ECAM_FUNC_SHIFT 12 /* Function number */ 504 505#define PCIE_ECAM_BUS_MASK 0xff 506#define PCIE_ECAM_DEV_MASK 0x1f 507#define PCIE_ECAM_FUNC_MASK 0x7 508#define PCIE_ECAM_REG_MASK 0xfff /* Limit offset to a maximum of 4K */ 509 510#define PCIE_ECAM_BUS(x) (((x) & PCIE_ECAM_BUS_MASK) << PCIE_ECAM_BUS_SHIFT) 511#define PCIE_ECAM_DEV(x) (((x) & PCIE_ECAM_DEV_MASK) << PCIE_ECAM_DEV_SHIFT) 512#define PCIE_ECAM_FUNC(x) (((x) & PCIE_ECAM_FUNC_MASK) << PCIE_ECAM_FUNC_SHIFT) 513#define PCIE_ECAM_REG(x) ((x) & PCIE_ECAM_REG_MASK) 514 515#define PCIE_ECAM_OFFSET(bus, dev, func, where) \ 516 (PCIE_ECAM_BUS(bus) | \ 517 PCIE_ECAM_DEV(dev) | \ 518 PCIE_ECAM_FUNC(func) | \ 519 PCIE_ECAM_REG(where)) 520 521#ifndef __ASSEMBLY__ 522 523#include <dm/pci.h> 524 525#ifdef CONFIG_SYS_PCI_64BIT 526typedef u64 pci_addr_t; 527typedef u64 pci_size_t; 528#else 529typedef unsigned long pci_addr_t; 530typedef unsigned long pci_size_t; 531#endif 532 533struct pci_region { 534 pci_addr_t bus_start; /* Start on the bus */ 535 phys_addr_t phys_start; /* Start in physical address space */ 536 pci_size_t size; /* Size */ 537 unsigned long flags; /* Resource flags */ 538 539 pci_addr_t bus_lower; 540}; 541 542#define PCI_REGION_MEM 0x00000000 /* PCI memory space */ 543#define PCI_REGION_IO 0x00000001 /* PCI IO space */ 544#define PCI_REGION_TYPE 0x00000001 545#define PCI_REGION_PREFETCH 0x00000008 /* prefetchable PCI memory */ 546 547#define PCI_REGION_SYS_MEMORY 0x00000100 /* System memory */ 548#define PCI_REGION_RO 0x00000200 /* Read-only memory */ 549 550static inline void pci_set_region(struct pci_region *reg, 551 pci_addr_t bus_start, 552 phys_addr_t phys_start, 553 pci_size_t size, 554 unsigned long flags) { 555 reg->bus_start = bus_start; 556 reg->phys_start = phys_start; 557 reg->size = size; 558 reg->flags = flags; 559} 560 561typedef int pci_dev_t; 562 563#define PCI_BUS(d) (((d) >> 16) & 0xff) 564 565/* 566 * Please note the difference in DEVFN usage in U-Boot vs Linux. U-Boot 567 * uses DEVFN in bits 15-8 but Linux instead expects DEVFN in bits 7-0. 568 * Please see the Linux header include/uapi/linux/pci.h for more details. 569 * This is relevant for the following macros: 570 * PCI_DEV, PCI_FUNC, PCI_DEVFN 571 * The U-Boot macro PCI_DEV is equivalent to the Linux PCI_SLOT version with 572 * the remark from above (input is in bits 15-8 instead of 7-0. 573 */ 574#define PCI_DEV(d) (((d) >> 11) & 0x1f) 575#define PCI_FUNC(d) (((d) >> 8) & 0x7) 576#define PCI_DEVFN(d, f) ((d) << 11 | (f) << 8) 577 578#define PCI_MASK_BUS(bdf) ((bdf) & 0xffff) 579#define PCI_ADD_BUS(bus, devfn) (((bus) << 16) | (devfn)) 580#define PCI_BDF(b, d, f) ((b) << 16 | PCI_DEVFN(d, f)) 581#define PCI_ANY_ID (~0) 582 583/* Convert from Linux format to U-Boot format */ 584#define PCI_TO_BDF(val) ((val) << 8) 585 586struct pci_device_id { 587 unsigned int vendor, device; /* Vendor and device ID or PCI_ANY_ID */ 588 unsigned int subvendor, subdevice; /* Subsystem ID's or PCI_ANY_ID */ 589 unsigned int class, class_mask; /* (class,subclass,prog-if) triplet */ 590 unsigned long driver_data; /* Data private to the driver */ 591}; 592 593struct pci_controller; 594 595struct pci_config_table { 596 unsigned int vendor, device; /* Vendor and device ID or PCI_ANY_ID */ 597 unsigned int class; /* Class ID, or PCI_ANY_ID */ 598 unsigned int bus; /* Bus number, or PCI_ANY_ID */ 599 unsigned int dev; /* Device number, or PCI_ANY_ID */ 600 unsigned int func; /* Function number, or PCI_ANY_ID */ 601 602 void (*config_device)(struct pci_controller* hose, pci_dev_t dev, 603 struct pci_config_table *); 604 unsigned long priv[3]; 605}; 606 607extern void pci_cfgfunc_do_nothing(struct pci_controller* hose, pci_dev_t dev, 608 struct pci_config_table *); 609extern void pci_cfgfunc_config_device(struct pci_controller* hose, pci_dev_t dev, 610 struct pci_config_table *); 611 612#define INDIRECT_TYPE_NO_PCIE_LINK 1 613 614/** 615 * Structure of a PCI controller (host bridge) 616 * 617 * With driver model this is dev_get_uclass_priv(bus) 618 * 619 * @skip_auto_config_until_reloc: true to avoid auto-config until U-Boot has 620 * relocated. Normally if PCI is used before relocation, this happens 621 * before relocation also. Some platforms set up static configuration in 622 * TPL/SPL to reduce code size and boot time, since these phases only know 623 * about a small subset of PCI devices. This is normally false. 624 */ 625struct pci_controller { 626 struct udevice *bus; 627 struct udevice *ctlr; 628 bool skip_auto_config_until_reloc; 629 630 int first_busno; 631 int last_busno; 632 633 volatile unsigned int *cfg_addr; 634 volatile unsigned char *cfg_data; 635 636 int indirect_type; 637 638 /* 639 * TODO(sjg@chromium.org): With driver model we use struct 640 * pci_controller for both the controller and any bridge devices 641 * attached to it. But there is only one region list and it is in the 642 * top-level controller. 643 * 644 * This could be changed so that struct pci_controller is only used 645 * for PCI controllers and a separate UCLASS (or perhaps 646 * UCLASS_PCI_GENERIC) is used for bridges. 647 */ 648 struct pci_region *regions; 649 int region_count; 650 651 struct pci_config_table *config_table; 652 653 void (*fixup_irq)(struct pci_controller *, pci_dev_t); 654 655 /* Used by auto config */ 656 struct pci_region *pci_mem, *pci_io, *pci_prefetch; 657}; 658 659#if defined(CONFIG_DM_PCI_COMPAT) 660extern phys_addr_t pci_hose_bus_to_phys(struct pci_controller* hose, 661 pci_addr_t addr, unsigned long flags); 662extern pci_addr_t pci_hose_phys_to_bus(struct pci_controller* hose, 663 phys_addr_t addr, unsigned long flags); 664 665#define pci_phys_to_bus(dev, addr, flags) \ 666 pci_hose_phys_to_bus(pci_bus_to_hose(PCI_BUS(dev)), (addr), (flags)) 667#define pci_bus_to_phys(dev, addr, flags) \ 668 pci_hose_bus_to_phys(pci_bus_to_hose(PCI_BUS(dev)), (addr), (flags)) 669 670#define pci_virt_to_bus(dev, addr, flags) \ 671 pci_hose_phys_to_bus(pci_bus_to_hose(PCI_BUS(dev)), \ 672 (virt_to_phys(addr)), (flags)) 673#define pci_bus_to_virt(dev, addr, flags, len, map_flags) \ 674 map_physmem(pci_hose_bus_to_phys(pci_bus_to_hose(PCI_BUS(dev)), \ 675 (addr), (flags)), \ 676 (len), (map_flags)) 677 678#define pci_phys_to_mem(dev, addr) \ 679 pci_phys_to_bus((dev), (addr), PCI_REGION_MEM) 680#define pci_mem_to_phys(dev, addr) \ 681 pci_bus_to_phys((dev), (addr), PCI_REGION_MEM) 682#define pci_phys_to_io(dev, addr) pci_phys_to_bus((dev), (addr), PCI_REGION_IO) 683#define pci_io_to_phys(dev, addr) pci_bus_to_phys((dev), (addr), PCI_REGION_IO) 684 685#define pci_virt_to_mem(dev, addr) \ 686 pci_virt_to_bus((dev), (addr), PCI_REGION_MEM) 687#define pci_mem_to_virt(dev, addr, len, map_flags) \ 688 pci_bus_to_virt((dev), (addr), PCI_REGION_MEM, (len), (map_flags)) 689#define pci_virt_to_io(dev, addr) \ 690 pci_virt_to_bus((dev), (addr), PCI_REGION_IO) 691#define pci_io_to_virt(dev, addr, len, map_flags) \ 692 pci_bus_to_virt((dev), (addr), PCI_REGION_IO, (len), (map_flags)) 693 694/* For driver model these are defined in macros in pci_compat.c */ 695extern int pci_hose_read_config_byte(struct pci_controller *hose, 696 pci_dev_t dev, int where, u8 *val); 697extern int pci_hose_read_config_word(struct pci_controller *hose, 698 pci_dev_t dev, int where, u16 *val); 699extern int pci_hose_read_config_dword(struct pci_controller *hose, 700 pci_dev_t dev, int where, u32 *val); 701extern int pci_hose_write_config_byte(struct pci_controller *hose, 702 pci_dev_t dev, int where, u8 val); 703extern int pci_hose_write_config_word(struct pci_controller *hose, 704 pci_dev_t dev, int where, u16 val); 705extern int pci_hose_write_config_dword(struct pci_controller *hose, 706 pci_dev_t dev, int where, u32 val); 707#endif 708 709void pciauto_region_init(struct pci_region *res); 710void pciauto_region_align(struct pci_region *res, pci_size_t size); 711void pciauto_config_init(struct pci_controller *hose); 712 713/** 714 * pciauto_region_allocate() - Allocate resources from a PCI resource region 715 * 716 * Allocates @size bytes from the PCI resource @res. If @supports_64bit is 717 * false, the result will be guaranteed to fit in 32 bits. 718 * 719 * @res: PCI region to allocate from 720 * @size: Amount of bytes to allocate 721 * @bar: Returns the PCI bus address of the allocated resource 722 * @supports_64bit: Whether to allow allocations above the 32-bit boundary 723 * Return: 0 if successful, -1 on failure 724 */ 725int pciauto_region_allocate(struct pci_region *res, pci_size_t size, 726 pci_addr_t *bar, bool supports_64bit); 727int pci_skip_dev(struct pci_controller *hose, pci_dev_t dev); 728 729#if defined(CONFIG_DM_PCI_COMPAT) 730extern int pci_hose_read_config_byte_via_dword(struct pci_controller *hose, 731 pci_dev_t dev, int where, u8 *val); 732extern int pci_hose_read_config_word_via_dword(struct pci_controller *hose, 733 pci_dev_t dev, int where, u16 *val); 734extern int pci_hose_write_config_byte_via_dword(struct pci_controller *hose, 735 pci_dev_t dev, int where, u8 val); 736extern int pci_hose_write_config_word_via_dword(struct pci_controller *hose, 737 pci_dev_t dev, int where, u16 val); 738 739extern void *pci_map_bar(pci_dev_t pdev, int bar, int flags); 740extern void pci_register_hose(struct pci_controller* hose); 741extern struct pci_controller* pci_bus_to_hose(int bus); 742extern struct pci_controller *find_hose_by_cfg_addr(void *cfg_addr); 743extern struct pci_controller *pci_get_hose_head(void); 744 745extern int pci_hose_scan(struct pci_controller *hose); 746extern int pci_hose_scan_bus(struct pci_controller *hose, int bus); 747 748extern void pciauto_setup_device(struct pci_controller *hose, 749 pci_dev_t dev, int bars_num, 750 struct pci_region *mem, 751 struct pci_region *prefetch, 752 struct pci_region *io); 753extern void pciauto_prescan_setup_bridge(struct pci_controller *hose, 754 pci_dev_t dev, int sub_bus); 755extern void pciauto_postscan_setup_bridge(struct pci_controller *hose, 756 pci_dev_t dev, int sub_bus); 757extern int pciauto_config_device(struct pci_controller *hose, pci_dev_t dev); 758 759extern pci_dev_t pci_find_device (unsigned int vendor, unsigned int device, int index); 760extern pci_dev_t pci_find_devices (struct pci_device_id *ids, int index); 761pci_dev_t pci_find_class(unsigned int find_class, int index); 762 763extern int pci_hose_find_capability(struct pci_controller *hose, pci_dev_t dev, 764 int cap); 765extern int pci_hose_find_cap_start(struct pci_controller *hose, pci_dev_t dev, 766 u8 hdr_type); 767extern int pci_find_cap(struct pci_controller *hose, pci_dev_t dev, int pos, 768 int cap); 769 770int pci_find_next_ext_capability(struct pci_controller *hose, 771 pci_dev_t dev, int start, int cap); 772int pci_hose_find_ext_capability(struct pci_controller *hose, 773 pci_dev_t dev, int cap); 774 775#endif /* defined(CONFIG_DM_PCI_COMPAT) */ 776 777const char * pci_class_str(u8 class); 778int pci_last_busno(void); 779 780#ifdef CONFIG_MPC85xx 781extern void pci_mpc85xx_init (struct pci_controller *hose); 782#endif 783 784/** 785 * pci_write_bar32() - Write the address of a BAR including control bits 786 * 787 * This writes a raw address (with control bits) to a bar. This can be used 788 * with devices which require hard-coded addresses, not part of the normal 789 * PCI enumeration process. 790 * 791 * This is only available if CONFIG_DM_PCI_COMPAT is enabled 792 * 793 * @hose: PCI hose to use 794 * @dev: PCI device to update 795 * @barnum: BAR number (0-5) 796 * @addr: BAR address with control bits 797 */ 798void pci_write_bar32(struct pci_controller *hose, pci_dev_t dev, int barnum, 799 u32 addr); 800 801/** 802 * pci_read_bar32() - read the address of a bar 803 * 804 * This is only available if CONFIG_DM_PCI_COMPAT is enabled 805 * 806 * @hose: PCI hose to use 807 * @dev: PCI device to inspect 808 * @barnum: BAR number (0-5) 809 * Return: address of the bar, masking out any control bits 810 * */ 811u32 pci_read_bar32(struct pci_controller *hose, pci_dev_t dev, int barnum); 812 813/** 814 * pci_hose_find_devices() - Find devices by vendor/device ID 815 * 816 * This is only available if CONFIG_DM_PCI_COMPAT is enabled 817 * 818 * @hose: PCI hose to search 819 * @busnum: Bus number to search 820 * @ids: PCI vendor/device IDs to look for, terminated by 0, 0 record 821 * @indexp: Pointer to device index to find. To find the first matching 822 * device, pass 0; to find the second, pass 1, etc. This 823 * parameter is decremented for each non-matching device so 824 * can be called repeatedly. 825 */ 826pci_dev_t pci_hose_find_devices(struct pci_controller *hose, int busnum, 827 struct pci_device_id *ids, int *indexp); 828 829/* Access sizes for PCI reads and writes */ 830enum pci_size_t { 831 PCI_SIZE_8, 832 PCI_SIZE_16, 833 PCI_SIZE_32, 834}; 835 836struct udevice; 837 838/** 839 * struct pci_child_plat - information stored about each PCI device 840 * 841 * Every device on a PCI bus has this per-child data. 842 * 843 * It can be accessed using dev_get_parent_plat(dev) if dev->parent is a 844 * PCI bus (i.e. UCLASS_PCI) 845 * 846 * @devfn: Encoded device and function index - see PCI_DEVFN() 847 * @vendor: PCI vendor ID (see pci_ids.h) 848 * @device: PCI device ID (see pci_ids.h) 849 * @class: PCI class, 3 bytes: (base, sub, prog-if) 850 * @is_virtfn: True for Virtual Function device 851 * @pfdev: Handle to Physical Function device 852 * @virtid: Virtual Function Index 853 */ 854struct pci_child_plat { 855 int devfn; 856 unsigned short vendor; 857 unsigned short device; 858 unsigned int class; 859 860 /* Variables for CONFIG_PCI_SRIOV */ 861 bool is_virtfn; 862 struct udevice *pfdev; 863 int virtid; 864}; 865 866/* PCI bus operations */ 867struct dm_pci_ops { 868 /** 869 * read_config() - Read a PCI configuration value 870 * 871 * PCI buses must support reading and writing configuration values 872 * so that the bus can be scanned and its devices configured. 873 * 874 * Normally PCI_BUS(@bdf) is the same as @dev_seq(bus), but not always. 875 * If bridges exist it is possible to use the top-level bus to 876 * access a sub-bus. In that case @bus will be the top-level bus 877 * and PCI_BUS(bdf) will be a different (higher) value 878 * 879 * @bus: Bus to read from 880 * @bdf: Bus, device and function to read 881 * @offset: Byte offset within the device's configuration space 882 * @valuep: Place to put the returned value 883 * @size: Access size 884 * @return 0 if OK, -ve on error 885 */ 886 int (*read_config)(const struct udevice *bus, pci_dev_t bdf, 887 uint offset, ulong *valuep, enum pci_size_t size); 888 /** 889 * write_config() - Write a PCI configuration value 890 * 891 * @bus: Bus to write to 892 * @bdf: Bus, device and function to write 893 * @offset: Byte offset within the device's configuration space 894 * @value: Value to write 895 * @size: Access size 896 * @return 0 if OK, -ve on error 897 */ 898 int (*write_config)(struct udevice *bus, pci_dev_t bdf, uint offset, 899 ulong value, enum pci_size_t size); 900}; 901 902/* Get access to a PCI bus' operations */ 903#define pci_get_ops(dev) ((struct dm_pci_ops *)(dev)->driver->ops) 904 905/** 906 * dm_pci_get_bdf() - Get the BDF value for a device 907 * 908 * @dev: Device to check 909 * Return: bus/device/function value (see PCI_BDF()) 910 */ 911pci_dev_t dm_pci_get_bdf(const struct udevice *dev); 912 913/** 914 * pci_bind_bus_devices() - scan a PCI bus and bind devices 915 * 916 * Scan a PCI bus looking for devices. Bind each one that is found. If 917 * devices are already bound that match the scanned devices, just update the 918 * child data so that the device can be used correctly (this happens when 919 * the device tree describes devices we expect to see on the bus). 920 * 921 * Devices that are bound in this way will use a generic PCI driver which 922 * does nothing. The device can still be accessed but will not provide any 923 * driver interface. 924 * 925 * @bus: Bus containing devices to bind 926 * Return: 0 if OK, -ve on error 927 */ 928int pci_bind_bus_devices(struct udevice *bus); 929 930/** 931 * pci_auto_config_devices() - configure bus devices ready for use 932 * 933 * This works through all devices on a bus by scanning the driver model 934 * data structures (normally these have been set up by pci_bind_bus_devices() 935 * earlier). 936 * 937 * Space is allocated for each PCI base address register (BAR) so that the 938 * devices are mapped into memory and I/O space ready for use. 939 * 940 * @bus: Bus containing devices to bind 941 * Return: 0 if OK, -ve on error 942 */ 943int pci_auto_config_devices(struct udevice *bus); 944 945/** 946 * dm_pci_bus_find_bdf() - Find a device given its PCI bus address 947 * 948 * @bdf: PCI device address: bus, device and function -see PCI_BDF() 949 * @devp: Returns the device for this address, if found 950 * Return: 0 if OK, -ENODEV if not found 951 */ 952int dm_pci_bus_find_bdf(pci_dev_t bdf, struct udevice **devp); 953 954/** 955 * pci_bus_find_devfn() - Find a device on a bus 956 * 957 * @find_devfn: PCI device address (device and function only) 958 * @devp: Returns the device for this address, if found 959 * Return: 0 if OK, -ENODEV if not found 960 */ 961int pci_bus_find_devfn(const struct udevice *bus, pci_dev_t find_devfn, 962 struct udevice **devp); 963 964/** 965 * pci_find_first_device() - return the first available PCI device 966 * 967 * This function and pci_find_next_device() allow iteration through all 968 * available PCI devices on all buses. Assuming there are any, this will 969 * return the first one. 970 * 971 * @devp: Set to the first available device, or NULL if no more are left 972 * or we got an error 973 * Return: 0 if all is OK, -ve on error (e.g. a bus/bridge failed to probe) 974 */ 975int pci_find_first_device(struct udevice **devp); 976 977/** 978 * pci_find_next_device() - return the next available PCI device 979 * 980 * Finds the next available PCI device after the one supplied, or sets @devp 981 * to NULL if there are no more. 982 * 983 * @devp: On entry, the last device returned. Set to the next available 984 * device, or NULL if no more are left or we got an error 985 * Return: 0 if all is OK, -ve on error (e.g. a bus/bridge failed to probe) 986 */ 987int pci_find_next_device(struct udevice **devp); 988 989/** 990 * pci_get_ff() - Returns a mask for the given access size 991 * 992 * @size: Access size 993 * Return: 0xff for PCI_SIZE_8, 0xffff for PCI_SIZE_16, 0xffffffff for 994 * PCI_SIZE_32 995 */ 996int pci_get_ff(enum pci_size_t size); 997 998/** 999 * pci_bus_find_devices () - Find devices on a bus 1000 * 1001 * @bus: Bus to search 1002 * @ids: PCI vendor/device IDs to look for, terminated by 0, 0 record 1003 * @indexp: Pointer to device index to find. To find the first matching 1004 * device, pass 0; to find the second, pass 1, etc. This 1005 * parameter is decremented for each non-matching device so 1006 * can be called repeatedly. 1007 * @devp: Returns matching device if found 1008 * Return: 0 if found, -ENODEV if not 1009 */ 1010int pci_bus_find_devices(struct udevice *bus, const struct pci_device_id *ids, 1011 int *indexp, struct udevice **devp); 1012 1013/** 1014 * pci_find_device_id() - Find a device on any bus 1015 * 1016 * @ids: PCI vendor/device IDs to look for, terminated by 0, 0 record 1017 * @index: Index number of device to find, 0 for the first match, 1 for 1018 * the second, etc. 1019 * @devp: Returns matching device if found 1020 * Return: 0 if found, -ENODEV if not 1021 */ 1022int pci_find_device_id(const struct pci_device_id *ids, int index, 1023 struct udevice **devp); 1024 1025/** 1026 * dm_pci_hose_probe_bus() - probe a subordinate bus, scanning it for devices 1027 * 1028 * This probes the given bus which causes it to be scanned for devices. The 1029 * devices will be bound but not probed. 1030 * 1031 * @hose specifies the PCI hose that will be used for the scan. This is 1032 * always a top-level bus with uclass UCLASS_PCI. The bus to scan is 1033 * in @bdf, and is a subordinate bus reachable from @hose. 1034 * 1035 * @hose: PCI hose to scan 1036 * @bdf: PCI bus address to scan (PCI_BUS(bdf) is the bus number) 1037 * Return: 0 if OK, -ve on error 1038 */ 1039int dm_pci_hose_probe_bus(struct udevice *bus); 1040 1041/** 1042 * pci_bus_read_config() - Read a configuration value from a device 1043 * 1044 * TODO(sjg@chromium.org): We should be able to pass just a device and have 1045 * it do the right thing. It would be good to have that function also. 1046 * 1047 * @bus: Bus to read from 1048 * @bdf: PCI device address: bus, device and function -see PCI_BDF() 1049 * @offset: Register offset to read 1050 * @valuep: Place to put the returned value 1051 * @size: Access size 1052 * Return: 0 if OK, -ve on error 1053 */ 1054int pci_bus_read_config(const struct udevice *bus, pci_dev_t bdf, int offset, 1055 unsigned long *valuep, enum pci_size_t size); 1056 1057/** 1058 * pci_bus_write_config() - Write a configuration value to a device 1059 * 1060 * @bus: Bus to write from 1061 * @bdf: PCI device address: bus, device and function -see PCI_BDF() 1062 * @offset: Register offset to write 1063 * @value: Value to write 1064 * @size: Access size 1065 * Return: 0 if OK, -ve on error 1066 */ 1067int pci_bus_write_config(struct udevice *bus, pci_dev_t bdf, int offset, 1068 unsigned long value, enum pci_size_t size); 1069 1070/** 1071 * pci_bus_clrset_config32() - Update a configuration value for a device 1072 * 1073 * The register at @offset is updated to (oldvalue & ~clr) | set. 1074 * 1075 * @bus: Bus to access 1076 * @bdf: PCI device address: bus, device and function -see PCI_BDF() 1077 * @offset: Register offset to update 1078 * @clr: Bits to clear 1079 * @set: Bits to set 1080 * Return: 0 if OK, -ve on error 1081 */ 1082int pci_bus_clrset_config32(struct udevice *bus, pci_dev_t bdf, int offset, 1083 u32 clr, u32 set); 1084 1085/** 1086 * Driver model PCI config access functions. Use these in preference to others 1087 * when you have a valid device 1088 */ 1089int dm_pci_read_config(const struct udevice *dev, int offset, 1090 unsigned long *valuep, enum pci_size_t size); 1091 1092int dm_pci_read_config8(const struct udevice *dev, int offset, u8 *valuep); 1093int dm_pci_read_config16(const struct udevice *dev, int offset, u16 *valuep); 1094int dm_pci_read_config32(const struct udevice *dev, int offset, u32 *valuep); 1095 1096int dm_pci_write_config(struct udevice *dev, int offset, unsigned long value, 1097 enum pci_size_t size); 1098 1099int dm_pci_write_config8(struct udevice *dev, int offset, u8 value); 1100int dm_pci_write_config16(struct udevice *dev, int offset, u16 value); 1101int dm_pci_write_config32(struct udevice *dev, int offset, u32 value); 1102 1103/** 1104 * These permit convenient read/modify/write on PCI configuration. The 1105 * register is updated to (oldvalue & ~clr) | set. 1106 */ 1107int dm_pci_clrset_config8(struct udevice *dev, int offset, u32 clr, u32 set); 1108int dm_pci_clrset_config16(struct udevice *dev, int offset, u32 clr, u32 set); 1109int dm_pci_clrset_config32(struct udevice *dev, int offset, u32 clr, u32 set); 1110 1111/* 1112 * The following functions provide access to the above without needing the 1113 * size parameter. We are trying to encourage the use of the 8/16/32-style 1114 * functions, rather than byte/word/dword. But both are supported. 1115 */ 1116int pci_write_config32(pci_dev_t pcidev, int offset, u32 value); 1117int pci_write_config16(pci_dev_t pcidev, int offset, u16 value); 1118int pci_write_config8(pci_dev_t pcidev, int offset, u8 value); 1119int pci_read_config32(pci_dev_t pcidev, int offset, u32 *valuep); 1120int pci_read_config16(pci_dev_t pcidev, int offset, u16 *valuep); 1121int pci_read_config8(pci_dev_t pcidev, int offset, u8 *valuep); 1122 1123/** 1124 * pci_generic_mmap_write_config() - Generic helper for writing to 1125 * memory-mapped PCI configuration space. 1126 * @bus: Pointer to the PCI bus 1127 * @addr_f: Callback for calculating the config space address 1128 * @bdf: Identifies the PCI device to access 1129 * @offset: The offset into the device's configuration space 1130 * @value: The value to write 1131 * @size: Indicates the size of access to perform 1132 * 1133 * Write the value @value of size @size from offset @offset within the 1134 * configuration space of the device identified by the bus, device & function 1135 * numbers in @bdf on the PCI bus @bus. The callback function @addr_f is 1136 * responsible for calculating the CPU address of the respective configuration 1137 * space offset. 1138 * 1139 * Return: 0 on success, else -EINVAL 1140 */ 1141int pci_generic_mmap_write_config( 1142 const struct udevice *bus, 1143 int (*addr_f)(const struct udevice *bus, pci_dev_t bdf, uint offset, 1144 void **addrp), 1145 pci_dev_t bdf, 1146 uint offset, 1147 ulong value, 1148 enum pci_size_t size); 1149 1150/** 1151 * pci_generic_mmap_read_config() - Generic helper for reading from 1152 * memory-mapped PCI configuration space. 1153 * @bus: Pointer to the PCI bus 1154 * @addr_f: Callback for calculating the config space address 1155 * @bdf: Identifies the PCI device to access 1156 * @offset: The offset into the device's configuration space 1157 * @valuep: A pointer at which to store the read value 1158 * @size: Indicates the size of access to perform 1159 * 1160 * Read a value of size @size from offset @offset within the configuration 1161 * space of the device identified by the bus, device & function numbers in @bdf 1162 * on the PCI bus @bus. The callback function @addr_f is responsible for 1163 * calculating the CPU address of the respective configuration space offset. 1164 * 1165 * Return: 0 on success, else -EINVAL 1166 */ 1167int pci_generic_mmap_read_config( 1168 const struct udevice *bus, 1169 int (*addr_f)(const struct udevice *bus, pci_dev_t bdf, uint offset, 1170 void **addrp), 1171 pci_dev_t bdf, 1172 uint offset, 1173 ulong *valuep, 1174 enum pci_size_t size); 1175 1176#if defined(CONFIG_PCI_SRIOV) 1177/** 1178 * pci_sriov_init() - Scan Virtual Function devices 1179 * 1180 * @pdev: Physical Function udevice handle 1181 * @vf_en: Number of Virtual Function devices to enable 1182 * Return: 0 on success, -ve on error 1183 */ 1184int pci_sriov_init(struct udevice *pdev, int vf_en); 1185 1186/** 1187 * pci_sriov_get_totalvfs() - Get total available Virtual Function devices 1188 * 1189 * @pdev: Physical Function udevice handle 1190 * Return: count on success, -ve on error 1191 */ 1192int pci_sriov_get_totalvfs(struct udevice *pdev); 1193#endif 1194 1195#ifdef CONFIG_DM_PCI_COMPAT 1196/* Compatibility with old naming */ 1197static inline int pci_write_config_dword(pci_dev_t pcidev, int offset, 1198 u32 value) 1199{ 1200 return pci_write_config32(pcidev, offset, value); 1201} 1202 1203/* Compatibility with old naming */ 1204static inline int pci_write_config_word(pci_dev_t pcidev, int offset, 1205 u16 value) 1206{ 1207 return pci_write_config16(pcidev, offset, value); 1208} 1209 1210/* Compatibility with old naming */ 1211static inline int pci_write_config_byte(pci_dev_t pcidev, int offset, 1212 u8 value) 1213{ 1214 return pci_write_config8(pcidev, offset, value); 1215} 1216 1217/* Compatibility with old naming */ 1218static inline int pci_read_config_dword(pci_dev_t pcidev, int offset, 1219 u32 *valuep) 1220{ 1221 return pci_read_config32(pcidev, offset, valuep); 1222} 1223 1224/* Compatibility with old naming */ 1225static inline int pci_read_config_word(pci_dev_t pcidev, int offset, 1226 u16 *valuep) 1227{ 1228 return pci_read_config16(pcidev, offset, valuep); 1229} 1230 1231/* Compatibility with old naming */ 1232static inline int pci_read_config_byte(pci_dev_t pcidev, int offset, 1233 u8 *valuep) 1234{ 1235 return pci_read_config8(pcidev, offset, valuep); 1236} 1237#endif /* CONFIG_DM_PCI_COMPAT */ 1238 1239/** 1240 * dm_pciauto_config_device() - configure a device ready for use 1241 * 1242 * Space is allocated for each PCI base address register (BAR) so that the 1243 * devices are mapped into memory and I/O space ready for use. 1244 * 1245 * @dev: Device to configure 1246 * Return: 0 if OK, -ve on error 1247 */ 1248int dm_pciauto_config_device(struct udevice *dev); 1249 1250/** 1251 * pci_conv_32_to_size() - convert a 32-bit read value to the given size 1252 * 1253 * Some PCI buses must always perform 32-bit reads. The data must then be 1254 * shifted and masked to reflect the required access size and offset. This 1255 * function performs this transformation. 1256 * 1257 * @value: Value to transform (32-bit value read from @offset & ~3) 1258 * @offset: Register offset that was read 1259 * @size: Required size of the result 1260 * Return: the value that would have been obtained if the read had been 1261 * performed at the given offset with the correct size 1262 */ 1263ulong pci_conv_32_to_size(ulong value, uint offset, enum pci_size_t size); 1264 1265/** 1266 * pci_conv_size_to_32() - update a 32-bit value to prepare for a write 1267 * 1268 * Some PCI buses must always perform 32-bit writes. To emulate a smaller 1269 * write the old 32-bit data must be read, updated with the required new data 1270 * and written back as a 32-bit value. This function performs the 1271 * transformation from the old value to the new value. 1272 * 1273 * @value: Value to transform (32-bit value read from @offset & ~3) 1274 * @offset: Register offset that should be written 1275 * @size: Required size of the write 1276 * Return: the value that should be written as a 32-bit access to @offset & ~3. 1277 */ 1278ulong pci_conv_size_to_32(ulong old, ulong value, uint offset, 1279 enum pci_size_t size); 1280 1281/** 1282 * pci_get_controller() - obtain the controller to use for a bus 1283 * 1284 * @dev: Device to check 1285 * Return: pointer to the controller device for this bus 1286 */ 1287struct udevice *pci_get_controller(struct udevice *dev); 1288 1289/** 1290 * pci_get_regions() - obtain pointers to all the region types 1291 * 1292 * @dev: Device to check 1293 * @iop: Returns a pointer to the I/O region, or NULL if none 1294 * @memp: Returns a pointer to the memory region, or NULL if none 1295 * @prefp: Returns a pointer to the pre-fetch region, or NULL if none 1296 * Return: the number of non-NULL regions returned, normally 3 1297 */ 1298int pci_get_regions(struct udevice *dev, struct pci_region **iop, 1299 struct pci_region **memp, struct pci_region **prefp); 1300int 1301pci_get_dma_regions(struct udevice *dev, struct pci_region *memp, int index); 1302/** 1303 * dm_pci_write_bar32() - Write the address of a BAR 1304 * 1305 * This writes a raw address to a bar 1306 * 1307 * @dev: PCI device to update 1308 * @barnum: BAR number (0-5) 1309 * @addr: BAR address 1310 */ 1311void dm_pci_write_bar32(struct udevice *dev, int barnum, u32 addr); 1312 1313/** 1314 * dm_pci_read_bar32() - read a base address register from a device 1315 * 1316 * @dev: Device to check 1317 * @barnum: Bar number to read (numbered from 0) 1318 * @return: value of BAR 1319 */ 1320u32 dm_pci_read_bar32(const struct udevice *dev, int barnum); 1321 1322/** 1323 * dm_pci_bus_to_phys() - convert a PCI bus address range to a physical address 1324 * 1325 * @dev: Device containing the PCI address 1326 * @addr: PCI address to convert 1327 * @len: Length of the address range 1328 * @mask: Mask to match flags for the region type 1329 * @flags: Flags for the region type (PCI_REGION_...) 1330 * Return: physical address corresponding to that PCI bus address 1331 */ 1332phys_addr_t dm_pci_bus_to_phys(struct udevice *dev, pci_addr_t addr, size_t len, 1333 unsigned long mask, unsigned long flags); 1334 1335/** 1336 * dm_pci_phys_to_bus() - convert a physical address to a PCI bus address 1337 * 1338 * @dev: Device containing the bus address 1339 * @addr: Physical address to convert 1340 * @len: Length of the address range 1341 * @mask: Mask to match flags for the region type 1342 * @flags: Flags for the region type (PCI_REGION_...) 1343 * Return: PCI bus address corresponding to that physical address 1344 */ 1345pci_addr_t dm_pci_phys_to_bus(struct udevice *dev, phys_addr_t addr, size_t len, 1346 unsigned long mask, unsigned long flags); 1347 1348/** 1349 * dm_pci_map_bar() - get a virtual address associated with a BAR region 1350 * 1351 * Looks up a base address register and finds the physical memory address 1352 * that corresponds to it. 1353 * Can be used for 32b BARs 0-5 on type 0 functions and for 32b BARs 0-1 on 1354 * type 1 functions. 1355 * Can also be used on type 0 functions that support Enhanced Allocation for 1356 * 32b/64b BARs. Note that duplicate BEI entries are not supported. 1357 * Can also be used on 64b bars on type 0 functions. 1358 * 1359 * @dev: Device to check 1360 * @bar: Bar register offset (PCI_BASE_ADDRESS_...) 1361 * @offset: Offset from the base to map 1362 * @len: Length to map 1363 * @mask: Mask to match flags for the region type 1364 * @flags: Flags for the region type (PCI_REGION_...) 1365 * @return: pointer to the virtual address to use or 0 on error 1366 */ 1367void *dm_pci_map_bar(struct udevice *dev, int bar, size_t offset, size_t len, 1368 unsigned long mask, unsigned long flags); 1369 1370/** 1371 * dm_pci_find_next_capability() - find a capability starting from an offset 1372 * 1373 * Tell if a device supports a given PCI capability. Returns the 1374 * address of the requested capability structure within the device's 1375 * PCI configuration space or 0 in case the device does not support it. 1376 * 1377 * Possible values for @cap: 1378 * 1379 * %PCI_CAP_ID_MSI Message Signalled Interrupts 1380 * %PCI_CAP_ID_PCIX PCI-X 1381 * %PCI_CAP_ID_EXP PCI Express 1382 * %PCI_CAP_ID_MSIX MSI-X 1383 * 1384 * See PCI_CAP_ID_xxx for the complete capability ID codes. 1385 * 1386 * @dev: PCI device to query 1387 * @start: offset to start from 1388 * @cap: capability code 1389 * @return: capability address or 0 if not supported 1390 */ 1391int dm_pci_find_next_capability(struct udevice *dev, u8 start, int cap); 1392 1393/** 1394 * dm_pci_find_capability() - find a capability 1395 * 1396 * Tell if a device supports a given PCI capability. Returns the 1397 * address of the requested capability structure within the device's 1398 * PCI configuration space or 0 in case the device does not support it. 1399 * 1400 * Possible values for @cap: 1401 * 1402 * %PCI_CAP_ID_MSI Message Signalled Interrupts 1403 * %PCI_CAP_ID_PCIX PCI-X 1404 * %PCI_CAP_ID_EXP PCI Express 1405 * %PCI_CAP_ID_MSIX MSI-X 1406 * 1407 * See PCI_CAP_ID_xxx for the complete capability ID codes. 1408 * 1409 * @dev: PCI device to query 1410 * @cap: capability code 1411 * @return: capability address or 0 if not supported 1412 */ 1413int dm_pci_find_capability(struct udevice *dev, int cap); 1414 1415/** 1416 * dm_pci_find_next_ext_capability() - find an extended capability 1417 * starting from an offset 1418 * 1419 * Tell if a device supports a given PCI express extended capability. 1420 * Returns the address of the requested extended capability structure 1421 * within the device's PCI configuration space or 0 in case the device 1422 * does not support it. 1423 * 1424 * Possible values for @cap: 1425 * 1426 * %PCI_EXT_CAP_ID_ERR Advanced Error Reporting 1427 * %PCI_EXT_CAP_ID_VC Virtual Channel 1428 * %PCI_EXT_CAP_ID_DSN Device Serial Number 1429 * %PCI_EXT_CAP_ID_PWR Power Budgeting 1430 * 1431 * See PCI_EXT_CAP_ID_xxx for the complete extended capability ID codes. 1432 * 1433 * @dev: PCI device to query 1434 * @start: offset to start from 1435 * @cap: extended capability code 1436 * @return: extended capability address or 0 if not supported 1437 */ 1438int dm_pci_find_next_ext_capability(struct udevice *dev, int start, int cap); 1439 1440/** 1441 * dm_pci_find_ext_capability() - find an extended capability 1442 * 1443 * Tell if a device supports a given PCI express extended capability. 1444 * Returns the address of the requested extended capability structure 1445 * within the device's PCI configuration space or 0 in case the device 1446 * does not support it. 1447 * 1448 * Possible values for @cap: 1449 * 1450 * %PCI_EXT_CAP_ID_ERR Advanced Error Reporting 1451 * %PCI_EXT_CAP_ID_VC Virtual Channel 1452 * %PCI_EXT_CAP_ID_DSN Device Serial Number 1453 * %PCI_EXT_CAP_ID_PWR Power Budgeting 1454 * 1455 * See PCI_EXT_CAP_ID_xxx for the complete extended capability ID codes. 1456 * 1457 * @dev: PCI device to query 1458 * @cap: extended capability code 1459 * @return: extended capability address or 0 if not supported 1460 */ 1461int dm_pci_find_ext_capability(struct udevice *dev, int cap); 1462 1463/** 1464 * dm_pci_flr() - Perform FLR if the device suppoorts it 1465 * 1466 * @dev: PCI device to reset 1467 * @return: 0 if OK, -ENOENT if FLR is not supported by dev 1468 */ 1469int dm_pci_flr(struct udevice *dev); 1470 1471#define dm_pci_virt_to_bus(dev, addr, flags) \ 1472 dm_pci_phys_to_bus(dev, (virt_to_phys(addr)), 0, PCI_REGION_TYPE, (flags)) 1473#define dm_pci_bus_to_virt(dev, addr, len, mask, flags, map_flags) \ 1474({ \ 1475 size_t _len = (len); \ 1476 phys_addr_t phys_addr = dm_pci_bus_to_phys((dev), (addr), _len, \ 1477 (mask), (flags)); \ 1478 map_physmem(phys_addr, _len, (map_flags)); \ 1479}) 1480 1481#define dm_pci_phys_to_mem(dev, addr) \ 1482 dm_pci_phys_to_bus((dev), (addr), 0, PCI_REGION_TYPE, PCI_REGION_MEM) 1483#define dm_pci_mem_to_phys(dev, addr) \ 1484 dm_pci_bus_to_phys((dev), (addr), 0, PCI_REGION_TYPE, PCI_REGION_MEM) 1485#define dm_pci_phys_to_io(dev, addr) \ 1486 dm_pci_phys_to_bus((dev), (addr), 0, PCI_REGION_TYPE, PCI_REGION_IO) 1487#define dm_pci_io_to_phys(dev, addr) \ 1488 dm_pci_bus_to_phys((dev), (addr), 0, PCI_REGION_TYPE, PCI_REGION_IO) 1489 1490#define dm_pci_virt_to_mem(dev, addr) \ 1491 dm_pci_virt_to_bus((dev), (addr), PCI_REGION_MEM) 1492#define dm_pci_mem_to_virt(dev, addr, len, map_flags) \ 1493 dm_pci_bus_to_virt((dev), (addr), (len), PCI_REGION_TYPE, \ 1494 PCI_REGION_MEM, (map_flags)) 1495#define dm_pci_virt_to_io(dev, addr) \ 1496 dm_pci_virt_to_bus((dev), (addr), PCI_REGION_IO) 1497#define dm_pci_io_to_virt(dev, addr, len, map_flags) \ 1498 dm_pci_bus_to_virt((dev), (addr), (len), PCI_REGION_TYPE, \ 1499 PCI_REGION_IO, (map_flags)) 1500 1501/** 1502 * dm_pci_find_device() - find a device by vendor/device ID 1503 * 1504 * @vendor: Vendor ID 1505 * @device: Device ID 1506 * @index: 0 to find the first match, 1 for second, etc. 1507 * @devp: Returns pointer to the device, if found 1508 * Return: 0 if found, -ve on error 1509 */ 1510int dm_pci_find_device(unsigned int vendor, unsigned int device, int index, 1511 struct udevice **devp); 1512 1513/** 1514 * dm_pci_find_class() - find a device by class 1515 * 1516 * @find_class: 3-byte (24-bit) class value to find 1517 * @index: 0 to find the first match, 1 for second, etc. 1518 * @devp: Returns pointer to the device, if found 1519 * Return: 0 if found, -ve on error 1520 */ 1521int dm_pci_find_class(uint find_class, int index, struct udevice **devp); 1522 1523/** 1524 * struct pci_emul_uc_priv - holds info about an emulator device 1525 * 1526 * There is always at most one emulator per client 1527 * 1528 * @client: Client device if any, else NULL 1529 */ 1530struct pci_emul_uc_priv { 1531 struct udevice *client; 1532}; 1533 1534/** 1535 * struct dm_pci_emul_ops - PCI device emulator operations 1536 */ 1537struct dm_pci_emul_ops { 1538 /** 1539 * read_config() - Read a PCI configuration value 1540 * 1541 * @dev: Emulated device to read from 1542 * @offset: Byte offset within the device's configuration space 1543 * @valuep: Place to put the returned value 1544 * @size: Access size 1545 * @return 0 if OK, -ve on error 1546 */ 1547 int (*read_config)(const struct udevice *dev, uint offset, 1548 ulong *valuep, enum pci_size_t size); 1549 /** 1550 * write_config() - Write a PCI configuration value 1551 * 1552 * @dev: Emulated device to write to 1553 * @offset: Byte offset within the device's configuration space 1554 * @value: Value to write 1555 * @size: Access size 1556 * @return 0 if OK, -ve on error 1557 */ 1558 int (*write_config)(struct udevice *dev, uint offset, ulong value, 1559 enum pci_size_t size); 1560 /** 1561 * read_io() - Read a PCI I/O value 1562 * 1563 * @dev: Emulated device to read from 1564 * @addr: I/O address to read 1565 * @valuep: Place to put the returned value 1566 * @size: Access size 1567 * @return 0 if OK, -ENOENT if @addr is not mapped by this device, 1568 * other -ve value on error 1569 */ 1570 int (*read_io)(struct udevice *dev, unsigned int addr, ulong *valuep, 1571 enum pci_size_t size); 1572 /** 1573 * write_io() - Write a PCI I/O value 1574 * 1575 * @dev: Emulated device to write from 1576 * @addr: I/O address to write 1577 * @value: Value to write 1578 * @size: Access size 1579 * @return 0 if OK, -ENOENT if @addr is not mapped by this device, 1580 * other -ve value on error 1581 */ 1582 int (*write_io)(struct udevice *dev, unsigned int addr, 1583 ulong value, enum pci_size_t size); 1584 /** 1585 * map_physmem() - Map a device into sandbox memory 1586 * 1587 * @dev: Emulated device to map 1588 * @addr: Memory address, normally corresponding to a PCI BAR. 1589 * The device should have been configured to have a BAR 1590 * at this address. 1591 * @lenp: On entry, the size of the area to map, On exit it is 1592 * updated to the size actually mapped, which may be less 1593 * if the device has less space 1594 * @ptrp: Returns a pointer to the mapped address. The device's 1595 * space can be accessed as @lenp bytes starting here 1596 * @return 0 if OK, -ENOENT if @addr is not mapped by this device, 1597 * other -ve value on error 1598 */ 1599 int (*map_physmem)(struct udevice *dev, phys_addr_t addr, 1600 unsigned long *lenp, void **ptrp); 1601 /** 1602 * unmap_physmem() - undo a memory mapping 1603 * 1604 * This must be called after map_physmem() to undo the mapping. 1605 * Some devices can use this to check what has been written into 1606 * their mapped memory and perform an operations they require on it. 1607 * In this way, map/unmap can be used as a sort of handshake between 1608 * the emulated device and its users. 1609 * 1610 * @dev: Emuated device to unmap 1611 * @vaddr: Mapped memory address, as passed to map_physmem() 1612 * @len: Size of area mapped, as returned by map_physmem() 1613 * @return 0 if OK, -ve on error 1614 */ 1615 int (*unmap_physmem)(struct udevice *dev, const void *vaddr, 1616 unsigned long len); 1617}; 1618 1619/* Get access to a PCI device emulator's operations */ 1620#define pci_get_emul_ops(dev) ((struct dm_pci_emul_ops *)(dev)->driver->ops) 1621 1622/** 1623 * sandbox_pci_get_emul() - Get the emulation device for a PCI device 1624 * 1625 * Searches for a suitable emulator for the given PCI bus device 1626 * 1627 * @bus: PCI bus to search 1628 * @find_devfn: PCI device and function address (PCI_DEVFN()) 1629 * @containerp: Returns container device if found 1630 * @emulp: Returns emulated device if found 1631 * Return: 0 if found, -ENODEV if not found 1632 */ 1633int sandbox_pci_get_emul(const struct udevice *bus, pci_dev_t find_devfn, 1634 struct udevice **containerp, struct udevice **emulp); 1635 1636/** 1637 * sandbox_pci_get_client() - Find the client for an emulation device 1638 * 1639 * @emul: Emulation device to check 1640 * @devp: Returns the client device emulated by this device 1641 * Return: 0 if OK, -ENOENT if the device has no client yet 1642 */ 1643int sandbox_pci_get_client(struct udevice *emul, struct udevice **devp); 1644 1645/** 1646 * board_pci_fixup_dev() - Board callback for PCI device fixups 1647 * 1648 * @bus: PCI bus 1649 * @dev: PCI device 1650 */ 1651extern void board_pci_fixup_dev(struct udevice *bus, struct udevice *dev); 1652 1653/** 1654 * PCI_DEVICE - macro used to describe a specific pci device 1655 * @vend: the 16 bit PCI Vendor ID 1656 * @dev: the 16 bit PCI Device ID 1657 * 1658 * This macro is used to create a struct pci_device_id that matches a 1659 * specific device. The subvendor and subdevice fields will be set to 1660 * PCI_ANY_ID. 1661 */ 1662#define PCI_DEVICE(vend, dev) \ 1663 .vendor = (vend), .device = (dev), \ 1664 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID 1665 1666/** 1667 * PCI_DEVICE_SUB - macro used to describe a specific pci device with subsystem 1668 * @vend: the 16 bit PCI Vendor ID 1669 * @dev: the 16 bit PCI Device ID 1670 * @subvend: the 16 bit PCI Subvendor ID 1671 * @subdev: the 16 bit PCI Subdevice ID 1672 * 1673 * This macro is used to create a struct pci_device_id that matches a 1674 * specific device with subsystem information. 1675 */ 1676#define PCI_DEVICE_SUB(vend, dev, subvend, subdev) \ 1677 .vendor = (vend), .device = (dev), \ 1678 .subvendor = (subvend), .subdevice = (subdev) 1679 1680/** 1681 * PCI_DEVICE_CLASS - macro used to describe a specific pci device class 1682 * @dev_class: the class, subclass, prog-if triple for this device 1683 * @dev_class_mask: the class mask for this device 1684 * 1685 * This macro is used to create a struct pci_device_id that matches a 1686 * specific PCI class. The vendor, device, subvendor, and subdevice 1687 * fields will be set to PCI_ANY_ID. 1688 */ 1689#define PCI_DEVICE_CLASS(dev_class, dev_class_mask) \ 1690 .class = (dev_class), .class_mask = (dev_class_mask), \ 1691 .vendor = PCI_ANY_ID, .device = PCI_ANY_ID, \ 1692 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID 1693 1694/** 1695 * PCI_VDEVICE - macro used to describe a specific pci device in short form 1696 * @vend: the vendor name 1697 * @dev: the 16 bit PCI Device ID 1698 * 1699 * This macro is used to create a struct pci_device_id that matches a 1700 * specific PCI device. The subvendor, and subdevice fields will be set 1701 * to PCI_ANY_ID. The macro allows the next field to follow as the device 1702 * private data. 1703 */ 1704 1705#define PCI_VDEVICE(vend, dev) \ 1706 .vendor = PCI_VENDOR_ID_##vend, .device = (dev), \ 1707 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 0, 0 1708 1709/** 1710 * struct pci_driver_entry - Matches a driver to its pci_device_id list 1711 * @driver: Driver to use 1712 * @match: List of match records for this driver, terminated by {} 1713 */ 1714struct pci_driver_entry { 1715 struct driver *driver; 1716 const struct pci_device_id *match; 1717}; 1718 1719#define U_BOOT_PCI_DEVICE(__name, __match) \ 1720 ll_entry_declare(struct pci_driver_entry, __name, pci_driver_entry) = {\ 1721 .driver = llsym(struct driver, __name, driver), \ 1722 .match = __match, \ 1723 } 1724 1725#endif /* __ASSEMBLY__ */ 1726#endif /* _PCI_H */ 1727