Searched refs:frequency (Results 1 - 25 of 28) sorted by relevance

12

/u-boot/drivers/spi/
H A Dtegra_spi.h8 int frequency; /* Default clock frequency, -1 for none */ member in struct:tegra_spi_plat
H A Dexynos_spi.c29 s32 frequency; /* Default clock frequency, -1 for none */ member in struct:exynos_spi_plat
36 unsigned int freq; /* Default frequency */
271 plat->frequency = fdtdec_get_int(blob, node, "spi-max-frequency",
275 debug("%s: regs=%p, periph_id=%d, max-frequency=%d, deactivate_delay=%d\n",
276 __func__, plat->regs, plat->periph_id, plat->frequency,
296 priv->freq = plat->frequency;
376 if (speed > plat->frequency)
377 speed = plat->frequency;
[all...]
H A Dzynq_spi.c61 u32 frequency; /* input frequency */ member in struct:zynq_spi_plat
74 u32 freq; /* required frequency */
155 plat->frequency = clock;
156 plat->speed_hz = plat->frequency / 2;
158 debug("%s: max-frequency=%d\n", __func__, plat->speed_hz);
306 if (speed > plat->frequency)
307 speed = plat->frequency;
309 /* Set the clock frequency */
316 ((plat->frequency /
[all...]
H A Dtegra114_spi.c114 plat->frequency = dev_read_u32_default(bus, "spi-max-frequency",
118 debug("%s: base=%#08lx, periph_id=%d, max-frequency=%d, deactivate_delay=%d\n",
119 __func__, plat->base, plat->periph_id, plat->frequency,
136 priv->freq = plat->frequency;
140 * Change SPI clock to correct frequency, PLLP_OUT0 source, falling
358 if (speed > plat->frequency)
359 speed = plat->frequency;
H A Dtegra20_slink.c113 plat->frequency = fdtdec_get_int(blob, node, "spi-max-frequency",
117 debug("%s: base=%#08lx, periph_id=%d, max-frequency=%d, deactivate_delay=%d\n",
118 __func__, plat->base, plat->periph_id, plat->frequency,
132 priv->freq = plat->frequency;
135 /* Change SPI clock to correct frequency, PLLP_OUT0 source */
149 /* Change SPI clock to correct frequency, PLLP_OUT0 source */
324 if (speed > plat->frequency)
325 speed = plat->frequency;
H A Dtegra20_sflash.c107 plat->frequency = fdtdec_get_int(blob, node, "spi-max-frequency",
111 debug("%s: base=%#08lx, periph_id=%d, max-frequency=%d, deactivate_delay=%d\n",
112 __func__, plat->base, plat->periph_id, plat->frequency,
126 priv->freq = plat->frequency;
129 /* Change SPI clock to correct frequency, PLLP_OUT0 source */
143 /* Change SPI clock to correct frequency, PLLP_OUT0 source */
321 if (speed > plat->frequency)
322 speed = plat->frequency;
H A Dtegra210_qspi.c115 plat->frequency = dev_read_u32_default(bus, "spi-max-frequency",
120 debug("%s: base=%#08lx, periph_id=%d, max-frequency=%d, deactivate_delay=%d\n",
121 __func__, plat->base, plat->periph_id, plat->frequency,
136 priv->freq = plat->frequency;
141 /* Change SPI clock to correct frequency, PLLP_OUT0 source */
387 if (speed > plat->frequency)
388 speed = plat->frequency;
H A Drk_spi.c47 s32 frequency; /* Default clock frequency, -1 for none */ member in struct:rockchip_spi_plat
185 plat->frequency = 20000000;
210 plat->frequency = dev_read_u32_default(bus, "spi-max-frequency",
217 debug("%s: base=%x, max-frequency=%d, deactivate_delay=%d\n",
218 __func__, (uint)plat->base, plat->frequency,
240 * the maximum frequency and can be generated from the assumed
245 * this frequency), we try to have an input frequency o
[all...]
H A Duniphier_spi.c75 u32 frequency; /* input frequency */ member in struct:uniphier_spi_plat
288 if (speed > plat->frequency)
289 speed = plat->frequency;
375 plat->frequency =
376 fdtdec_get_int(blob, node, "spi-max-frequency", 12500000);
381 plat->speed_hz = plat->frequency / 2;
H A Ddesignware_spi.c120 s32 frequency; /* Default clock frequency, -1 for none */ member in struct:dw_spi_plat
133 unsigned int freq; /* Default frequency */
257 plat->frequency = dev_read_u32_default(bus, "spi-max-frequency",
263 dev_info(bus, "max-frequency=%d\n", plat->frequency);
367 priv->freq = plat->frequency;
697 if (speed > plat->frequency)
698 speed = plat->frequency;
[all...]
H A Dzynqmp_gqspi.c171 u32 frequency; member in struct:zynqmp_qspi_plat
313 clk_rate = plat->frequency;
367 log_debug("%s, Speed: %d, Max: %d\n", __func__, speed, plat->frequency);
369 if (speed > plat->frequency)
370 speed = plat->frequency;
373 /* Set the clock frequency */
376 ((plat->frequency /
383 plat->speed_hz = plat->frequency / (2 << baud_rate_val);
425 plat->frequency = clock;
426 plat->speed_hz = plat->frequency /
[all...]
H A Dmxs_spi.c48 s32 frequency; /* Default clock frequency, -1 for none */ member in struct:mxs_spi_plat
334 priv->max_freq = plat->frequency;
451 plat->frequency =
452 dev_read_u32_default(bus, "spi-max-frequency", 40000000);
469 debug("%s: base=0x%x, max-frequency=%d num-cs=%d dma_id=%d clk_id=%d\n",
470 __func__, (uint)plat->base, plat->frequency, plat->num_cs,
/u-boot/arch/arm/include/asm/arch-tegra124/
H A Dclock.h32 * @frequency: the requested PLLD frequency
37 u32 clock_set_display_rate(u32 frequency);
/u-boot/arch/arm/include/asm/arch-am33xx/
H A Dsys_proto.h42 int am335x_get_mpu_vdd(int sil_rev, int frequency);
43 int am335x_get_tps65910_mpu_vdd(int sil_rev, int frequency);
/u-boot/arch/arm/mach-omap2/am33xx/
H A Dsys_info.c178 int am335x_get_mpu_vdd(int sil_rev, int frequency) argument
180 int sel_mask = am335x_get_tps65910_mpu_vdd(sil_rev, frequency);
194 int am335x_get_tps65910_mpu_vdd(int sil_rev, int frequency) argument
198 switch (frequency) {
/u-boot/arch/x86/cpu/slimbootloader/
H A Dslimbootloader.c18 * the only tsc frequency info is used for the timer driver for now.
23 * bypass TSC calibration and use the provided TSC frequency.
42 /* frequency is in KHz, so to Hz */
43 gd->arch.clock_rate = data->frequency * 1000;
/u-boot/drivers/pwm/
H A Dpwm-cadence-ttc.c60 unsigned long frequency; member in struct:cadence_ttc_pwm_priv
102 period_clocks = div64_u64(((int64_t)period_ns * priv->frequency),
125 duty_clocks = div64_u64(((int64_t)duty_ns * priv->frequency),
196 priv->frequency = clk_get_rate(&clk);
197 if (IS_ERR_VALUE(priv->frequency)) {
199 return priv->frequency;
201 dev_dbg(dev, "Clk frequency: %ld\n", priv->frequency);
/u-boot/arch/sandbox/include/asm/
H A Dsdl.h134 static inline int sandbox_sdl_sound_start(uint frequency) argument
/u-boot/drivers/mmc/
H A Dnexell_dw_mmc.c42 int frequency; member in struct:nexell_dwmmc_priv
168 priv->frequency = dev_read_u32_default(dev, "frequency", 50000000);
169 priv->max_freq = dev_read_u32_default(dev, "max-frequency", 50000000);
202 if (nx_dw_mmc_set_clk(host, priv->frequency * 4) !=
203 priv->frequency * 4) {
205 __func__, priv->frequency * 4);
209 __func__, priv->frequency * 4);
/u-boot/arch/arm/cpu/armv7/s5p-common/
H A Dpwm.c105 unsigned long frequency; local
121 frequency = NS_IN_SEC / period_ns;
124 tin_rate = pwm_calc_tin(pwm_id, frequency);
/u-boot/arch/x86/include/asm/arch-slimbootloader/
H A Dslimbootloader.h79 * @clk : uart frequency in Hz
95 * stages from the reset vector. In addition, this has TSC frequency in KHz to
102 * @frequency: tsc frequency in KHz
110 u32 frequency; member in struct:sbl_performance_info
/u-boot/drivers/ddr/marvell/a38x/
H A Dddr3_training_ip_prv_if.h57 enum mv_ddr_freq frequency);
67 u32 dev_num, enum mv_ddr_freq frequency,
H A Dddr3_training_ip_flow.h68 enum mv_ddr_freq frequency,
71 enum mv_ddr_freq frequency,
H A Dddr3_training.c110 u32 if_id, enum mv_ddr_freq frequency);
112 u32 if_id, enum mv_ddr_freq frequency);
115 u32 if_id, enum mv_ddr_freq frequency);
1156 u32 if_id, enum mv_ddr_freq frequency)
1173 tip_get_freq_config_info_func((u8)dev_num, frequency,
1203 mdelay(100 / (mv_ddr_freq_get(frequency)) / mv_ddr_freq_get(MV_DDR_FREQ_LOW_FREQ));
1229 u32 if_id, enum mv_ddr_freq frequency)
1248 u32 freq = mv_ddr_freq_get(frequency);
1252 access_type, if_id, frequency));
1254 if (frequency
1155 adll_calibration(u32 dev_num, enum hws_access_type access_type, u32 if_id, enum mv_ddr_freq frequency) argument
1228 ddr3_tip_freq_set(u32 dev_num, enum hws_access_type access_type, u32 if_id, enum mv_ddr_freq frequency) argument
1679 ddr3_tip_set_timing(u32 dev_num, enum hws_access_type access_type, u32 if_id, enum mv_ddr_freq frequency) argument
1829 ddr4_tip_set_timing(u32 dev_num, enum hws_access_type access_type, u32 if_id, enum mv_ddr_freq frequency) argument
[all...]
H A Dmv_ddr_plat.c460 static u8 ddr3_tip_clock_mode(u32 frequency) argument
462 if ((frequency == MV_DDR_FREQ_LOW_FREQ) || (mv_ddr_freq_get(frequency) <= 400))
852 enum mv_ddr_freq frequency)
858 u32 ddr_freq = mv_ddr_freq_get(frequency);
891 switch (frequency) {
965 dunit_write(0x18488, (1 << 16), ((ddr3_tip_clock_mode(frequency) & 0x1) << 16));
966 dunit_write(0x1524, (1 << 15), ((ddr3_tip_clock_mode(frequency) - 1) << 15));
851 ddr3_tip_a38x_set_divider(u8 dev_num, u32 if_id, enum mv_ddr_freq frequency) argument

Completed in 136 milliseconds

12