1// SPDX-License-Identifier: GPL-2.0 2/* 3 * NVIDIA Tegra SPI controller (T114 and later) 4 * 5 * Copyright (c) 2010-2013 NVIDIA Corporation 6 */ 7 8#include <dm.h> 9#include <log.h> 10#include <time.h> 11#include <asm/io.h> 12#include <asm/arch/clock.h> 13#include <asm/arch-tegra/clk_rst.h> 14#include <spi.h> 15#include <linux/bitops.h> 16#include <linux/delay.h> 17#include "tegra_spi.h" 18 19/* COMMAND1 */ 20#define SPI_CMD1_GO BIT(31) 21#define SPI_CMD1_M_S BIT(30) 22#define SPI_CMD1_MODE_MASK GENMASK(1, 0) 23#define SPI_CMD1_MODE_SHIFT 28 24#define SPI_CMD1_CS_SEL_MASK GENMASK(1, 0) 25#define SPI_CMD1_CS_SEL_SHIFT 26 26#define SPI_CMD1_CS_POL_INACTIVE3 BIT(25) 27#define SPI_CMD1_CS_POL_INACTIVE2 BIT(24) 28#define SPI_CMD1_CS_POL_INACTIVE1 BIT(23) 29#define SPI_CMD1_CS_POL_INACTIVE0 BIT(22) 30#define SPI_CMD1_CS_SW_HW BIT(21) 31#define SPI_CMD1_CS_SW_VAL BIT(20) 32#define SPI_CMD1_IDLE_SDA_MASK GENMASK(1, 0) 33#define SPI_CMD1_IDLE_SDA_SHIFT 18 34#define SPI_CMD1_BIDIR BIT(17) 35#define SPI_CMD1_LSBI_FE BIT(16) 36#define SPI_CMD1_LSBY_FE BIT(15) 37#define SPI_CMD1_BOTH_EN_BIT BIT(14) 38#define SPI_CMD1_BOTH_EN_BYTE BIT(13) 39#define SPI_CMD1_RX_EN BIT(12) 40#define SPI_CMD1_TX_EN BIT(11) 41#define SPI_CMD1_PACKED BIT(5) 42#define SPI_CMD1_BIT_LEN_MASK GENMASK(4, 0) 43#define SPI_CMD1_BIT_LEN_SHIFT 0 44 45/* COMMAND2 */ 46#define SPI_CMD2_TX_CLK_TAP_DELAY BIT(6) 47#define SPI_CMD2_TX_CLK_TAP_DELAY_MASK GENMASK(11, 6) 48#define SPI_CMD2_RX_CLK_TAP_DELAY BIT(0) 49#define SPI_CMD2_RX_CLK_TAP_DELAY_MASK GENMASK(5, 0) 50 51/* TRANSFER STATUS */ 52#define SPI_XFER_STS_RDY BIT(30) 53 54/* FIFO STATUS */ 55#define SPI_FIFO_STS_CS_INACTIVE BIT(31) 56#define SPI_FIFO_STS_FRAME_END BIT(30) 57#define SPI_FIFO_STS_RX_FIFO_FLUSH BIT(15) 58#define SPI_FIFO_STS_TX_FIFO_FLUSH BIT(14) 59#define SPI_FIFO_STS_ERR BIT(8) 60#define SPI_FIFO_STS_TX_FIFO_OVF BIT(7) 61#define SPI_FIFO_STS_TX_FIFO_UNR BIT(6) 62#define SPI_FIFO_STS_RX_FIFO_OVF BIT(5) 63#define SPI_FIFO_STS_RX_FIFO_UNR BIT(4) 64#define SPI_FIFO_STS_TX_FIFO_FULL BIT(3) 65#define SPI_FIFO_STS_TX_FIFO_EMPTY BIT(2) 66#define SPI_FIFO_STS_RX_FIFO_FULL BIT(1) 67#define SPI_FIFO_STS_RX_FIFO_EMPTY BIT(0) 68 69#define SPI_TIMEOUT 1000 70#define TEGRA_SPI_MAX_FREQ 52000000 71 72struct spi_regs { 73 u32 command1; /* 000:SPI_COMMAND1 register */ 74 u32 command2; /* 004:SPI_COMMAND2 register */ 75 u32 timing1; /* 008:SPI_CS_TIM1 register */ 76 u32 timing2; /* 00c:SPI_CS_TIM2 register */ 77 u32 xfer_status;/* 010:SPI_TRANS_STATUS register */ 78 u32 fifo_status;/* 014:SPI_FIFO_STATUS register */ 79 u32 tx_data; /* 018:SPI_TX_DATA register */ 80 u32 rx_data; /* 01c:SPI_RX_DATA register */ 81 u32 dma_ctl; /* 020:SPI_DMA_CTL register */ 82 u32 dma_blk; /* 024:SPI_DMA_BLK register */ 83 u32 rsvd[56]; /* 028-107 reserved */ 84 u32 tx_fifo; /* 108:SPI_FIFO1 register */ 85 u32 rsvd2[31]; /* 10c-187 reserved */ 86 u32 rx_fifo; /* 188:SPI_FIFO2 register */ 87 u32 spare_ctl; /* 18c:SPI_SPARE_CTRL register */ 88}; 89 90struct tegra114_spi_priv { 91 struct spi_regs *regs; 92 unsigned int freq; 93 unsigned int mode; 94 int periph_id; 95 int valid; 96 int last_transaction_us; 97}; 98 99static int tegra114_spi_of_to_plat(struct udevice *bus) 100{ 101 struct tegra_spi_plat *plat = dev_get_plat(bus); 102 103 plat->base = dev_read_addr(bus); 104 plat->periph_id = clock_decode_periph_id(bus); 105 106 if (plat->periph_id == PERIPH_ID_NONE) { 107 debug("%s: could not decode periph id %d\n", __func__, 108 plat->periph_id); 109 return -FDT_ERR_NOTFOUND; 110 } 111 112 /* Use 500KHz as a suitable default */ 113 plat->frequency = dev_read_u32_default(bus, "spi-max-frequency", 114 500000); 115 plat->deactivate_delay_us = dev_read_u32_default(bus, 116 "spi-deactivate-delay", 0); 117 debug("%s: base=%#08lx, periph_id=%d, max-frequency=%d, deactivate_delay=%d\n", 118 __func__, plat->base, plat->periph_id, plat->frequency, 119 plat->deactivate_delay_us); 120 121 return 0; 122} 123 124static int tegra114_spi_probe(struct udevice *bus) 125{ 126 struct tegra_spi_plat *plat = dev_get_plat(bus); 127 struct tegra114_spi_priv *priv = dev_get_priv(bus); 128 struct spi_regs *regs; 129 ulong rate; 130 131 priv->regs = (struct spi_regs *)plat->base; 132 regs = priv->regs; 133 134 priv->last_transaction_us = timer_get_us(); 135 priv->freq = plat->frequency; 136 priv->periph_id = plat->periph_id; 137 138 /* 139 * Change SPI clock to correct frequency, PLLP_OUT0 source, falling 140 * back to the oscillator if that is too fast. 141 */ 142 rate = clock_start_periph_pll(priv->periph_id, CLOCK_ID_PERIPH, 143 priv->freq); 144 if (rate > priv->freq + 100000) { 145 rate = clock_start_periph_pll(priv->periph_id, CLOCK_ID_OSC, 146 priv->freq); 147 if (rate != priv->freq) { 148 printf("Warning: SPI '%s' requested clock %u, actual clock %lu\n", 149 bus->name, priv->freq, rate); 150 } 151 } 152 udelay(plat->deactivate_delay_us); 153 154 /* Clear stale status here */ 155 setbits_le32(®s->fifo_status, 156 SPI_FIFO_STS_ERR | 157 SPI_FIFO_STS_TX_FIFO_OVF | 158 SPI_FIFO_STS_TX_FIFO_UNR | 159 SPI_FIFO_STS_RX_FIFO_OVF | 160 SPI_FIFO_STS_RX_FIFO_UNR | 161 SPI_FIFO_STS_TX_FIFO_FULL | 162 SPI_FIFO_STS_TX_FIFO_EMPTY | 163 SPI_FIFO_STS_RX_FIFO_FULL | 164 SPI_FIFO_STS_RX_FIFO_EMPTY); 165 debug("%s: FIFO STATUS = %08x\n", __func__, readl(®s->fifo_status)); 166 167 setbits_le32(&priv->regs->command1, SPI_CMD1_M_S | SPI_CMD1_CS_SW_HW | 168 (priv->mode << SPI_CMD1_MODE_SHIFT) | SPI_CMD1_CS_SW_VAL); 169 debug("%s: COMMAND1 = %08x\n", __func__, readl(®s->command1)); 170 171 return 0; 172} 173 174/** 175 * Activate the CS by driving it LOW 176 * 177 * @param slave Pointer to spi_slave to which controller has to 178 * communicate with 179 */ 180static void spi_cs_activate(struct udevice *dev) 181{ 182 struct udevice *bus = dev->parent; 183 struct tegra_spi_plat *pdata = dev_get_plat(bus); 184 struct tegra114_spi_priv *priv = dev_get_priv(bus); 185 186 /* If it's too soon to do another transaction, wait */ 187 if (pdata->deactivate_delay_us && 188 priv->last_transaction_us) { 189 ulong delay_us; /* The delay completed so far */ 190 delay_us = timer_get_us() - priv->last_transaction_us; 191 if (delay_us < pdata->deactivate_delay_us) 192 udelay(pdata->deactivate_delay_us - delay_us); 193 } 194 195 clrbits_le32(&priv->regs->command1, SPI_CMD1_CS_SW_VAL); 196} 197 198/** 199 * Deactivate the CS by driving it HIGH 200 * 201 * @param slave Pointer to spi_slave to which controller has to 202 * communicate with 203 */ 204static void spi_cs_deactivate(struct udevice *dev) 205{ 206 struct udevice *bus = dev->parent; 207 struct tegra_spi_plat *pdata = dev_get_plat(bus); 208 struct tegra114_spi_priv *priv = dev_get_priv(bus); 209 210 setbits_le32(&priv->regs->command1, SPI_CMD1_CS_SW_VAL); 211 212 /* Remember time of this transaction so we can honour the bus delay */ 213 if (pdata->deactivate_delay_us) 214 priv->last_transaction_us = timer_get_us(); 215 216 debug("Deactivate CS, bus '%s'\n", bus->name); 217} 218 219static int tegra114_spi_xfer(struct udevice *dev, unsigned int bitlen, 220 const void *data_out, void *data_in, 221 unsigned long flags) 222{ 223 struct udevice *bus = dev->parent; 224 struct tegra114_spi_priv *priv = dev_get_priv(bus); 225 struct spi_regs *regs = priv->regs; 226 u32 reg, tmpdout, tmpdin = 0; 227 const u8 *dout = data_out; 228 u8 *din = data_in; 229 int num_bytes; 230 int ret; 231 232 debug("%s: slave %u:%u dout %p din %p bitlen %u\n", 233 __func__, dev_seq(bus), spi_chip_select(dev), dout, din, bitlen); 234 if (bitlen % 8) 235 return -1; 236 num_bytes = bitlen / 8; 237 238 ret = 0; 239 240 if (flags & SPI_XFER_BEGIN) 241 spi_cs_activate(dev); 242 243 /* clear all error status bits */ 244 reg = readl(®s->fifo_status); 245 writel(reg, ®s->fifo_status); 246 247 clrsetbits_le32(®s->command1, SPI_CMD1_CS_SW_VAL, 248 SPI_CMD1_RX_EN | SPI_CMD1_TX_EN | SPI_CMD1_LSBY_FE | 249 (spi_chip_select(dev) << SPI_CMD1_CS_SEL_SHIFT)); 250 251 /* set xfer size to 1 block (32 bits) */ 252 writel(0, ®s->dma_blk); 253 254 /* handle data in 32-bit chunks */ 255 while (num_bytes > 0) { 256 int bytes; 257 int tm, i; 258 259 tmpdout = 0; 260 bytes = (num_bytes > 4) ? 4 : num_bytes; 261 262 if (dout != NULL) { 263 for (i = 0; i < bytes; ++i) 264 tmpdout = (tmpdout << 8) | dout[i]; 265 dout += bytes; 266 } 267 268 num_bytes -= bytes; 269 270 /* clear ready bit */ 271 setbits_le32(®s->xfer_status, SPI_XFER_STS_RDY); 272 273 clrsetbits_le32(®s->command1, 274 SPI_CMD1_BIT_LEN_MASK << SPI_CMD1_BIT_LEN_SHIFT, 275 (bytes * 8 - 1) << SPI_CMD1_BIT_LEN_SHIFT); 276 writel(tmpdout, ®s->tx_fifo); 277 setbits_le32(®s->command1, SPI_CMD1_GO); 278 279 /* 280 * Wait for SPI transmit FIFO to empty, or to time out. 281 * The RX FIFO status will be read and cleared last 282 */ 283 for (tm = 0; tm < SPI_TIMEOUT; ++tm) { 284 u32 fifo_status, xfer_status; 285 286 xfer_status = readl(®s->xfer_status); 287 if (!(xfer_status & SPI_XFER_STS_RDY)) 288 continue; 289 290 fifo_status = readl(®s->fifo_status); 291 if (fifo_status & SPI_FIFO_STS_ERR) { 292 debug("%s: got a fifo error: ", __func__); 293 if (fifo_status & SPI_FIFO_STS_TX_FIFO_OVF) 294 debug("tx FIFO overflow "); 295 if (fifo_status & SPI_FIFO_STS_TX_FIFO_UNR) 296 debug("tx FIFO underrun "); 297 if (fifo_status & SPI_FIFO_STS_RX_FIFO_OVF) 298 debug("rx FIFO overflow "); 299 if (fifo_status & SPI_FIFO_STS_RX_FIFO_UNR) 300 debug("rx FIFO underrun "); 301 if (fifo_status & SPI_FIFO_STS_TX_FIFO_FULL) 302 debug("tx FIFO full "); 303 if (fifo_status & SPI_FIFO_STS_TX_FIFO_EMPTY) 304 debug("tx FIFO empty "); 305 if (fifo_status & SPI_FIFO_STS_RX_FIFO_FULL) 306 debug("rx FIFO full "); 307 if (fifo_status & SPI_FIFO_STS_RX_FIFO_EMPTY) 308 debug("rx FIFO empty "); 309 debug("\n"); 310 break; 311 } 312 313 if (!(fifo_status & SPI_FIFO_STS_RX_FIFO_EMPTY)) { 314 tmpdin = readl(®s->rx_fifo); 315 316 /* swap bytes read in */ 317 if (din != NULL) { 318 for (i = bytes - 1; i >= 0; --i) { 319 din[i] = tmpdin & 0xff; 320 tmpdin >>= 8; 321 } 322 din += bytes; 323 } 324 325 /* We can exit when we've had both RX and TX */ 326 break; 327 } 328 } 329 330 if (tm >= SPI_TIMEOUT) 331 ret = tm; 332 333 /* clear ACK RDY, etc. bits */ 334 writel(readl(®s->fifo_status), ®s->fifo_status); 335 } 336 337 if (flags & SPI_XFER_END) 338 spi_cs_deactivate(dev); 339 340 debug("%s: transfer ended. Value=%08x, fifo_status = %08x\n", 341 __func__, tmpdin, readl(®s->fifo_status)); 342 343 if (ret) { 344 printf("%s: timeout during SPI transfer, tm %d\n", 345 __func__, ret); 346 return -1; 347 } 348 349 return ret; 350} 351 352static int tegra114_spi_set_speed(struct udevice *bus, uint speed) 353{ 354 struct tegra_spi_plat *plat = dev_get_plat(bus); 355 struct tegra114_spi_priv *priv = dev_get_priv(bus); 356 357 if (speed > plat->frequency) 358 speed = plat->frequency; 359 priv->freq = speed; 360 debug("%s: regs=%p, speed=%d\n", __func__, priv->regs, priv->freq); 361 362 return 0; 363} 364 365static int tegra114_spi_set_mode(struct udevice *bus, uint mode) 366{ 367 struct tegra114_spi_priv *priv = dev_get_priv(bus); 368 369 priv->mode = mode; 370 debug("%s: regs=%p, mode=%d\n", __func__, priv->regs, priv->mode); 371 372 return 0; 373} 374 375static const struct dm_spi_ops tegra114_spi_ops = { 376 .xfer = tegra114_spi_xfer, 377 .set_speed = tegra114_spi_set_speed, 378 .set_mode = tegra114_spi_set_mode, 379 /* 380 * cs_info is not needed, since we require all chip selects to be 381 * in the device tree explicitly 382 */ 383}; 384 385static const struct udevice_id tegra114_spi_ids[] = { 386 { .compatible = "nvidia,tegra114-spi" }, 387 { } 388}; 389 390U_BOOT_DRIVER(tegra114_spi) = { 391 .name = "tegra114_spi", 392 .id = UCLASS_SPI, 393 .of_match = tegra114_spi_ids, 394 .ops = &tegra114_spi_ops, 395 .of_to_plat = tegra114_spi_of_to_plat, 396 .plat_auto = sizeof(struct tegra_spi_plat), 397 .priv_auto = sizeof(struct tegra114_spi_priv), 398 .probe = tegra114_spi_probe, 399}; 400