1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * (C) Copyright 2013 Xilinx, Inc. 4 * (C) Copyright 2015 Jagan Teki <jteki@openedev.com> 5 * 6 * Xilinx Zynq PS SPI controller driver (master mode only) 7 */ 8 9#include <common.h> 10#include <dm.h> 11#include <dm/device_compat.h> 12#include <log.h> 13#include <malloc.h> 14#include <spi.h> 15#include <time.h> 16#include <clk.h> 17#include <asm/global_data.h> 18#include <asm/io.h> 19#include <linux/bitops.h> 20#include <linux/delay.h> 21 22DECLARE_GLOBAL_DATA_PTR; 23 24/* zynq spi register bit masks ZYNQ_SPI_<REG>_<BIT>_MASK */ 25#define ZYNQ_SPI_CR_MSA_MASK BIT(15) /* Manual start enb */ 26#define ZYNQ_SPI_CR_MCS_MASK BIT(14) /* Manual chip select */ 27#define ZYNQ_SPI_CR_CS_MASK GENMASK(13, 10) /* Chip select */ 28#define ZYNQ_SPI_CR_BAUD_MASK GENMASK(5, 3) /* Baud rate div */ 29#define ZYNQ_SPI_CR_CPHA_MASK BIT(2) /* Clock phase */ 30#define ZYNQ_SPI_CR_CPOL_MASK BIT(1) /* Clock polarity */ 31#define ZYNQ_SPI_CR_MSTREN_MASK BIT(0) /* Mode select */ 32#define ZYNQ_SPI_IXR_RXNEMPTY_MASK BIT(4) /* RX_FIFO_not_empty */ 33#define ZYNQ_SPI_IXR_TXOW_MASK BIT(2) /* TX_FIFO_not_full */ 34#define ZYNQ_SPI_IXR_ALL_MASK GENMASK(6, 0) /* All IXR bits */ 35#define ZYNQ_SPI_ENR_SPI_EN_MASK BIT(0) /* SPI Enable */ 36 37#define ZYNQ_SPI_CR_BAUD_MAX 8 /* Baud rate divisor max val */ 38#define ZYNQ_SPI_CR_BAUD_SHIFT 3 /* Baud rate divisor shift */ 39#define ZYNQ_SPI_CR_SS_SHIFT 10 /* Slave select shift */ 40 41#define ZYNQ_SPI_FIFO_DEPTH 128 42#define ZYNQ_SPI_WAIT (CONFIG_SYS_HZ / 100) /* 10 ms */ 43 44/* zynq spi register set */ 45struct zynq_spi_regs { 46 u32 cr; /* 0x00 */ 47 u32 isr; /* 0x04 */ 48 u32 ier; /* 0x08 */ 49 u32 idr; /* 0x0C */ 50 u32 imr; /* 0x10 */ 51 u32 enr; /* 0x14 */ 52 u32 dr; /* 0x18 */ 53 u32 txdr; /* 0x1C */ 54 u32 rxdr; /* 0x20 */ 55}; 56 57 58/* zynq spi platform data */ 59struct zynq_spi_plat { 60 struct zynq_spi_regs *regs; 61 u32 frequency; /* input frequency */ 62 u32 speed_hz; 63 uint deactivate_delay_us; /* Delay to wait after deactivate */ 64 uint activate_delay_us; /* Delay to wait after activate */ 65}; 66 67/* zynq spi priv */ 68struct zynq_spi_priv { 69 struct zynq_spi_regs *regs; 70 u8 cs; 71 u8 mode; 72 ulong last_transaction_us; /* Time of last transaction end */ 73 u8 fifo_depth; 74 u32 freq; /* required frequency */ 75}; 76 77static int zynq_spi_of_to_plat(struct udevice *bus) 78{ 79 struct zynq_spi_plat *plat = dev_get_plat(bus); 80 const void *blob = gd->fdt_blob; 81 int node = dev_of_offset(bus); 82 83 plat->regs = dev_read_addr_ptr(bus); 84 85 plat->deactivate_delay_us = fdtdec_get_int(blob, node, 86 "spi-deactivate-delay", 0); 87 plat->activate_delay_us = fdtdec_get_int(blob, node, 88 "spi-activate-delay", 0); 89 90 return 0; 91} 92 93static void zynq_spi_init_hw(struct zynq_spi_priv *priv) 94{ 95 struct zynq_spi_regs *regs = priv->regs; 96 u32 confr; 97 98 /* Disable SPI */ 99 confr = ZYNQ_SPI_ENR_SPI_EN_MASK; 100 writel(~confr, ®s->enr); 101 102 /* Disable Interrupts */ 103 writel(ZYNQ_SPI_IXR_ALL_MASK, ®s->idr); 104 105 /* Clear RX FIFO */ 106 while (readl(®s->isr) & 107 ZYNQ_SPI_IXR_RXNEMPTY_MASK) 108 readl(®s->rxdr); 109 110 /* Clear Interrupts */ 111 writel(ZYNQ_SPI_IXR_ALL_MASK, ®s->isr); 112 113 /* Manual slave select and Auto start */ 114 confr = ZYNQ_SPI_CR_MCS_MASK | ZYNQ_SPI_CR_CS_MASK | 115 ZYNQ_SPI_CR_MSTREN_MASK; 116 confr &= ~ZYNQ_SPI_CR_MSA_MASK; 117 writel(confr, ®s->cr); 118 119 /* Enable SPI */ 120 writel(ZYNQ_SPI_ENR_SPI_EN_MASK, ®s->enr); 121} 122 123static int zynq_spi_probe(struct udevice *bus) 124{ 125 struct zynq_spi_plat *plat = dev_get_plat(bus); 126 struct zynq_spi_priv *priv = dev_get_priv(bus); 127 struct clk clk; 128 unsigned long clock; 129 int ret; 130 131 priv->regs = plat->regs; 132 priv->fifo_depth = ZYNQ_SPI_FIFO_DEPTH; 133 134 ret = clk_get_by_name(bus, "ref_clk", &clk); 135 if (ret < 0) { 136 dev_err(bus, "failed to get clock\n"); 137 return ret; 138 } 139 140 clock = clk_get_rate(&clk); 141 if (IS_ERR_VALUE(clock)) { 142 dev_err(bus, "failed to get rate\n"); 143 return clock; 144 } 145 146 ret = clk_enable(&clk); 147 if (ret) { 148 dev_err(bus, "failed to enable clock\n"); 149 return ret; 150 } 151 152 /* init the zynq spi hw */ 153 zynq_spi_init_hw(priv); 154 155 plat->frequency = clock; 156 plat->speed_hz = plat->frequency / 2; 157 158 debug("%s: max-frequency=%d\n", __func__, plat->speed_hz); 159 160 return 0; 161} 162 163static void spi_cs_activate(struct udevice *dev) 164{ 165 struct udevice *bus = dev->parent; 166 struct zynq_spi_plat *plat = dev_get_plat(bus); 167 struct zynq_spi_priv *priv = dev_get_priv(bus); 168 struct zynq_spi_regs *regs = priv->regs; 169 u32 cr; 170 171 /* If it's too soon to do another transaction, wait */ 172 if (plat->deactivate_delay_us && priv->last_transaction_us) { 173 ulong delay_us; /* The delay completed so far */ 174 delay_us = timer_get_us() - priv->last_transaction_us; 175 if (delay_us < plat->deactivate_delay_us) 176 udelay(plat->deactivate_delay_us - delay_us); 177 } 178 179 clrbits_le32(®s->cr, ZYNQ_SPI_CR_CS_MASK); 180 cr = readl(®s->cr); 181 /* 182 * CS cal logic: CS[13:10] 183 * xxx0 - cs0 184 * xx01 - cs1 185 * x011 - cs2 186 */ 187 cr |= (~(1 << priv->cs) << ZYNQ_SPI_CR_SS_SHIFT) & ZYNQ_SPI_CR_CS_MASK; 188 writel(cr, ®s->cr); 189 190 if (plat->activate_delay_us) 191 udelay(plat->activate_delay_us); 192} 193 194static void spi_cs_deactivate(struct udevice *dev) 195{ 196 struct udevice *bus = dev->parent; 197 struct zynq_spi_plat *plat = dev_get_plat(bus); 198 struct zynq_spi_priv *priv = dev_get_priv(bus); 199 struct zynq_spi_regs *regs = priv->regs; 200 201 setbits_le32(®s->cr, ZYNQ_SPI_CR_CS_MASK); 202 203 /* Remember time of this transaction so we can honour the bus delay */ 204 if (plat->deactivate_delay_us) 205 priv->last_transaction_us = timer_get_us(); 206} 207 208static int zynq_spi_claim_bus(struct udevice *dev) 209{ 210 struct udevice *bus = dev->parent; 211 struct zynq_spi_priv *priv = dev_get_priv(bus); 212 struct zynq_spi_regs *regs = priv->regs; 213 214 writel(ZYNQ_SPI_ENR_SPI_EN_MASK, ®s->enr); 215 216 return 0; 217} 218 219static int zynq_spi_release_bus(struct udevice *dev) 220{ 221 struct udevice *bus = dev->parent; 222 struct zynq_spi_priv *priv = dev_get_priv(bus); 223 struct zynq_spi_regs *regs = priv->regs; 224 u32 confr; 225 226 confr = ZYNQ_SPI_ENR_SPI_EN_MASK; 227 writel(~confr, ®s->enr); 228 229 return 0; 230} 231 232static int zynq_spi_xfer(struct udevice *dev, unsigned int bitlen, 233 const void *dout, void *din, unsigned long flags) 234{ 235 struct udevice *bus = dev->parent; 236 struct zynq_spi_priv *priv = dev_get_priv(bus); 237 struct zynq_spi_regs *regs = priv->regs; 238 struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev); 239 u32 len = bitlen / 8; 240 u32 tx_len = len, rx_len = len, tx_tvl; 241 const u8 *tx_buf = dout; 242 u8 *rx_buf = din, buf; 243 u32 ts, status; 244 245 debug("spi_xfer: bus:%i cs:%i bitlen:%i len:%i flags:%lx\n", 246 dev_seq(bus), slave_plat->cs, bitlen, len, flags); 247 248 if (bitlen % 8) { 249 debug("spi_xfer: Non byte aligned SPI transfer\n"); 250 return -1; 251 } 252 253 priv->cs = slave_plat->cs; 254 if (flags & SPI_XFER_BEGIN) 255 spi_cs_activate(dev); 256 257 while (rx_len > 0) { 258 /* Write the data into TX FIFO - tx threshold is fifo_depth */ 259 tx_tvl = 0; 260 while ((tx_tvl < priv->fifo_depth) && tx_len) { 261 if (tx_buf) 262 buf = *tx_buf++; 263 else 264 buf = 0; 265 writel(buf, ®s->txdr); 266 tx_len--; 267 tx_tvl++; 268 } 269 270 /* Check TX FIFO completion */ 271 ts = get_timer(0); 272 status = readl(®s->isr); 273 while (!(status & ZYNQ_SPI_IXR_TXOW_MASK)) { 274 if (get_timer(ts) > ZYNQ_SPI_WAIT) { 275 printf("spi_xfer: Timeout! TX FIFO not full\n"); 276 return -1; 277 } 278 status = readl(®s->isr); 279 } 280 281 /* Read the data from RX FIFO */ 282 status = readl(®s->isr); 283 while ((status & ZYNQ_SPI_IXR_RXNEMPTY_MASK) && rx_len) { 284 buf = readl(®s->rxdr); 285 if (rx_buf) 286 *rx_buf++ = buf; 287 status = readl(®s->isr); 288 rx_len--; 289 } 290 } 291 292 if (flags & SPI_XFER_END) 293 spi_cs_deactivate(dev); 294 295 return 0; 296} 297 298static int zynq_spi_set_speed(struct udevice *bus, uint speed) 299{ 300 struct zynq_spi_plat *plat = dev_get_plat(bus); 301 struct zynq_spi_priv *priv = dev_get_priv(bus); 302 struct zynq_spi_regs *regs = priv->regs; 303 uint32_t confr; 304 u8 baud_rate_val = 0; 305 306 if (speed > plat->frequency) 307 speed = plat->frequency; 308 309 /* Set the clock frequency */ 310 confr = readl(®s->cr); 311 if (speed == 0) { 312 /* Set baudrate x8, if the freq is 0 */ 313 baud_rate_val = 0x2; 314 } else if (plat->speed_hz != speed) { 315 while ((baud_rate_val < ZYNQ_SPI_CR_BAUD_MAX) && 316 ((plat->frequency / 317 (2 << baud_rate_val)) > speed)) 318 baud_rate_val++; 319 plat->speed_hz = speed / (2 << baud_rate_val); 320 } 321 confr &= ~ZYNQ_SPI_CR_BAUD_MASK; 322 confr |= (baud_rate_val << ZYNQ_SPI_CR_BAUD_SHIFT); 323 324 writel(confr, ®s->cr); 325 priv->freq = speed; 326 327 debug("zynq_spi_set_speed: regs=%p, speed=%d\n", 328 priv->regs, priv->freq); 329 330 return 0; 331} 332 333static int zynq_spi_set_mode(struct udevice *bus, uint mode) 334{ 335 struct zynq_spi_priv *priv = dev_get_priv(bus); 336 struct zynq_spi_regs *regs = priv->regs; 337 uint32_t confr; 338 339 /* Set the SPI Clock phase and polarities */ 340 confr = readl(®s->cr); 341 confr &= ~(ZYNQ_SPI_CR_CPHA_MASK | ZYNQ_SPI_CR_CPOL_MASK); 342 343 if (mode & SPI_CPHA) 344 confr |= ZYNQ_SPI_CR_CPHA_MASK; 345 if (mode & SPI_CPOL) 346 confr |= ZYNQ_SPI_CR_CPOL_MASK; 347 348 writel(confr, ®s->cr); 349 priv->mode = mode; 350 351 debug("zynq_spi_set_mode: regs=%p, mode=%d\n", priv->regs, priv->mode); 352 353 return 0; 354} 355 356static const struct dm_spi_ops zynq_spi_ops = { 357 .claim_bus = zynq_spi_claim_bus, 358 .release_bus = zynq_spi_release_bus, 359 .xfer = zynq_spi_xfer, 360 .set_speed = zynq_spi_set_speed, 361 .set_mode = zynq_spi_set_mode, 362}; 363 364static const struct udevice_id zynq_spi_ids[] = { 365 { .compatible = "xlnx,zynq-spi-r1p6" }, 366 { .compatible = "cdns,spi-r1p6" }, 367 { } 368}; 369 370U_BOOT_DRIVER(zynq_spi) = { 371 .name = "zynq_spi", 372 .id = UCLASS_SPI, 373 .of_match = zynq_spi_ids, 374 .ops = &zynq_spi_ops, 375 .of_to_plat = zynq_spi_of_to_plat, 376 .plat_auto = sizeof(struct zynq_spi_plat), 377 .priv_auto = sizeof(struct zynq_spi_priv), 378 .probe = zynq_spi_probe, 379}; 380