Searched refs:divn (Results 1 - 11 of 11) sorted by relevance
/u-boot/arch/arm/mach-uniphier/clk/ |
H A D | pll.h | 15 unsigned int ssc_rate, unsigned int divn);
|
H A D | pll-base-ld20.c | 33 unsigned int ssc_rate, unsigned int divn) 43 divn * 512)); 50 divn * 512)); 32 uniphier_ld20_sscpll_init(unsigned long reg_base, unsigned int freq, unsigned int ssc_rate, unsigned int divn) argument
|
/u-boot/arch/arm/include/asm/arch-tegra/ |
H A D | clock.h | 57 * @param divn feedback divider 64 unsigned long clock_start_pll(enum clock_id id, u32 divm, u32 divn, 84 * @param divn returns feedback divider 91 int clock_ll_read_pll(enum clock_id clkid, u32 *divm, u32 *divn,
|
H A D | warmboot.h | 73 u32 divn:10; member in struct:pllx_base_reg::__anon6
|
/u-boot/arch/arm/mach-tegra/tegra20/ |
H A D | warmboot.c | 150 u32 divm, divn, divp, cpcon, lfcon; local 152 if (clock_ll_read_pll(CLOCK_ID_MEMORY, &divm, &divn, &divp, 156 scratch2.pllm_base_divn = divn;
|
H A D | warmboot_avp.c | 168 pllx_base.divn = scratch3.pllx_base_divn;
|
/u-boot/drivers/clk/stm32/ |
H A D | clk-stm32mp1.c | 924 int divm, divn; local 932 divn = cfgr1 & RCC_PLLNCFGR1_DIVN_MASK; 945 (((divn + 1) << 13) + fracv), 948 fvco = (ulong)(refclk * (divn + 1) / (divm + 1)); 1350 u32 divm, divn, divp, frac; local 1389 divn = (u32)((freq / input_freq) - 1); 1390 if (divn < DIVN_MIN || divn > DIVN_MAX) 1394 ((divn + 1) * FRAC_MAX)); 1400 vco = (post_divm * (divn 1724 int divm, divn, divy; local [all...] |
H A D | clk-stm32h7.c | 326 u16 divn; member in struct:pll_psc 339 .divn = 80, 405 pll1divr |= (sys_pll_psc.divn - 1);
|
/u-boot/arch/arm/mach-tegra/ |
H A D | cpu.c | 214 int pllx_set_rate(struct clk_pll_simple *pll , u32 divn, u32 divm, argument 232 reg |= (divn << pllinfo->n_shift) | (divp << pllinfo->p_shift); 246 if (divn > 600)
|
H A D | clock.c | 99 int clock_ll_read_pll(enum clock_id clkid, u32 *divm, u32 *divn, argument 113 *divn = (data >> pllinfo->n_shift) & pllinfo->n_mask; 123 unsigned long clock_start_pll(enum clock_id clkid, u32 divm, u32 divn, argument 157 data = (divm << pllinfo->m_shift) | (divn << pllinfo->n_shift);
|
/u-boot/arch/arm/mach-tegra/tegra124/ |
H A D | clock.c | 1104 u32 divm, divn, divp, cpcon; local 1131 divn = vco / cf; 1132 if (divn >= max_n) 1135 diff = vco - divn * cf; 1136 if (divn + 1 < max_n && diff > cf / 2) { 1137 divn++; 1146 best_n = divn;
|
Completed in 73 milliseconds