1294838Szbb// SPDX-License-Identifier: GPL-2.0 2294838Szbb/* 3294838Szbb * Copyright (c) 2010-2019, NVIDIA CORPORATION. All rights reserved. 4294838Szbb */ 5294838Szbb 6294838Szbb/* Tegra SoC common clock control functions */ 7294838Szbb 8294838Szbb#include <common.h> 9294838Szbb#include <div64.h> 10294838Szbb#include <dm.h> 11294838Szbb#include <errno.h> 12294838Szbb#include <log.h> 13294838Szbb#include <time.h> 14294838Szbb#include <asm/io.h> 15294838Szbb#include <asm/arch/clock.h> 16294838Szbb#include <asm/arch/tegra.h> 17294838Szbb#include <asm/arch-tegra/ap.h> 18294838Szbb#include <asm/arch-tegra/clk_rst.h> 19294838Szbb#include <asm/arch-tegra/pmc.h> 20294838Szbb#include <asm/arch-tegra/timer.h> 21294838Szbb#include <linux/delay.h> 22294838Szbb 23294838Szbb/* 24294838Szbb * This is our record of the current clock rate of each clock. We don't 25294838Szbb * fill all of these in since we are only really interested in clocks which 26294838Szbb * we use as parents. 27294838Szbb */ 28294838Szbbstatic unsigned pll_rate[CLOCK_ID_COUNT]; 29294838Szbb 30294838Szbb/* 31294838Szbb * The oscillator frequency is fixed to one of seven set values. Based on this 32294838Szbb * the other clocks are set up appropriately. 33294838Szbb */ 34294838Szbbstatic unsigned osc_freq[CLOCK_OSC_FREQ_COUNT] = { 35294838Szbb 13000000, 36294838Szbb 16800000, 37294838Szbb 0, 38294838Szbb 0, 39294838Szbb 19200000, 40294838Szbb 38400000, 41294838Szbb 0, 42294838Szbb 0, 43294838Szbb 12000000, 44294838Szbb 48000000, 45294838Szbb 0, 46294838Szbb 0, 47294838Szbb 26000000, 48294838Szbb}; 49294838Szbb 50294838Szbb/* return 1 if a peripheral ID is in range */ 51294838Szbb#define clock_type_id_isvalid(id) ((id) >= 0 && \ 52294838Szbb (id) < CLOCK_TYPE_COUNT) 53294838Szbb 54294838Szbbchar pllp_valid = 1; /* PLLP is set up correctly */ 55294838Szbb 56294838Szbb/* return 1 if a periphc_internal_id is in range */ 57294838Szbb#define periphc_internal_id_isvalid(id) ((id) >= 0 && \ 58294838Szbb (id) < PERIPHC_COUNT) 59294838Szbb 60294838Szbb/* number of clock outputs of a PLL */ 61294838Szbbstatic const u8 pll_num_clkouts[] = { 62294838Szbb 1, /* PLLC */ 63294838Szbb 1, /* PLLM */ 64294838Szbb 4, /* PLLP */ 65294838Szbb 1, /* PLLA */ 66294838Szbb 0, /* PLLU */ 67294838Szbb 0, /* PLLD */ 68294838Szbb}; 69294838Szbb 70294838Szbbint clock_get_osc_bypass(void) 71294838Szbb{ 72294838Szbb struct clk_rst_ctlr *clkrst = 73294838Szbb (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; 74294838Szbb u32 reg; 75294838Szbb 76294838Szbb reg = readl(&clkrst->crc_osc_ctrl); 77294838Szbb return (reg & OSC_XOBP_MASK) >> OSC_XOBP_SHIFT; 78294838Szbb} 79294838Szbb 80294838Szbb/* Returns a pointer to the registers of the given pll */ 81294838Szbbstatic struct clk_pll *get_pll(enum clock_id clkid) 82294838Szbb{ 83294838Szbb struct clk_rst_ctlr *clkrst = 84294838Szbb (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; 85294838Szbb 86294838Szbb assert(clock_id_is_pll(clkid)); 87294838Szbb if (clkid >= (enum clock_id)TEGRA_CLK_PLLS) { 88294838Szbb debug("%s: Invalid PLL %d\n", __func__, clkid); 89294838Szbb return NULL; 90294838Szbb } 91294838Szbb return &clkrst->crc_pll[clkid]; 92294838Szbb} 93294838Szbb 94294838Szbb__weak struct clk_pll_simple *clock_get_simple_pll(enum clock_id clkid) 95294838Szbb{ 96294838Szbb return NULL; 97294838Szbb} 98294838Szbb 99294838Szbbint clock_ll_read_pll(enum clock_id clkid, u32 *divm, u32 *divn, 100294838Szbb u32 *divp, u32 *cpcon, u32 *lfcon) 101294838Szbb{ 102294838Szbb struct clk_pll *pll = get_pll(clkid); 103294838Szbb struct clk_pll_info *pllinfo = &tegra_pll_info_table[clkid]; 104294838Szbb u32 data; 105294838Szbb 106294838Szbb assert(clkid != CLOCK_ID_USB); 107294838Szbb 108294838Szbb /* Safety check, adds to code size but is small */ 109294838Szbb if (!clock_id_is_pll(clkid) || clkid == CLOCK_ID_USB) 110294838Szbb return -1; 111294838Szbb data = readl(&pll->pll_base); 112294838Szbb *divm = (data >> pllinfo->m_shift) & pllinfo->m_mask; 113294838Szbb *divn = (data >> pllinfo->n_shift) & pllinfo->n_mask; 114294838Szbb *divp = (data >> pllinfo->p_shift) & pllinfo->p_mask; 115294838Szbb data = readl(&pll->pll_misc); 116294838Szbb /* NOTE: On T210, cpcon/lfcon no longer exist, moved to KCP/KVCO */ 117294838Szbb *cpcon = (data >> pllinfo->kcp_shift) & pllinfo->kcp_mask; 118294838Szbb *lfcon = (data >> pllinfo->kvco_shift) & pllinfo->kvco_mask; 119294838Szbb 120294838Szbb return 0; 121294838Szbb} 122294838Szbb 123294838Szbbunsigned long clock_start_pll(enum clock_id clkid, u32 divm, u32 divn, 124294838Szbb u32 divp, u32 cpcon, u32 lfcon) 125294838Szbb{ 126294838Szbb struct clk_pll *pll = NULL; 127294838Szbb struct clk_pll_info *pllinfo = &tegra_pll_info_table[clkid]; 128294838Szbb struct clk_pll_simple *simple_pll = NULL; 129294838Szbb u32 misc_data, data; 130294838Szbb 131294838Szbb if (clkid < (enum clock_id)TEGRA_CLK_PLLS) 132294838Szbb pll = get_pll(clkid); 133294838Szbb else 134294838Szbb simple_pll = clock_get_simple_pll(clkid); 135294838Szbb 136294838Szbb if (!simple_pll && !pll) { 137294838Szbb log_err("Unknown PLL id %d\n", clkid); 138294838Szbb return 0; 139294838Szbb } 140294838Szbb 141294838Szbb /* 142294838Szbb * pllinfo has the m/n/p and kcp/kvco mask and shift 143294838Szbb * values for all of the PLLs used in U-Boot, with any 144294838Szbb * SoC differences accounted for. 145294838Szbb * 146294838Szbb * Preserve EN_LOCKDET, etc. 147294838Szbb */ 148294838Szbb if (pll) 149294838Szbb misc_data = readl(&pll->pll_misc); 150294838Szbb else 151294838Szbb misc_data = readl(&simple_pll->pll_misc); 152 misc_data &= ~(pllinfo->kcp_mask << pllinfo->kcp_shift); 153 misc_data |= cpcon << pllinfo->kcp_shift; 154 misc_data &= ~(pllinfo->kvco_mask << pllinfo->kvco_shift); 155 misc_data |= lfcon << pllinfo->kvco_shift; 156 157 data = (divm << pllinfo->m_shift) | (divn << pllinfo->n_shift); 158 data |= divp << pllinfo->p_shift; 159 data |= (1 << PLL_ENABLE_SHIFT); /* BYPASS s/b 0 already */ 160 161 if (pll) { 162 writel(misc_data, &pll->pll_misc); 163 writel(data, &pll->pll_base); 164 } else { 165 writel(misc_data, &simple_pll->pll_misc); 166 writel(data, &simple_pll->pll_base); 167 } 168 169 /* calculate the stable time */ 170 return timer_get_us() + CLOCK_PLL_STABLE_DELAY_US; 171} 172 173void clock_ll_set_source_divisor(enum periph_id periph_id, unsigned source, 174 unsigned divisor) 175{ 176 u32 *reg = get_periph_source_reg(periph_id); 177 u32 value; 178 179 value = readl(reg); 180 181 value &= ~OUT_CLK_SOURCE_31_30_MASK; 182 value |= source << OUT_CLK_SOURCE_31_30_SHIFT; 183 184 value &= ~OUT_CLK_DIVISOR_MASK; 185 value |= divisor << OUT_CLK_DIVISOR_SHIFT; 186 187 writel(value, reg); 188} 189 190int clock_ll_set_source_bits(enum periph_id periph_id, int mux_bits, 191 unsigned source) 192{ 193 u32 *reg = get_periph_source_reg(periph_id); 194 195 switch (mux_bits) { 196 case MASK_BITS_31_30: 197 clrsetbits_le32(reg, OUT_CLK_SOURCE_31_30_MASK, 198 source << OUT_CLK_SOURCE_31_30_SHIFT); 199 break; 200 201 case MASK_BITS_31_29: 202 clrsetbits_le32(reg, OUT_CLK_SOURCE_31_29_MASK, 203 source << OUT_CLK_SOURCE_31_29_SHIFT); 204 break; 205 206 case MASK_BITS_31_28: 207 clrsetbits_le32(reg, OUT_CLK_SOURCE_31_28_MASK, 208 source << OUT_CLK_SOURCE_31_28_SHIFT); 209 break; 210 211 default: 212 return -1; 213 } 214 215 return 0; 216} 217 218static int clock_ll_get_source_bits(enum periph_id periph_id, int mux_bits) 219{ 220 u32 *reg = get_periph_source_reg(periph_id); 221 u32 val = readl(reg); 222 223 switch (mux_bits) { 224 case MASK_BITS_31_30: 225 val >>= OUT_CLK_SOURCE_31_30_SHIFT; 226 val &= OUT_CLK_SOURCE_31_30_MASK; 227 return val; 228 case MASK_BITS_31_29: 229 val >>= OUT_CLK_SOURCE_31_29_SHIFT; 230 val &= OUT_CLK_SOURCE_31_29_MASK; 231 return val; 232 case MASK_BITS_31_28: 233 val >>= OUT_CLK_SOURCE_31_28_SHIFT; 234 val &= OUT_CLK_SOURCE_31_28_MASK; 235 return val; 236 default: 237 return -1; 238 } 239} 240 241void clock_ll_set_source(enum periph_id periph_id, unsigned source) 242{ 243 clock_ll_set_source_bits(periph_id, MASK_BITS_31_30, source); 244} 245 246/** 247 * Given the parent's rate and the required rate for the children, this works 248 * out the peripheral clock divider to use, in 7.1 binary format. 249 * 250 * @param divider_bits number of divider bits (8 or 16) 251 * @param parent_rate clock rate of parent clock in Hz 252 * @param rate required clock rate for this clock 253 * Return: divider which should be used 254 */ 255static int clk_get_divider(unsigned divider_bits, unsigned long parent_rate, 256 unsigned long rate) 257{ 258 u64 divider = parent_rate * 2; 259 unsigned max_divider = 1 << divider_bits; 260 261 divider += rate - 1; 262 do_div(divider, rate); 263 264 if ((s64)divider - 2 < 0) 265 return 0; 266 267 if ((s64)divider - 2 >= max_divider) 268 return -1; 269 270 return divider - 2; 271} 272 273int clock_set_pllout(enum clock_id clkid, enum pll_out_id pllout, unsigned rate) 274{ 275 struct clk_pll *pll = get_pll(clkid); 276 int data = 0, div = 0, offset = 0; 277 278 if (!clock_id_is_pll(clkid)) 279 return -1; 280 281 if (pllout + 1 > pll_num_clkouts[clkid]) 282 return -1; 283 284 div = clk_get_divider(8, pll_rate[clkid], rate); 285 286 if (div < 0) 287 return -1; 288 289 /* out2 and out4 are in the high part of the register */ 290 if (pllout == PLL_OUT2 || pllout == PLL_OUT4) 291 offset = 16; 292 293 data = (div << PLL_OUT_RATIO_SHIFT) | 294 PLL_OUT_OVRRIDE | PLL_OUT_CLKEN | PLL_OUT_RSTN; 295 clrsetbits_le32(&pll->pll_out[pllout >> 1], 296 PLL_OUT_RATIO_MASK << offset, data << offset); 297 298 return 0; 299} 300 301/** 302 * Given the parent's rate and the divider in 7.1 format, this works out the 303 * resulting peripheral clock rate. 304 * 305 * @param parent_rate clock rate of parent clock in Hz 306 * @param divider which should be used in 7.1 format 307 * Return: effective clock rate of peripheral 308 */ 309static unsigned long get_rate_from_divider(unsigned long parent_rate, 310 int divider) 311{ 312 u64 rate; 313 314 rate = (u64)parent_rate * 2; 315 do_div(rate, divider + 2); 316 return rate; 317} 318 319unsigned long clock_get_periph_rate(enum periph_id periph_id, 320 enum clock_id parent) 321{ 322 u32 *reg = get_periph_source_reg(periph_id); 323 unsigned parent_rate = pll_rate[parent]; 324 int div = (readl(reg) & OUT_CLK_DIVISOR_MASK) >> OUT_CLK_DIVISOR_SHIFT; 325 326 switch (periph_id) { 327 case PERIPH_ID_UART1: 328 case PERIPH_ID_UART2: 329 case PERIPH_ID_UART3: 330 case PERIPH_ID_UART4: 331 case PERIPH_ID_UART5: 332#ifdef CONFIG_TEGRA20 333 /* There's no divider for these clocks in this SoC. */ 334 return parent_rate; 335#else 336 /* 337 * This undoes the +2 in get_rate_from_divider() which I 338 * believe is incorrect. Ideally we would fix 339 * get_rate_from_divider(), but... Removing the +2 from 340 * get_rate_from_divider() would probably require remove the -2 341 * from the tail of clk_get_divider() since I believe that's 342 * only there to invert get_rate_from_divider()'s +2. Observe 343 * how find_best_divider() uses those two functions together. 344 * However, doing so breaks other stuff, such as Seaboard's 345 * display, likely due to clock_set_pllout()'s call to 346 * clk_get_divider(). Attempting to fix that by making 347 * clock_set_pllout() subtract 2 from clk_get_divider()'s 348 * return value doesn't help. In summary this clock driver is 349 * quite broken but I'm afraid I have no idea how to fix it 350 * without completely replacing it. 351 * 352 * Be careful to avoid a divide by zero error. 353 */ 354 if (div >= 1) 355 div -= 2; 356 break; 357#endif 358 default: 359 break; 360 } 361 362 return get_rate_from_divider(parent_rate, div); 363} 364 365/** 366 * Find the best available 7.1 format divisor given a parent clock rate and 367 * required child clock rate. This function assumes that a second-stage 368 * divisor is available which can divide by powers of 2 from 1 to 256. 369 * 370 * @param divider_bits number of divider bits (8 or 16) 371 * @param parent_rate clock rate of parent clock in Hz 372 * @param rate required clock rate for this clock 373 * @param extra_div value for the second-stage divisor (not set if this 374 * function returns -1. 375 * Return: divider which should be used, or -1 if nothing is valid 376 * 377 */ 378static int find_best_divider(unsigned divider_bits, unsigned long parent_rate, 379 unsigned long rate, int *extra_div) 380{ 381 int shift; 382 int best_divider = -1; 383 int best_error = rate; 384 385 /* try dividers from 1 to 256 and find closest match */ 386 for (shift = 0; shift <= 8 && best_error > 0; shift++) { 387 unsigned divided_parent = parent_rate >> shift; 388 int divider = clk_get_divider(divider_bits, divided_parent, 389 rate); 390 unsigned effective_rate = get_rate_from_divider(divided_parent, 391 divider); 392 int error = rate - effective_rate; 393 394 /* Given a valid divider, look for the lowest error */ 395 if (divider != -1 && error < best_error) { 396 best_error = error; 397 *extra_div = 1 << shift; 398 best_divider = divider; 399 } 400 } 401 402 /* return what we found - *extra_div will already be set */ 403 return best_divider; 404} 405 406/** 407 * Adjust peripheral PLL to use the given divider and source. 408 * 409 * @param periph_id peripheral to adjust 410 * @param source Source number (0-3 or 0-7) 411 * @param mux_bits Number of mux bits (2 or 4) 412 * @param divider Required divider in 7.1 or 15.1 format 413 * Return: 0 if ok, -1 on error (requesting a parent clock which is not valid 414 * for this peripheral) 415 */ 416static int adjust_periph_pll(enum periph_id periph_id, int source, 417 int mux_bits, unsigned divider) 418{ 419 u32 *reg = get_periph_source_reg(periph_id); 420 421 clrsetbits_le32(reg, OUT_CLK_DIVISOR_MASK, 422 divider << OUT_CLK_DIVISOR_SHIFT); 423 udelay(1); 424 425 /* work out the source clock and set it */ 426 if (source < 0) 427 return -1; 428 429 clock_ll_set_source_bits(periph_id, mux_bits, source); 430 431 udelay(2); 432 return 0; 433} 434 435enum clock_id clock_get_periph_parent(enum periph_id periph_id) 436{ 437 int err, mux_bits, divider_bits, type; 438 int source; 439 440 err = get_periph_clock_info(periph_id, &mux_bits, ÷r_bits, &type); 441 if (err) 442 return CLOCK_ID_NONE; 443 444 source = clock_ll_get_source_bits(periph_id, mux_bits); 445 446 return get_periph_clock_id(periph_id, source); 447} 448 449unsigned clock_adjust_periph_pll_div(enum periph_id periph_id, 450 enum clock_id parent, unsigned rate, int *extra_div) 451{ 452 unsigned effective_rate; 453 int mux_bits, divider_bits, source; 454 int divider; 455 int xdiv = 0; 456 457 /* work out the source clock and set it */ 458 source = get_periph_clock_source(periph_id, parent, &mux_bits, 459 ÷r_bits); 460 461 divider = find_best_divider(divider_bits, pll_rate[parent], 462 rate, &xdiv); 463 if (extra_div) 464 *extra_div = xdiv; 465 466 assert(divider >= 0); 467 if (adjust_periph_pll(periph_id, source, mux_bits, divider)) 468 return -1U; 469 debug("periph %d, rate=%d, reg=%p = %x\n", periph_id, rate, 470 get_periph_source_reg(periph_id), 471 readl(get_periph_source_reg(periph_id))); 472 473 /* Check what we ended up with. This shouldn't matter though */ 474 effective_rate = clock_get_periph_rate(periph_id, parent); 475 if (extra_div) 476 effective_rate /= *extra_div; 477 if (rate != effective_rate) 478 debug("Requested clock rate %u not honored (got %u)\n", 479 rate, effective_rate); 480 return effective_rate; 481} 482 483unsigned clock_start_periph_pll(enum periph_id periph_id, 484 enum clock_id parent, unsigned rate) 485{ 486 unsigned effective_rate; 487 488 reset_set_enable(periph_id, 1); 489 clock_enable(periph_id); 490 udelay(2); 491 492 effective_rate = clock_adjust_periph_pll_div(periph_id, parent, rate, 493 NULL); 494 495 reset_set_enable(periph_id, 0); 496 return effective_rate; 497} 498 499void clock_enable(enum periph_id clkid) 500{ 501 clock_set_enable(clkid, 1); 502} 503 504void clock_disable(enum periph_id clkid) 505{ 506 clock_set_enable(clkid, 0); 507} 508 509void reset_periph(enum periph_id periph_id, int us_delay) 510{ 511 /* Put peripheral into reset */ 512 reset_set_enable(periph_id, 1); 513 udelay(us_delay); 514 515 /* Remove reset */ 516 reset_set_enable(periph_id, 0); 517 518 udelay(us_delay); 519} 520 521void reset_cmplx_set_enable(int cpu, int which, int reset) 522{ 523 struct clk_rst_ctlr *clkrst = 524 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; 525 u32 mask; 526 527 /* Form the mask, which depends on the cpu chosen (2 or 4) */ 528 assert(cpu >= 0 && cpu < MAX_NUM_CPU); 529 mask = which << cpu; 530 531 /* either enable or disable those reset for that CPU */ 532 if (reset) 533 writel(mask, &clkrst->crc_cpu_cmplx_set); 534 else 535 writel(mask, &clkrst->crc_cpu_cmplx_clr); 536} 537 538unsigned int __weak clk_m_get_rate(unsigned int parent_rate) 539{ 540 return parent_rate; 541} 542 543unsigned clock_get_rate(enum clock_id clkid) 544{ 545 struct clk_pll *pll = NULL; 546 struct clk_pll_simple *simple_pll = NULL; 547 u32 base, divm; 548 u64 parent_rate, rate; 549 struct clk_pll_info *pllinfo = &tegra_pll_info_table[clkid]; 550 551 parent_rate = osc_freq[clock_get_osc_freq()]; 552 if (clkid == CLOCK_ID_OSC) 553 return parent_rate; 554 555 if (clkid == CLOCK_ID_CLK_M) 556 return clk_m_get_rate(parent_rate); 557 558 if (clkid < (enum clock_id)TEGRA_CLK_PLLS) 559 pll = get_pll(clkid); 560 else 561 simple_pll = clock_get_simple_pll(clkid); 562 563 if (!simple_pll && !pll) { 564 log_err("Unknown PLL id %d\n", clkid); 565 return 0; 566 } 567 568 if (pll) 569 base = readl(&pll->pll_base); 570 else 571 base = readl(&simple_pll->pll_base); 572 573 rate = parent_rate * ((base >> pllinfo->n_shift) & pllinfo->n_mask); 574 divm = (base >> pllinfo->m_shift) & pllinfo->m_mask; 575 /* 576 * PLLU uses p_mask/p_shift for VCO on all but T210, 577 * T210 uses normal DIVP. Handled in pllinfo table. 578 */ 579#ifdef CONFIG_TEGRA210 580 /* 581 * PLLP's primary output (pllP_out0) on T210 is the VCO, and divp is 582 * not applied. pllP_out2 does have divp applied. All other pllP_outN 583 * are divided down from pllP_out0. We only support pllP_out0 in 584 * U-Boot at the time of writing this comment. 585 */ 586 if (clkid != CLOCK_ID_PERIPH) 587#endif 588 divm <<= (base >> pllinfo->p_shift) & pllinfo->p_mask; 589 do_div(rate, divm); 590 return rate; 591} 592 593/** 594 * Set the output frequency you want for each PLL clock. 595 * PLL output frequencies are programmed by setting their N, M and P values. 596 * The governing equations are: 597 * VCO = (Fi / m) * n, Fo = VCO / (2^p) 598 * where Fo is the output frequency from the PLL. 599 * Example: Set the output frequency to 216Mhz(Fo) with 12Mhz OSC(Fi) 600 * 216Mhz = ((12Mhz / m) * n) / (2^p) so n=432,m=12,p=1 601 * Please see Tegra TRM section 5.3 to get the detail for PLL Programming 602 * 603 * @param n PLL feedback divider(DIVN) 604 * @param m PLL input divider(DIVN) 605 * @param p post divider(DIVP) 606 * @param cpcon base PLL charge pump(CPCON) 607 * Return: 0 if ok, -1 on error (the requested PLL is incorrect and cannot 608 * be overridden), 1 if PLL is already correct 609 */ 610int clock_set_rate(enum clock_id clkid, u32 n, u32 m, u32 p, u32 cpcon) 611{ 612 u32 base_reg, misc_reg; 613 struct clk_pll *pll = NULL; 614 struct clk_pll_simple *simple_pll = NULL; 615 struct clk_pll_info *pllinfo = &tegra_pll_info_table[clkid]; 616 617 if (clkid < (enum clock_id)TEGRA_CLK_PLLS) 618 pll = get_pll(clkid); 619 else 620 simple_pll = clock_get_simple_pll(clkid); 621 622 if (!simple_pll && !pll) { 623 log_err("Unknown PLL id %d\n", clkid); 624 return 0; 625 } 626 627 if (pll) 628 base_reg = readl(&pll->pll_base); 629 else 630 base_reg = readl(&simple_pll->pll_base); 631 632 /* Set BYPASS, m, n and p to PLL_BASE */ 633 base_reg &= ~(pllinfo->m_mask << pllinfo->m_shift); 634 base_reg |= m << pllinfo->m_shift; 635 636 base_reg &= ~(pllinfo->n_mask << pllinfo->n_shift); 637 base_reg |= n << pllinfo->n_shift; 638 639 base_reg &= ~(pllinfo->p_mask << pllinfo->p_shift); 640 base_reg |= p << pllinfo->p_shift; 641 642 if (clkid == CLOCK_ID_PERIPH) { 643 /* 644 * If the PLL is already set up, check that it is correct 645 * and record this info for clock_verify() to check. 646 */ 647 if (base_reg & PLL_BASE_OVRRIDE_MASK) { 648 base_reg |= PLL_ENABLE_MASK; 649 if (base_reg != readl(&pll->pll_base)) 650 pllp_valid = 0; 651 return pllp_valid ? 1 : -1; 652 } 653 base_reg |= PLL_BASE_OVRRIDE_MASK; 654 } 655 656 base_reg |= PLL_BYPASS_MASK; 657 if (pll) 658 writel(base_reg, &pll->pll_base); 659 else 660 writel(base_reg, &simple_pll->pll_base); 661 662 /* Set cpcon (KCP) to PLL_MISC */ 663 if (pll) 664 misc_reg = readl(&pll->pll_misc); 665 else 666 misc_reg = readl(&simple_pll->pll_misc); 667 668 misc_reg &= ~(pllinfo->kcp_mask << pllinfo->kcp_shift); 669 misc_reg |= cpcon << pllinfo->kcp_shift; 670 if (pll) 671 writel(misc_reg, &pll->pll_misc); 672 else 673 writel(misc_reg, &simple_pll->pll_misc); 674 675 /* Enable PLL */ 676 base_reg |= PLL_ENABLE_MASK; 677 if (pll) 678 writel(base_reg, &pll->pll_base); 679 else 680 writel(base_reg, &simple_pll->pll_base); 681 682 /* Disable BYPASS */ 683 base_reg &= ~PLL_BYPASS_MASK; 684 if (pll) 685 writel(base_reg, &pll->pll_base); 686 else 687 writel(base_reg, &simple_pll->pll_base); 688 689 return 0; 690} 691 692void clock_ll_start_uart(enum periph_id periph_id) 693{ 694 /* Assert UART reset and enable clock */ 695 reset_set_enable(periph_id, 1); 696 clock_enable(periph_id); 697 clock_ll_set_source(periph_id, 0); /* UARTx_CLK_SRC = 00, PLLP_OUT0 */ 698 699 /* wait for 2us */ 700 udelay(2); 701 702 /* De-assert reset to UART */ 703 reset_set_enable(periph_id, 0); 704} 705 706#if CONFIG_IS_ENABLED(OF_CONTROL) 707int clock_decode_periph_id(struct udevice *dev) 708{ 709 enum periph_id id; 710 u32 cell[2]; 711 int err; 712 713 err = dev_read_u32_array(dev, "clocks", cell, ARRAY_SIZE(cell)); 714 if (err) 715 return -1; 716 id = clk_id_to_periph_id(cell[1]); 717 assert(clock_periph_id_isvalid(id)); 718 return id; 719} 720 721/* 722 * Get periph clock id and its parent from device tree. 723 * 724 * @param dev udevice associated with FDT node 725 * @param clk_id pointer to u32 array of 2 values 726 * first is periph clock, second is 727 * its PLL parent according to FDT. 728 */ 729int clock_decode_pair(struct udevice *dev, int *clk_id) 730{ 731 u32 cell[4]; 732 int err; 733 734 err = dev_read_u32_array(dev, "clocks", cell, ARRAY_SIZE(cell)); 735 if (err) 736 return -EINVAL; 737 738 clk_id[0] = clk_id_to_periph_id(cell[1]); 739 clk_id[1] = clk_id_to_pll_id(cell[3]); 740 741 return 0; 742} 743#endif /* CONFIG_IS_ENABLED(OF_CONTROL) */ 744 745int clock_verify(void) 746{ 747 struct clk_pll *pll = get_pll(CLOCK_ID_PERIPH); 748 u32 reg = readl(&pll->pll_base); 749 750 if (!pllp_valid) { 751 printf("Warning: PLLP %x is not correct\n", reg); 752 return -1; 753 } 754 debug("PLLP %x is correct\n", reg); 755 return 0; 756} 757 758void clock_init(void) 759{ 760 int i; 761 762 pll_rate[CLOCK_ID_CGENERAL] = clock_get_rate(CLOCK_ID_CGENERAL); 763 pll_rate[CLOCK_ID_MEMORY] = clock_get_rate(CLOCK_ID_MEMORY); 764 pll_rate[CLOCK_ID_PERIPH] = clock_get_rate(CLOCK_ID_PERIPH); 765 pll_rate[CLOCK_ID_USB] = clock_get_rate(CLOCK_ID_USB); 766 pll_rate[CLOCK_ID_DISPLAY] = clock_get_rate(CLOCK_ID_DISPLAY); 767 pll_rate[CLOCK_ID_XCPU] = clock_get_rate(CLOCK_ID_XCPU); 768 pll_rate[CLOCK_ID_SFROM32KHZ] = 32768; 769 pll_rate[CLOCK_ID_OSC] = clock_get_rate(CLOCK_ID_OSC); 770 pll_rate[CLOCK_ID_CLK_M] = clock_get_rate(CLOCK_ID_CLK_M); 771#ifndef CONFIG_TEGRA20 772 pll_rate[CLOCK_ID_DISPLAY2] = clock_get_rate(CLOCK_ID_DISPLAY2); 773#endif 774 775 debug("Osc = %d\n", pll_rate[CLOCK_ID_OSC]); 776 debug("CLKM = %d\n", pll_rate[CLOCK_ID_CLK_M]); 777 debug("PLLC = %d\n", pll_rate[CLOCK_ID_CGENERAL]); 778 debug("PLLM = %d\n", pll_rate[CLOCK_ID_MEMORY]); 779 debug("PLLP = %d\n", pll_rate[CLOCK_ID_PERIPH]); 780 debug("PLLU = %d\n", pll_rate[CLOCK_ID_USB]); 781 debug("PLLD = %d\n", pll_rate[CLOCK_ID_DISPLAY]); 782 debug("PLLX = %d\n", pll_rate[CLOCK_ID_XCPU]); 783 784 for (i = 0; periph_clk_init_table[i].periph_id != -1; i++) { 785 enum periph_id periph_id; 786 enum clock_id parent; 787 int source, mux_bits, divider_bits; 788 789 periph_id = periph_clk_init_table[i].periph_id; 790 parent = periph_clk_init_table[i].parent_clock_id; 791 792 source = get_periph_clock_source(periph_id, parent, &mux_bits, 793 ÷r_bits); 794 clock_ll_set_source_bits(periph_id, mux_bits, source); 795 } 796} 797 798static void set_avp_clock_source(u32 src) 799{ 800 struct clk_rst_ctlr *clkrst = 801 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; 802 u32 val; 803 804 val = (src << SCLK_SWAKEUP_FIQ_SOURCE_SHIFT) | 805 (src << SCLK_SWAKEUP_IRQ_SOURCE_SHIFT) | 806 (src << SCLK_SWAKEUP_RUN_SOURCE_SHIFT) | 807 (src << SCLK_SWAKEUP_IDLE_SOURCE_SHIFT) | 808 (SCLK_SYS_STATE_RUN << SCLK_SYS_STATE_SHIFT); 809 writel(val, &clkrst->crc_sclk_brst_pol); 810 udelay(3); 811} 812 813/* 814 * This function is useful on Tegra30, and any later SoCs that have compatible 815 * PLLP configuration registers. 816 * NOTE: Not used on Tegra210 - see tegra210_setup_pllp in T210 clock.c 817 */ 818void tegra30_set_up_pllp(void) 819{ 820 struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; 821 u32 reg; 822 823 /* 824 * Based on the Tegra TRM, the system clock (which is the AVP clock) can 825 * run up to 275MHz. On power on, the default sytem clock source is set 826 * to PLLP_OUT0. This function sets PLLP's (hence PLLP_OUT0's) rate to 827 * 408MHz which is beyond system clock's upper limit. 828 * 829 * The fix is to set the system clock to CLK_M before initializing PLLP, 830 * and then switch back to PLLP_OUT4, which has an appropriate divider 831 * configured, after PLLP has been configured 832 */ 833 set_avp_clock_source(SCLK_SOURCE_CLKM); 834 835 /* 836 * PLLP output frequency set to 408Mhz 837 * PLLC output frequency set to 228Mhz 838 */ 839 switch (clock_get_osc_freq()) { 840 case CLOCK_OSC_FREQ_12_0: /* OSC is 12Mhz */ 841 case CLOCK_OSC_FREQ_48_0: /* OSC is 48Mhz */ 842 clock_set_rate(CLOCK_ID_PERIPH, 408, 12, 0, 8); 843 clock_set_rate(CLOCK_ID_CGENERAL, 456, 12, 1, 8); 844 break; 845 846 case CLOCK_OSC_FREQ_26_0: /* OSC is 26Mhz */ 847 clock_set_rate(CLOCK_ID_PERIPH, 408, 26, 0, 8); 848 clock_set_rate(CLOCK_ID_CGENERAL, 600, 26, 0, 8); 849 break; 850 851 case CLOCK_OSC_FREQ_13_0: /* OSC is 13Mhz */ 852 case CLOCK_OSC_FREQ_16_8: /* OSC is 16.8Mhz */ 853 clock_set_rate(CLOCK_ID_PERIPH, 408, 13, 0, 8); 854 clock_set_rate(CLOCK_ID_CGENERAL, 600, 13, 0, 8); 855 break; 856 857 case CLOCK_OSC_FREQ_19_2: 858 case CLOCK_OSC_FREQ_38_4: 859 default: 860 /* 861 * These are not supported. It is too early to print a 862 * message and the UART likely won't work anyway due to the 863 * oscillator being wrong. 864 */ 865 break; 866 } 867 868 /* Set PLLP_OUT1, 2, 3 & 4 freqs to 9.6, 48, 102 & 204MHz */ 869 870 /* OUT1, 2 */ 871 /* Assert RSTN before enable */ 872 reg = PLLP_OUT2_RSTN_EN | PLLP_OUT1_RSTN_EN; 873 writel(reg, &clkrst->crc_pll[CLOCK_ID_PERIPH].pll_out[0]); 874 /* Set divisor and reenable */ 875 reg = (IN_408_OUT_48_DIVISOR << PLLP_OUT2_RATIO) 876 | PLLP_OUT2_OVR | PLLP_OUT2_CLKEN | PLLP_OUT2_RSTN_DIS 877 | (IN_408_OUT_9_6_DIVISOR << PLLP_OUT1_RATIO) 878 | PLLP_OUT1_OVR | PLLP_OUT1_CLKEN | PLLP_OUT1_RSTN_DIS; 879 writel(reg, &clkrst->crc_pll[CLOCK_ID_PERIPH].pll_out[0]); 880 881 /* OUT3, 4 */ 882 /* Assert RSTN before enable */ 883 reg = PLLP_OUT4_RSTN_EN | PLLP_OUT3_RSTN_EN; 884 writel(reg, &clkrst->crc_pll[CLOCK_ID_PERIPH].pll_out[1]); 885 /* Set divisor and reenable */ 886 reg = (IN_408_OUT_204_DIVISOR << PLLP_OUT4_RATIO) 887 | PLLP_OUT4_OVR | PLLP_OUT4_CLKEN | PLLP_OUT4_RSTN_DIS 888 | (IN_408_OUT_102_DIVISOR << PLLP_OUT3_RATIO) 889 | PLLP_OUT3_OVR | PLLP_OUT3_CLKEN | PLLP_OUT3_RSTN_DIS; 890 writel(reg, &clkrst->crc_pll[CLOCK_ID_PERIPH].pll_out[1]); 891 892 set_avp_clock_source(SCLK_SOURCE_PLLP_OUT4); 893} 894 895int clock_external_output(int clk_id) 896{ 897 u32 val; 898 899 if (clk_id >= 1 && clk_id <= 3) { 900 val = tegra_pmc_readl(offsetof(struct pmc_ctlr, 901 pmc_clk_out_cntrl)); 902 val |= 1 << (2 + (clk_id - 1) * 8); 903 tegra_pmc_writel(val, 904 offsetof(struct pmc_ctlr, 905 pmc_clk_out_cntrl)); 906 907 } else { 908 printf("%s: Unknown output clock id %d\n", __func__, clk_id); 909 return -EINVAL; 910 } 911 912 return 0; 913} 914 915__weak bool clock_early_init_done(void) 916{ 917 return true; 918} 919