1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * (C) Copyright 2013-2015 4 * NVIDIA Corporation <www.nvidia.com> 5 */ 6 7/* Tegra124 Clock control functions */ 8 9#include <common.h> 10#include <init.h> 11#include <log.h> 12#include <asm/io.h> 13#include <asm/arch/clock.h> 14#include <asm/arch/sysctr.h> 15#include <asm/arch/tegra.h> 16#include <asm/arch-tegra/clk_rst.h> 17#include <asm/arch-tegra/timer.h> 18#include <div64.h> 19#include <fdtdec.h> 20#include <linux/delay.h> 21 22#include <dt-bindings/clock/tegra124-car.h> 23#include <dt-bindings/clock/tegra124-car-common.h> 24 25/* 26 * Clock types that we can use as a source. The Tegra124 has muxes for the 27 * peripheral clocks, and in most cases there are four options for the clock 28 * source. This gives us a clock 'type' and exploits what commonality exists 29 * in the device. 30 * 31 * Letters are obvious, except for T which means CLK_M, and S which means the 32 * clock derived from 32KHz. Beware that CLK_M (also called OSC in the 33 * datasheet) and PLL_M are different things. The former is the basic 34 * clock supplied to the SOC from an external oscillator. The latter is the 35 * memory clock PLL. 36 * 37 * See definitions in clock_id in the header file. 38 */ 39enum clock_type_id { 40 CLOCK_TYPE_AXPT, /* PLL_A, PLL_X, PLL_P, CLK_M */ 41 CLOCK_TYPE_MCPA, /* and so on */ 42 CLOCK_TYPE_MCPT, 43 CLOCK_TYPE_PCM, 44 CLOCK_TYPE_PCMT, 45 CLOCK_TYPE_PDCT, 46 CLOCK_TYPE_ACPT, 47 CLOCK_TYPE_ASPTE, 48 CLOCK_TYPE_PMDACD2T, 49 CLOCK_TYPE_PCST, 50 CLOCK_TYPE_DP, 51 52 CLOCK_TYPE_PC2CC3M, 53 CLOCK_TYPE_PC2CC3S_T, 54 CLOCK_TYPE_PC2CC3M_T, 55 CLOCK_TYPE_PC2CC3M_T16, /* PC2CC3M_T, but w/16-bit divisor (I2C) */ 56 CLOCK_TYPE_MC2CC3P_A, 57 CLOCK_TYPE_M, 58 CLOCK_TYPE_MCPTM2C2C3, 59 CLOCK_TYPE_PC2CC3T_S, 60 CLOCK_TYPE_AC2CC3P_TS2, 61 62 CLOCK_TYPE_COUNT, 63 CLOCK_TYPE_NONE = -1, /* invalid clock type */ 64}; 65 66enum { 67 CLOCK_MAX_MUX = 8 /* number of source options for each clock */ 68}; 69 70/* 71 * Clock source mux for each clock type. This just converts our enum into 72 * a list of mux sources for use by the code. 73 * 74 * Note: 75 * The extra column in each clock source array is used to store the mask 76 * bits in its register for the source. 77 */ 78#define CLK(x) CLOCK_ID_ ## x 79static enum clock_id clock_source[CLOCK_TYPE_COUNT][CLOCK_MAX_MUX+1] = { 80 { CLK(AUDIO), CLK(XCPU), CLK(PERIPH), CLK(CLK_M), 81 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE), 82 MASK_BITS_31_30}, 83 { CLK(MEMORY), CLK(CGENERAL), CLK(PERIPH), CLK(AUDIO), 84 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE), 85 MASK_BITS_31_30}, 86 { CLK(MEMORY), CLK(CGENERAL), CLK(PERIPH), CLK(OSC), 87 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE), 88 MASK_BITS_31_30}, 89 { CLK(PERIPH), CLK(CGENERAL), CLK(MEMORY), CLK(NONE), 90 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE), 91 MASK_BITS_31_30}, 92 { CLK(PERIPH), CLK(CGENERAL), CLK(MEMORY), CLK(OSC), 93 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE), 94 MASK_BITS_31_30}, 95 { CLK(PERIPH), CLK(DISPLAY), CLK(CGENERAL), CLK(OSC), 96 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE), 97 MASK_BITS_31_30}, 98 { CLK(AUDIO), CLK(CGENERAL), CLK(PERIPH), CLK(OSC), 99 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE), 100 MASK_BITS_31_30}, 101 { CLK(AUDIO), CLK(SFROM32KHZ), CLK(PERIPH), CLK(OSC), 102 CLK(EPCI), CLK(NONE), CLK(NONE), CLK(NONE), 103 MASK_BITS_31_29}, 104 { CLK(PERIPH), CLK(MEMORY), CLK(DISPLAY), CLK(AUDIO), 105 CLK(CGENERAL), CLK(DISPLAY2), CLK(OSC), CLK(NONE), 106 MASK_BITS_31_29}, 107 { CLK(PERIPH), CLK(CGENERAL), CLK(SFROM32KHZ), CLK(OSC), 108 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE), 109 MASK_BITS_31_28}, 110 /* CLOCK_TYPE_DP */ 111 { CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE), 112 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE), 113 MASK_BITS_31_28}, 114 115 /* Additional clock types on Tegra114+ */ 116 /* CLOCK_TYPE_PC2CC3M */ 117 { CLK(PERIPH), CLK(CGENERAL2), CLK(CGENERAL), CLK(CGENERAL3), 118 CLK(MEMORY), CLK(NONE), CLK(NONE), CLK(NONE), 119 MASK_BITS_31_29}, 120 /* CLOCK_TYPE_PC2CC3S_T */ 121 { CLK(PERIPH), CLK(CGENERAL2), CLK(CGENERAL), CLK(CGENERAL3), 122 CLK(SFROM32KHZ), CLK(NONE), CLK(OSC), CLK(NONE), 123 MASK_BITS_31_29}, 124 /* CLOCK_TYPE_PC2CC3M_T */ 125 { CLK(PERIPH), CLK(CGENERAL2), CLK(CGENERAL), CLK(CGENERAL3), 126 CLK(MEMORY), CLK(NONE), CLK(OSC), CLK(NONE), 127 MASK_BITS_31_29}, 128 /* CLOCK_TYPE_PC2CC3M_T, w/16-bit divisor (I2C) */ 129 { CLK(PERIPH), CLK(CGENERAL2), CLK(CGENERAL), CLK(CGENERAL3), 130 CLK(MEMORY), CLK(NONE), CLK(OSC), CLK(NONE), 131 MASK_BITS_31_29}, 132 /* CLOCK_TYPE_MC2CC3P_A */ 133 { CLK(MEMORY), CLK(CGENERAL2), CLK(CGENERAL), CLK(CGENERAL3), 134 CLK(PERIPH), CLK(NONE), CLK(AUDIO), CLK(NONE), 135 MASK_BITS_31_29}, 136 /* CLOCK_TYPE_M */ 137 { CLK(MEMORY), CLK(NONE), CLK(NONE), CLK(NONE), 138 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE), 139 MASK_BITS_31_30}, 140 /* CLOCK_TYPE_MCPTM2C2C3 */ 141 { CLK(MEMORY), CLK(CGENERAL), CLK(PERIPH), CLK(OSC), 142 CLK(MEMORY2), CLK(CGENERAL2), CLK(CGENERAL3), CLK(NONE), 143 MASK_BITS_31_29}, 144 /* CLOCK_TYPE_PC2CC3T_S */ 145 { CLK(PERIPH), CLK(CGENERAL2), CLK(CGENERAL), CLK(CGENERAL3), 146 CLK(OSC), CLK(NONE), CLK(SFROM32KHZ), CLK(NONE), 147 MASK_BITS_31_29}, 148 /* CLOCK_TYPE_AC2CC3P_TS2 */ 149 { CLK(AUDIO), CLK(CGENERAL2), CLK(CGENERAL), CLK(CGENERAL3), 150 CLK(PERIPH), CLK(NONE), CLK(OSC), CLK(SRC2), 151 MASK_BITS_31_29}, 152}; 153 154/* 155 * Clock type for each peripheral clock source. We put the name in each 156 * record just so it is easy to match things up 157 */ 158#define TYPE(name, type) type 159static enum clock_type_id clock_periph_type[PERIPHC_COUNT] = { 160 /* 0x00 */ 161 TYPE(PERIPHC_I2S1, CLOCK_TYPE_AXPT), 162 TYPE(PERIPHC_I2S2, CLOCK_TYPE_AXPT), 163 TYPE(PERIPHC_SPDIF_OUT, CLOCK_TYPE_AXPT), 164 TYPE(PERIPHC_SPDIF_IN, CLOCK_TYPE_PC2CC3M), 165 TYPE(PERIPHC_PWM, CLOCK_TYPE_PC2CC3S_T), 166 TYPE(PERIPHC_05h, CLOCK_TYPE_NONE), 167 TYPE(PERIPHC_SBC2, CLOCK_TYPE_PC2CC3M_T), 168 TYPE(PERIPHC_SBC3, CLOCK_TYPE_PC2CC3M_T), 169 170 /* 0x08 */ 171 TYPE(PERIPHC_08h, CLOCK_TYPE_NONE), 172 TYPE(PERIPHC_I2C1, CLOCK_TYPE_PC2CC3M_T16), 173 TYPE(PERIPHC_I2C5, CLOCK_TYPE_PC2CC3M_T16), 174 TYPE(PERIPHC_0bh, CLOCK_TYPE_NONE), 175 TYPE(PERIPHC_0ch, CLOCK_TYPE_NONE), 176 TYPE(PERIPHC_SBC1, CLOCK_TYPE_PC2CC3M_T), 177 TYPE(PERIPHC_DISP1, CLOCK_TYPE_PMDACD2T), 178 TYPE(PERIPHC_DISP2, CLOCK_TYPE_PMDACD2T), 179 180 /* 0x10 */ 181 TYPE(PERIPHC_10h, CLOCK_TYPE_NONE), 182 TYPE(PERIPHC_11h, CLOCK_TYPE_NONE), 183 TYPE(PERIPHC_VI, CLOCK_TYPE_MC2CC3P_A), 184 TYPE(PERIPHC_13h, CLOCK_TYPE_NONE), 185 TYPE(PERIPHC_SDMMC1, CLOCK_TYPE_PC2CC3M_T), 186 TYPE(PERIPHC_SDMMC2, CLOCK_TYPE_PC2CC3M_T), 187 TYPE(PERIPHC_16h, CLOCK_TYPE_NONE), 188 TYPE(PERIPHC_17h, CLOCK_TYPE_NONE), 189 190 /* 0x18 */ 191 TYPE(PERIPHC_18h, CLOCK_TYPE_NONE), 192 TYPE(PERIPHC_SDMMC4, CLOCK_TYPE_PC2CC3M_T), 193 TYPE(PERIPHC_VFIR, CLOCK_TYPE_PC2CC3M_T), 194 TYPE(PERIPHC_1Bh, CLOCK_TYPE_NONE), 195 TYPE(PERIPHC_1Ch, CLOCK_TYPE_NONE), 196 TYPE(PERIPHC_HSI, CLOCK_TYPE_PC2CC3M_T), 197 TYPE(PERIPHC_UART1, CLOCK_TYPE_PC2CC3M_T), 198 TYPE(PERIPHC_UART2, CLOCK_TYPE_PC2CC3M_T), 199 200 /* 0x20 */ 201 TYPE(PERIPHC_HOST1X, CLOCK_TYPE_MC2CC3P_A), 202 TYPE(PERIPHC_21h, CLOCK_TYPE_NONE), 203 TYPE(PERIPHC_22h, CLOCK_TYPE_NONE), 204 TYPE(PERIPHC_HDMI, CLOCK_TYPE_PMDACD2T), 205 TYPE(PERIPHC_24h, CLOCK_TYPE_NONE), 206 TYPE(PERIPHC_25h, CLOCK_TYPE_NONE), 207 TYPE(PERIPHC_I2C2, CLOCK_TYPE_PC2CC3M_T16), 208 TYPE(PERIPHC_EMC, CLOCK_TYPE_MCPTM2C2C3), 209 210 /* 0x28 */ 211 TYPE(PERIPHC_UART3, CLOCK_TYPE_PC2CC3M_T), 212 TYPE(PERIPHC_29h, CLOCK_TYPE_NONE), 213 TYPE(PERIPHC_VI_SENSOR, CLOCK_TYPE_MC2CC3P_A), 214 TYPE(PERIPHC_2bh, CLOCK_TYPE_NONE), 215 TYPE(PERIPHC_2ch, CLOCK_TYPE_NONE), 216 TYPE(PERIPHC_SBC4, CLOCK_TYPE_PC2CC3M_T), 217 TYPE(PERIPHC_I2C3, CLOCK_TYPE_PC2CC3M_T16), 218 TYPE(PERIPHC_SDMMC3, CLOCK_TYPE_PC2CC3M_T), 219 220 /* 0x30 */ 221 TYPE(PERIPHC_UART4, CLOCK_TYPE_PC2CC3M_T), 222 TYPE(PERIPHC_UART5, CLOCK_TYPE_PC2CC3M_T), 223 TYPE(PERIPHC_VDE, CLOCK_TYPE_PC2CC3M_T), 224 TYPE(PERIPHC_OWR, CLOCK_TYPE_PC2CC3M_T), 225 TYPE(PERIPHC_NOR, CLOCK_TYPE_PC2CC3M_T), 226 TYPE(PERIPHC_CSITE, CLOCK_TYPE_PC2CC3M_T), 227 TYPE(PERIPHC_I2S0, CLOCK_TYPE_AXPT), 228 TYPE(PERIPHC_DTV, CLOCK_TYPE_NONE), 229 230 /* 0x38 */ 231 TYPE(PERIPHC_38h, CLOCK_TYPE_NONE), 232 TYPE(PERIPHC_39h, CLOCK_TYPE_NONE), 233 TYPE(PERIPHC_3ah, CLOCK_TYPE_NONE), 234 TYPE(PERIPHC_3bh, CLOCK_TYPE_NONE), 235 TYPE(PERIPHC_MSENC, CLOCK_TYPE_MC2CC3P_A), 236 TYPE(PERIPHC_TSEC, CLOCK_TYPE_PC2CC3M_T), 237 TYPE(PERIPHC_3eh, CLOCK_TYPE_NONE), 238 TYPE(PERIPHC_OSC, CLOCK_TYPE_NONE), 239 240 /* 0x40 */ 241 TYPE(PERIPHC_40h, CLOCK_TYPE_NONE), /* start with 0x3b0 */ 242 TYPE(PERIPHC_MSELECT, CLOCK_TYPE_PC2CC3M_T), 243 TYPE(PERIPHC_TSENSOR, CLOCK_TYPE_PC2CC3T_S), 244 TYPE(PERIPHC_I2S3, CLOCK_TYPE_AXPT), 245 TYPE(PERIPHC_I2S4, CLOCK_TYPE_AXPT), 246 TYPE(PERIPHC_I2C4, CLOCK_TYPE_PC2CC3M_T16), 247 TYPE(PERIPHC_SBC5, CLOCK_TYPE_PC2CC3M_T), 248 TYPE(PERIPHC_SBC6, CLOCK_TYPE_PC2CC3M_T), 249 250 /* 0x48 */ 251 TYPE(PERIPHC_AUDIO, CLOCK_TYPE_AC2CC3P_TS2), 252 TYPE(PERIPHC_49h, CLOCK_TYPE_NONE), 253 TYPE(PERIPHC_DAM0, CLOCK_TYPE_AC2CC3P_TS2), 254 TYPE(PERIPHC_DAM1, CLOCK_TYPE_AC2CC3P_TS2), 255 TYPE(PERIPHC_DAM2, CLOCK_TYPE_AC2CC3P_TS2), 256 TYPE(PERIPHC_HDA2CODEC2X, CLOCK_TYPE_PC2CC3M_T), 257 TYPE(PERIPHC_ACTMON, CLOCK_TYPE_PC2CC3S_T), 258 TYPE(PERIPHC_EXTPERIPH1, CLOCK_TYPE_ASPTE), 259 260 /* 0x50 */ 261 TYPE(PERIPHC_EXTPERIPH2, CLOCK_TYPE_ASPTE), 262 TYPE(PERIPHC_EXTPERIPH3, CLOCK_TYPE_ASPTE), 263 TYPE(PERIPHC_52h, CLOCK_TYPE_NONE), 264 TYPE(PERIPHC_I2CSLOW, CLOCK_TYPE_PC2CC3S_T), 265 TYPE(PERIPHC_SYS, CLOCK_TYPE_NONE), 266 TYPE(PERIPHC_55h, CLOCK_TYPE_NONE), 267 TYPE(PERIPHC_56h, CLOCK_TYPE_NONE), 268 TYPE(PERIPHC_57h, CLOCK_TYPE_NONE), 269 270 /* 0x58 */ 271 TYPE(PERIPHC_58h, CLOCK_TYPE_NONE), 272 TYPE(PERIPHC_SOR, CLOCK_TYPE_NONE), 273 TYPE(PERIPHC_5ah, CLOCK_TYPE_NONE), 274 TYPE(PERIPHC_5bh, CLOCK_TYPE_NONE), 275 TYPE(PERIPHC_SATAOOB, CLOCK_TYPE_PCMT), 276 TYPE(PERIPHC_SATA, CLOCK_TYPE_PCMT), 277 TYPE(PERIPHC_HDA, CLOCK_TYPE_PC2CC3M_T), 278 TYPE(PERIPHC_5fh, CLOCK_TYPE_NONE), 279 280 /* 0x60 */ 281 TYPE(PERIPHC_XUSB_CORE_HOST, CLOCK_TYPE_NONE), 282 TYPE(PERIPHC_XUSB_FALCON, CLOCK_TYPE_NONE), 283 TYPE(PERIPHC_XUSB_FS, CLOCK_TYPE_NONE), 284 TYPE(PERIPHC_XUSB_CORE_DEV, CLOCK_TYPE_NONE), 285 TYPE(PERIPHC_XUSB_SS, CLOCK_TYPE_NONE), 286 TYPE(PERIPHC_CILAB, CLOCK_TYPE_NONE), 287 TYPE(PERIPHC_CILCD, CLOCK_TYPE_NONE), 288 TYPE(PERIPHC_CILE, CLOCK_TYPE_NONE), 289 290 /* 0x68 */ 291 TYPE(PERIPHC_DSIA_LP, CLOCK_TYPE_NONE), 292 TYPE(PERIPHC_DSIB_LP, CLOCK_TYPE_NONE), 293 TYPE(PERIPHC_ENTROPY, CLOCK_TYPE_NONE), 294 TYPE(PERIPHC_DVFS_REF, CLOCK_TYPE_NONE), 295 TYPE(PERIPHC_DVFS_SOC, CLOCK_TYPE_NONE), 296 TYPE(PERIPHC_TRACECLKIN, CLOCK_TYPE_NONE), 297 TYPE(PERIPHC_ADX0, CLOCK_TYPE_NONE), 298 TYPE(PERIPHC_AMX0, CLOCK_TYPE_NONE), 299 300 /* 0x70 */ 301 TYPE(PERIPHC_EMC_LATENCY, CLOCK_TYPE_NONE), 302 TYPE(PERIPHC_SOC_THERM, CLOCK_TYPE_NONE), 303 TYPE(PERIPHC_72h, CLOCK_TYPE_NONE), 304 TYPE(PERIPHC_73h, CLOCK_TYPE_NONE), 305 TYPE(PERIPHC_74h, CLOCK_TYPE_NONE), 306 TYPE(PERIPHC_75h, CLOCK_TYPE_NONE), 307 TYPE(PERIPHC_VI_SENSOR2, CLOCK_TYPE_NONE), 308 TYPE(PERIPHC_I2C6, CLOCK_TYPE_PC2CC3M_T16), 309 310 /* 0x78 */ 311 TYPE(PERIPHC_78h, CLOCK_TYPE_NONE), 312 TYPE(PERIPHC_EMC_DLL, CLOCK_TYPE_MCPTM2C2C3), 313 TYPE(PERIPHC_HDMI_AUDIO, CLOCK_TYPE_NONE), 314 TYPE(PERIPHC_CLK72MHZ, CLOCK_TYPE_NONE), 315 TYPE(PERIPHC_ADX1, CLOCK_TYPE_AC2CC3P_TS2), 316 TYPE(PERIPHC_AMX1, CLOCK_TYPE_AC2CC3P_TS2), 317 TYPE(PERIPHC_VIC, CLOCK_TYPE_NONE), 318 TYPE(PERIPHC_7Fh, CLOCK_TYPE_NONE), 319}; 320 321/* 322 * This array translates a periph_id to a periphc_internal_id 323 * 324 * Not present/matched up: 325 * uint vi_sensor; _VI_SENSOR_0, 0x1A8 326 * SPDIF - which is both 0x08 and 0x0c 327 * 328 */ 329#define NONE(name) (-1) 330#define OFFSET(name, value) PERIPHC_ ## name 331static s8 periph_id_to_internal_id[PERIPH_ID_COUNT] = { 332 /* Low word: 31:0 */ 333 NONE(CPU), 334 NONE(COP), 335 NONE(TRIGSYS), 336 NONE(ISPB), 337 NONE(RESERVED4), 338 NONE(TMR), 339 PERIPHC_UART1, 340 PERIPHC_UART2, /* and vfir 0x68 */ 341 342 /* 8 */ 343 NONE(GPIO), 344 PERIPHC_SDMMC2, 345 PERIPHC_SPDIF_IN, 346 PERIPHC_I2S1, 347 PERIPHC_I2C1, 348 NONE(RESERVED13), 349 PERIPHC_SDMMC1, 350 PERIPHC_SDMMC4, 351 352 /* 16 */ 353 NONE(TCW), 354 PERIPHC_PWM, 355 PERIPHC_I2S2, 356 NONE(RESERVED19), 357 PERIPHC_VI, 358 NONE(RESERVED21), 359 NONE(USBD), 360 NONE(ISP), 361 362 /* 24 */ 363 NONE(RESERVED24), 364 NONE(RESERVED25), 365 PERIPHC_DISP2, 366 PERIPHC_DISP1, 367 PERIPHC_HOST1X, 368 NONE(VCP), 369 PERIPHC_I2S0, 370 NONE(CACHE2), 371 372 /* Middle word: 63:32 */ 373 NONE(MEM), 374 NONE(AHBDMA), 375 NONE(APBDMA), 376 NONE(RESERVED35), 377 NONE(RESERVED36), 378 NONE(STAT_MON), 379 NONE(RESERVED38), 380 NONE(FUSE), 381 382 /* 40 */ 383 NONE(KFUSE), 384 PERIPHC_SBC1, /* SBCx = SPIx */ 385 PERIPHC_NOR, 386 NONE(RESERVED43), 387 PERIPHC_SBC2, 388 NONE(XIO), 389 PERIPHC_SBC3, 390 PERIPHC_I2C5, 391 392 /* 48 */ 393 NONE(DSI), 394 NONE(RESERVED49), 395 PERIPHC_HSI, 396 PERIPHC_HDMI, 397 NONE(CSI), 398 NONE(RESERVED53), 399 PERIPHC_I2C2, 400 PERIPHC_UART3, 401 402 /* 56 */ 403 NONE(MIPI_CAL), 404 PERIPHC_EMC, 405 NONE(USB2), 406 NONE(USB3), 407 NONE(RESERVED60), 408 PERIPHC_VDE, 409 NONE(BSEA), 410 NONE(BSEV), 411 412 /* Upper word 95:64 */ 413 NONE(RESERVED64), 414 PERIPHC_UART4, 415 PERIPHC_UART5, 416 PERIPHC_I2C3, 417 PERIPHC_SBC4, 418 PERIPHC_SDMMC3, 419 NONE(PCIE), 420 PERIPHC_OWR, 421 422 /* 72 */ 423 NONE(AFI), 424 PERIPHC_CSITE, 425 NONE(PCIEXCLK), 426 NONE(AVPUCQ), 427 NONE(LA), 428 NONE(TRACECLKIN), 429 NONE(SOC_THERM), 430 NONE(DTV), 431 432 /* 80 */ 433 NONE(RESERVED80), 434 PERIPHC_I2CSLOW, 435 NONE(DSIB), 436 PERIPHC_TSEC, 437 NONE(RESERVED84), 438 NONE(RESERVED85), 439 NONE(RESERVED86), 440 NONE(EMUCIF), 441 442 /* 88 */ 443 NONE(RESERVED88), 444 NONE(XUSB_HOST), 445 NONE(RESERVED90), 446 PERIPHC_MSENC, 447 NONE(RESERVED92), 448 NONE(RESERVED93), 449 NONE(RESERVED94), 450 NONE(XUSB_DEV), 451 452 /* V word: 31:0 */ 453 NONE(CPUG), 454 NONE(CPULP), 455 NONE(V_RESERVED2), 456 PERIPHC_MSELECT, 457 NONE(V_RESERVED4), 458 PERIPHC_I2S3, 459 PERIPHC_I2S4, 460 PERIPHC_I2C4, 461 462 /* 104 */ 463 PERIPHC_SBC5, 464 PERIPHC_SBC6, 465 PERIPHC_AUDIO, 466 NONE(APBIF), 467 PERIPHC_DAM0, 468 PERIPHC_DAM1, 469 PERIPHC_DAM2, 470 PERIPHC_HDA2CODEC2X, 471 472 /* 112 */ 473 NONE(ATOMICS), 474 NONE(V_RESERVED17), 475 NONE(V_RESERVED18), 476 NONE(V_RESERVED19), 477 NONE(V_RESERVED20), 478 NONE(V_RESERVED21), 479 NONE(V_RESERVED22), 480 PERIPHC_ACTMON, 481 482 /* 120 */ 483 PERIPHC_EXTPERIPH1, 484 NONE(EXTPERIPH2), 485 NONE(EXTPERIPH3), 486 NONE(OOB), 487 PERIPHC_SATA, 488 PERIPHC_HDA, 489 NONE(TZRAM), 490 NONE(SE), 491 492 /* W word: 31:0 */ 493 NONE(HDA2HDMICODEC), 494 NONE(SATACOLD), 495 NONE(W_RESERVED2), 496 NONE(W_RESERVED3), 497 NONE(W_RESERVED4), 498 NONE(W_RESERVED5), 499 NONE(W_RESERVED6), 500 NONE(W_RESERVED7), 501 502 /* 136 */ 503 NONE(CEC), 504 NONE(W_RESERVED9), 505 NONE(W_RESERVED10), 506 NONE(W_RESERVED11), 507 NONE(W_RESERVED12), 508 NONE(W_RESERVED13), 509 NONE(XUSB_PADCTL), 510 NONE(W_RESERVED15), 511 512 /* 144 */ 513 NONE(W_RESERVED16), 514 NONE(W_RESERVED17), 515 NONE(W_RESERVED18), 516 NONE(W_RESERVED19), 517 NONE(W_RESERVED20), 518 NONE(ENTROPY), 519 NONE(DDS), 520 NONE(W_RESERVED23), 521 522 /* 152 */ 523 NONE(DP2), 524 NONE(AMX0), 525 NONE(ADX0), 526 NONE(DVFS), 527 NONE(XUSB_SS), 528 NONE(W_RESERVED29), 529 NONE(W_RESERVED30), 530 NONE(W_RESERVED31), 531 532 /* X word: 31:0 */ 533 NONE(SPARE), 534 NONE(X_RESERVED1), 535 NONE(X_RESERVED2), 536 NONE(X_RESERVED3), 537 NONE(CAM_MCLK), 538 NONE(CAM_MCLK2), 539 PERIPHC_I2C6, 540 NONE(X_RESERVED7), 541 542 /* 168 */ 543 NONE(X_RESERVED8), 544 NONE(X_RESERVED9), 545 NONE(X_RESERVED10), 546 NONE(VIM2_CLK), 547 NONE(X_RESERVED12), 548 NONE(X_RESERVED13), 549 NONE(EMC_DLL), 550 NONE(X_RESERVED15), 551 552 /* 176 */ 553 NONE(HDMI_AUDIO), 554 NONE(CLK72MHZ), 555 NONE(VIC), 556 NONE(X_RESERVED19), 557 NONE(ADX1), 558 NONE(DPAUX), 559 PERIPHC_SOR, 560 NONE(X_RESERVED23), 561 562 /* 184 */ 563 NONE(GPU), 564 NONE(AMX1), 565 NONE(X_RESERVED26), 566 NONE(X_RESERVED27), 567 NONE(X_RESERVED28), 568 NONE(X_RESERVED29), 569 NONE(X_RESERVED30), 570 NONE(X_RESERVED31), 571}; 572 573/* 574 * PLL divider shift/mask tables for all PLL IDs. 575 */ 576struct clk_pll_info tegra_pll_info_table[CLOCK_ID_PLL_COUNT] = { 577 /* 578 * T124: same as T114, some deviations from T2x/T30. Adds PLLDP. 579 * NOTE: If kcp_mask/kvco_mask == 0, they're not used in that PLL (PLLX, etc.) 580 * If lock_ena or lock_det are >31, they're not used in that PLL. 581 */ 582 583 { .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0xFF, .p_shift = 20, .p_mask = 0x0F, 584 .lock_ena = 24, .lock_det = 27, .kcp_shift = 28, .kcp_mask = 3, .kvco_shift = 27, .kvco_mask = 1 }, /* PLLC */ 585 { .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0xFF, .p_shift = 0, .p_mask = 0, 586 .lock_ena = 0, .lock_det = 27, .kcp_shift = 1, .kcp_mask = 3, .kvco_shift = 0, .kvco_mask = 1 }, /* PLLM */ 587 { .m_shift = 0, .m_mask = 0x1F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x07, 588 .lock_ena = 18, .lock_det = 27, .kcp_shift = 8, .kcp_mask = 0xF, .kvco_shift = 4, .kvco_mask = 0xF }, /* PLLP */ 589 { .m_shift = 0, .m_mask = 0x1F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x07, 590 .lock_ena = 18, .lock_det = 27, .kcp_shift = 8, .kcp_mask = 0xF, .kvco_shift = 4, .kvco_mask = 0xF }, /* PLLA */ 591 { .m_shift = 0, .m_mask = 0x1F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x01, 592 .lock_ena = 22, .lock_det = 27, .kcp_shift = 8, .kcp_mask = 0xF, .kvco_shift = 4, .kvco_mask = 0xF }, /* PLLU */ 593 { .m_shift = 0, .m_mask = 0x1F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x07, 594 .lock_ena = 22, .lock_det = 27, .kcp_shift = 8, .kcp_mask = 0xF, .kvco_shift = 4, .kvco_mask = 0xF }, /* PLLD */ 595 { .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0xFF, .p_shift = 20, .p_mask = 0x0F, 596 .lock_ena = 18, .lock_det = 27, .kcp_shift = 0, .kcp_mask = 0, .kvco_shift = 0, .kvco_mask = 0 }, /* PLLX */ 597 { .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0xFF, .p_shift = 0, .p_mask = 0, 598 .lock_ena = 9, .lock_det = 11, .kcp_shift = 6, .kcp_mask = 3, .kvco_shift = 0, .kvco_mask = 1 }, /* PLLE */ 599 { .m_shift = 0, .m_mask = 0x0F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x07, 600 .lock_ena = 18, .lock_det = 27, .kcp_shift = 8, .kcp_mask = 0xF, .kvco_shift = 4, .kvco_mask = 0xF }, /* PLLS (RESERVED) */ 601 { .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0xFF, .p_shift = 20, .p_mask = 0xF, 602 .lock_ena = 30, .lock_det = 27, .kcp_shift = 25, .kcp_mask = 3, .kvco_shift = 24, .kvco_mask = 1 }, /* PLLDP */ 603}; 604 605/* 606 * Get the oscillator frequency, from the corresponding hardware configuration 607 * field. Note that T30+ supports 3 new higher freqs. 608 */ 609enum clock_osc_freq clock_get_osc_freq(void) 610{ 611 struct clk_rst_ctlr *clkrst = 612 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; 613 u32 reg; 614 615 reg = readl(&clkrst->crc_osc_ctrl); 616 return (reg & OSC_FREQ_MASK) >> OSC_FREQ_SHIFT; 617} 618 619/* Returns a pointer to the clock source register for a peripheral */ 620u32 *get_periph_source_reg(enum periph_id periph_id) 621{ 622 struct clk_rst_ctlr *clkrst = 623 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; 624 enum periphc_internal_id internal_id; 625 626 /* Coresight is a special case */ 627 if (periph_id == PERIPH_ID_CSI) 628 return &clkrst->crc_clk_src[PERIPH_ID_CSI+1]; 629 630 assert(periph_id >= PERIPH_ID_FIRST && periph_id < PERIPH_ID_COUNT); 631 internal_id = periph_id_to_internal_id[periph_id]; 632 assert(internal_id != -1); 633 if (internal_id >= PERIPHC_X_FIRST) { 634 internal_id -= PERIPHC_X_FIRST; 635 return &clkrst->crc_clk_src_x[internal_id]; 636 } else if (internal_id >= PERIPHC_VW_FIRST) { 637 internal_id -= PERIPHC_VW_FIRST; 638 return &clkrst->crc_clk_src_vw[internal_id]; 639 } else { 640 return &clkrst->crc_clk_src[internal_id]; 641 } 642} 643 644int get_periph_clock_info(enum periph_id periph_id, int *mux_bits, 645 int *divider_bits, int *type) 646{ 647 enum periphc_internal_id internal_id; 648 649 if (!clock_periph_id_isvalid(periph_id)) 650 return -1; 651 652 internal_id = periph_id_to_internal_id[periph_id]; 653 if (!periphc_internal_id_isvalid(internal_id)) 654 return -1; 655 656 *type = clock_periph_type[internal_id]; 657 if (!clock_type_id_isvalid(*type)) 658 return -1; 659 660 *mux_bits = clock_source[*type][CLOCK_MAX_MUX]; 661 662 if (*type == CLOCK_TYPE_PC2CC3M_T16) 663 *divider_bits = 16; 664 else 665 *divider_bits = 8; 666 667 return 0; 668} 669 670enum clock_id get_periph_clock_id(enum periph_id periph_id, int source) 671{ 672 enum periphc_internal_id internal_id; 673 int type; 674 675 if (!clock_periph_id_isvalid(periph_id)) 676 return CLOCK_ID_NONE; 677 678 internal_id = periph_id_to_internal_id[periph_id]; 679 if (!periphc_internal_id_isvalid(internal_id)) 680 return CLOCK_ID_NONE; 681 682 type = clock_periph_type[internal_id]; 683 if (!clock_type_id_isvalid(type)) 684 return CLOCK_ID_NONE; 685 686 return clock_source[type][source]; 687} 688 689/** 690 * Given a peripheral ID and the required source clock, this returns which 691 * value should be programmed into the source mux for that peripheral. 692 * 693 * There is special code here to handle the one source type with 5 sources. 694 * 695 * @param periph_id peripheral to start 696 * @param source PLL id of required parent clock 697 * @param mux_bits Set to number of bits in mux register: 2 or 4 698 * @param divider_bits Set to number of divider bits (8 or 16) 699 * Return: mux value (0-4, or -1 if not found) 700 */ 701int get_periph_clock_source(enum periph_id periph_id, 702 enum clock_id parent, int *mux_bits, int *divider_bits) 703{ 704 enum clock_type_id type; 705 int mux, err; 706 707 err = get_periph_clock_info(periph_id, mux_bits, divider_bits, &type); 708 assert(!err); 709 710 for (mux = 0; mux < CLOCK_MAX_MUX; mux++) 711 if (clock_source[type][mux] == parent) 712 return mux; 713 714 /* if we get here, either us or the caller has made a mistake */ 715 printf("Caller requested bad clock: periph=%d, parent=%d\n", periph_id, 716 parent); 717 return -1; 718} 719 720void clock_set_enable(enum periph_id periph_id, int enable) 721{ 722 struct clk_rst_ctlr *clkrst = 723 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; 724 u32 *clk; 725 u32 reg; 726 727 /* Enable/disable the clock to this peripheral */ 728 assert(clock_periph_id_isvalid(periph_id)); 729 if ((int)periph_id < (int)PERIPH_ID_VW_FIRST) 730 clk = &clkrst->crc_clk_out_enb[PERIPH_REG(periph_id)]; 731 else if ((int)periph_id < PERIPH_ID_X_FIRST) 732 clk = &clkrst->crc_clk_out_enb_vw[PERIPH_REG(periph_id)]; 733 else 734 clk = &clkrst->crc_clk_out_enb_x; 735 reg = readl(clk); 736 if (enable) 737 reg |= PERIPH_MASK(periph_id); 738 else 739 reg &= ~PERIPH_MASK(periph_id); 740 writel(reg, clk); 741} 742 743void reset_set_enable(enum periph_id periph_id, int enable) 744{ 745 struct clk_rst_ctlr *clkrst = 746 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; 747 u32 *reset; 748 u32 reg; 749 750 /* Enable/disable reset to the peripheral */ 751 assert(clock_periph_id_isvalid(periph_id)); 752 if (periph_id < PERIPH_ID_VW_FIRST) 753 reset = &clkrst->crc_rst_dev[PERIPH_REG(periph_id)]; 754 else if ((int)periph_id < PERIPH_ID_X_FIRST) 755 reset = &clkrst->crc_rst_dev_vw[PERIPH_REG(periph_id)]; 756 else 757 reset = &clkrst->crc_rst_devices_x; 758 reg = readl(reset); 759 if (enable) 760 reg |= PERIPH_MASK(periph_id); 761 else 762 reg &= ~PERIPH_MASK(periph_id); 763 writel(reg, reset); 764} 765 766#if CONFIG_IS_ENABLED(OF_CONTROL) 767/* 768 * Convert a device tree clock ID to our peripheral ID. They are mostly 769 * the same but we are very cautious so we check that a valid clock ID is 770 * provided. 771 * 772 * @param clk_id Clock ID according to tegra124 device tree binding 773 * Return: peripheral ID, or PERIPH_ID_NONE if the clock ID is invalid 774 */ 775enum periph_id clk_id_to_periph_id(int clk_id) 776{ 777 if (clk_id > PERIPH_ID_COUNT) 778 return PERIPH_ID_NONE; 779 780 switch (clk_id) { 781 case PERIPH_ID_RESERVED4: 782 case PERIPH_ID_RESERVED25: 783 case PERIPH_ID_RESERVED35: 784 case PERIPH_ID_RESERVED36: 785 case PERIPH_ID_RESERVED38: 786 case PERIPH_ID_RESERVED43: 787 case PERIPH_ID_RESERVED49: 788 case PERIPH_ID_RESERVED53: 789 case PERIPH_ID_RESERVED64: 790 case PERIPH_ID_RESERVED84: 791 case PERIPH_ID_RESERVED85: 792 case PERIPH_ID_RESERVED86: 793 case PERIPH_ID_RESERVED88: 794 case PERIPH_ID_RESERVED90: 795 case PERIPH_ID_RESERVED92: 796 case PERIPH_ID_RESERVED93: 797 case PERIPH_ID_RESERVED94: 798 case PERIPH_ID_V_RESERVED2: 799 case PERIPH_ID_V_RESERVED4: 800 case PERIPH_ID_V_RESERVED17: 801 case PERIPH_ID_V_RESERVED18: 802 case PERIPH_ID_V_RESERVED19: 803 case PERIPH_ID_V_RESERVED20: 804 case PERIPH_ID_V_RESERVED21: 805 case PERIPH_ID_V_RESERVED22: 806 case PERIPH_ID_W_RESERVED2: 807 case PERIPH_ID_W_RESERVED3: 808 case PERIPH_ID_W_RESERVED4: 809 case PERIPH_ID_W_RESERVED5: 810 case PERIPH_ID_W_RESERVED6: 811 case PERIPH_ID_W_RESERVED7: 812 case PERIPH_ID_W_RESERVED9: 813 case PERIPH_ID_W_RESERVED10: 814 case PERIPH_ID_W_RESERVED11: 815 case PERIPH_ID_W_RESERVED12: 816 case PERIPH_ID_W_RESERVED13: 817 case PERIPH_ID_W_RESERVED15: 818 case PERIPH_ID_W_RESERVED16: 819 case PERIPH_ID_W_RESERVED17: 820 case PERIPH_ID_W_RESERVED18: 821 case PERIPH_ID_W_RESERVED19: 822 case PERIPH_ID_W_RESERVED20: 823 case PERIPH_ID_W_RESERVED23: 824 case PERIPH_ID_W_RESERVED29: 825 case PERIPH_ID_W_RESERVED30: 826 case PERIPH_ID_W_RESERVED31: 827 return PERIPH_ID_NONE; 828 default: 829 return clk_id; 830 } 831} 832 833/* 834 * Convert a device tree clock ID to our PLL ID. 835 * 836 * @param clk_id Clock ID according to tegra124 device tree binding 837 * Return: clock ID, or CLOCK_ID_NONE if the clock ID is invalid 838 */ 839enum clock_id clk_id_to_pll_id(int clk_id) 840{ 841 switch (clk_id) { 842 case TEGRA124_CLK_PLL_C: 843 return CLOCK_ID_CGENERAL; 844 case TEGRA124_CLK_PLL_M: 845 return CLOCK_ID_MEMORY; 846 case TEGRA124_CLK_PLL_P: 847 return CLOCK_ID_PERIPH; 848 case TEGRA124_CLK_PLL_A: 849 return CLOCK_ID_AUDIO; 850 case TEGRA124_CLK_PLL_U: 851 return CLOCK_ID_USB; 852 case TEGRA124_CLK_PLL_D: 853 case TEGRA124_CLK_PLL_D_OUT0: 854 return CLOCK_ID_DISPLAY; 855 case TEGRA124_CLK_PLL_X: 856 return CLOCK_ID_XCPU; 857 case TEGRA124_CLK_PLL_E: 858 return CLOCK_ID_EPCI; 859 case TEGRA124_CLK_CLK_32K: 860 return CLOCK_ID_32KHZ; 861 case TEGRA124_CLK_CLK_M: 862 return CLOCK_ID_CLK_M; 863 default: 864 return CLOCK_ID_NONE; 865 } 866} 867#endif /* CONFIG_IS_ENABLED(OF_CONTROL) */ 868 869void clock_early_init(void) 870{ 871 struct clk_rst_ctlr *clkrst = 872 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; 873 struct clk_pll_info *pllinfo; 874 u32 data; 875 876 tegra30_set_up_pllp(); 877 878 /* clear IDDQ before accessing any other PLLC registers */ 879 pllinfo = &tegra_pll_info_table[CLOCK_ID_CGENERAL]; 880 clrbits_le32(&clkrst->crc_pll[CLOCK_ID_CGENERAL].pll_misc, PLLC_IDDQ); 881 udelay(2); 882 883 /* 884 * PLLC output frequency set to 600Mhz 885 * PLLD output frequency set to 925Mhz 886 */ 887 switch (clock_get_osc_freq()) { 888 case CLOCK_OSC_FREQ_12_0: /* OSC is 12Mhz */ 889 case CLOCK_OSC_FREQ_48_0: /* OSC is 48Mhz */ 890 clock_set_rate(CLOCK_ID_CGENERAL, 600, 12, 0, 8); 891 clock_set_rate(CLOCK_ID_DISPLAY, 925, 12, 0, 12); 892 break; 893 894 case CLOCK_OSC_FREQ_26_0: /* OSC is 26Mhz */ 895 clock_set_rate(CLOCK_ID_CGENERAL, 600, 26, 0, 8); 896 clock_set_rate(CLOCK_ID_DISPLAY, 925, 26, 0, 12); 897 break; 898 899 case CLOCK_OSC_FREQ_13_0: /* OSC is 13Mhz */ 900 case CLOCK_OSC_FREQ_16_8: /* OSC is 16.8Mhz */ 901 clock_set_rate(CLOCK_ID_CGENERAL, 600, 13, 0, 8); 902 clock_set_rate(CLOCK_ID_DISPLAY, 925, 13, 0, 12); 903 break; 904 case CLOCK_OSC_FREQ_19_2: 905 case CLOCK_OSC_FREQ_38_4: 906 default: 907 /* 908 * These are not supported. It is too early to print a 909 * message and the UART likely won't work anyway due to the 910 * oscillator being wrong. 911 */ 912 break; 913 } 914 915 /* PLLC_MISC2: Set dynramp_stepA/B. MISC2 maps to pll_out[1] */ 916 writel(0x00561600, &clkrst->crc_pll[CLOCK_ID_CGENERAL].pll_out[1]); 917 918 /* PLLC_MISC: Set LOCK_ENABLE */ 919 pllinfo = &tegra_pll_info_table[CLOCK_ID_CGENERAL]; 920 setbits_le32(&clkrst->crc_pll[CLOCK_ID_CGENERAL].pll_misc, (1 << pllinfo->lock_ena)); 921 udelay(2); 922 923 /* PLLD_MISC: Set CLKENABLE, CPCON 12, LFCON 1, and enable lock */ 924 pllinfo = &tegra_pll_info_table[CLOCK_ID_DISPLAY]; 925 data = (12 << pllinfo->kcp_shift) | (1 << pllinfo->kvco_shift); 926 data |= (1 << PLLD_CLKENABLE) | (1 << pllinfo->lock_ena); 927 writel(data, &clkrst->crc_pll[CLOCK_ID_DISPLAY].pll_misc); 928 udelay(2); 929} 930 931/* 932 * clock_early_init_done - Check if clock_early_init() has been called 933 * 934 * Check a register that we set up to see if clock_early_init() has already 935 * been called. 936 * 937 * Return: true if clock_early_init() was called, false if not 938 */ 939bool clock_early_init_done(void) 940{ 941 struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; 942 u32 val; 943 944 val = readl(&clkrst->crc_sclk_brst_pol); 945 946 return val == 0x20002222; 947} 948 949void arch_timer_init(void) 950{ 951 struct sysctr_ctlr *sysctr = (struct sysctr_ctlr *)NV_PA_TSC_BASE; 952 u32 freq, val; 953 954 freq = clock_get_rate(CLOCK_ID_CLK_M); 955 debug("%s: clk_m freq is %dHz [0x%08X]\n", __func__, freq, freq); 956 957 /* ARM CNTFRQ */ 958 asm("mcr p15, 0, %0, c14, c0, 0\n" : : "r" (freq)); 959 960 /* Only Tegra114+ has the System Counter regs */ 961 debug("%s: setting CNTFID0 to 0x%08X\n", __func__, freq); 962 writel(freq, &sysctr->cntfid0); 963 964 val = readl(&sysctr->cntcr); 965 val |= TSC_CNTCR_ENABLE | TSC_CNTCR_HDBG; 966 writel(val, &sysctr->cntcr); 967 debug("%s: TSC CNTCR = 0x%08X\n", __func__, val); 968} 969 970#define PLLE_SS_CNTL 0x68 971#define PLLE_SS_CNTL_SSCINCINTR(x) (((x) & 0x3f) << 24) 972#define PLLE_SS_CNTL_SSCINC(x) (((x) & 0xff) << 16) 973#define PLLE_SS_CNTL_SSCINVERT (1 << 15) 974#define PLLE_SS_CNTL_SSCCENTER (1 << 14) 975#define PLLE_SS_CNTL_SSCBYP (1 << 12) 976#define PLLE_SS_CNTL_INTERP_RESET (1 << 11) 977#define PLLE_SS_CNTL_BYPASS_SS (1 << 10) 978#define PLLE_SS_CNTL_SSCMAX(x) (((x) & 0x1ff) << 0) 979 980#define PLLE_BASE 0x0e8 981#define PLLE_BASE_ENABLE (1 << 30) 982#define PLLE_BASE_LOCK_OVERRIDE (1 << 29) 983#define PLLE_BASE_PLDIV_CML(x) (((x) & 0xf) << 24) 984#define PLLE_BASE_NDIV(x) (((x) & 0xff) << 8) 985#define PLLE_BASE_MDIV(x) (((x) & 0xff) << 0) 986 987#define PLLE_MISC 0x0ec 988#define PLLE_MISC_IDDQ_SWCTL (1 << 14) 989#define PLLE_MISC_IDDQ_OVERRIDE (1 << 13) 990#define PLLE_MISC_LOCK_ENABLE (1 << 9) 991#define PLLE_MISC_PTS (1 << 8) 992#define PLLE_MISC_VREG_BG_CTRL(x) (((x) & 0x3) << 4) 993#define PLLE_MISC_VREG_CTRL(x) (((x) & 0x3) << 2) 994 995#define PLLE_AUX 0x48c 996#define PLLE_AUX_SEQ_ENABLE (1 << 24) 997#define PLLE_AUX_ENABLE_SWCTL (1 << 4) 998 999int tegra_plle_enable(void) 1000{ 1001 unsigned int m = 1, n = 200, cpcon = 13; 1002 u32 value; 1003 1004 value = readl(NV_PA_CLK_RST_BASE + PLLE_BASE); 1005 value &= ~PLLE_BASE_LOCK_OVERRIDE; 1006 writel(value, NV_PA_CLK_RST_BASE + PLLE_BASE); 1007 1008 value = readl(NV_PA_CLK_RST_BASE + PLLE_AUX); 1009 value |= PLLE_AUX_ENABLE_SWCTL; 1010 value &= ~PLLE_AUX_SEQ_ENABLE; 1011 writel(value, NV_PA_CLK_RST_BASE + PLLE_AUX); 1012 1013 udelay(1); 1014 1015 value = readl(NV_PA_CLK_RST_BASE + PLLE_MISC); 1016 value |= PLLE_MISC_IDDQ_SWCTL; 1017 value &= ~PLLE_MISC_IDDQ_OVERRIDE; 1018 value |= PLLE_MISC_LOCK_ENABLE; 1019 value |= PLLE_MISC_PTS; 1020 value |= PLLE_MISC_VREG_BG_CTRL(3); 1021 value |= PLLE_MISC_VREG_CTRL(2); 1022 writel(value, NV_PA_CLK_RST_BASE + PLLE_MISC); 1023 1024 udelay(5); 1025 1026 value = readl(NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); 1027 value |= PLLE_SS_CNTL_SSCBYP | PLLE_SS_CNTL_INTERP_RESET | 1028 PLLE_SS_CNTL_BYPASS_SS; 1029 writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); 1030 1031 value = readl(NV_PA_CLK_RST_BASE + PLLE_BASE); 1032 value &= ~PLLE_BASE_PLDIV_CML(0xf); 1033 value &= ~PLLE_BASE_NDIV(0xff); 1034 value &= ~PLLE_BASE_MDIV(0xff); 1035 value |= PLLE_BASE_PLDIV_CML(cpcon); 1036 value |= PLLE_BASE_NDIV(n); 1037 value |= PLLE_BASE_MDIV(m); 1038 writel(value, NV_PA_CLK_RST_BASE + PLLE_BASE); 1039 1040 udelay(1); 1041 1042 value = readl(NV_PA_CLK_RST_BASE + PLLE_BASE); 1043 value |= PLLE_BASE_ENABLE; 1044 writel(value, NV_PA_CLK_RST_BASE + PLLE_BASE); 1045 1046 /* wait for lock */ 1047 udelay(300); 1048 1049 value = readl(NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); 1050 value &= ~PLLE_SS_CNTL_SSCINVERT; 1051 value &= ~PLLE_SS_CNTL_SSCCENTER; 1052 1053 value &= ~PLLE_SS_CNTL_SSCINCINTR(0x3f); 1054 value &= ~PLLE_SS_CNTL_SSCINC(0xff); 1055 value &= ~PLLE_SS_CNTL_SSCMAX(0x1ff); 1056 1057 value |= PLLE_SS_CNTL_SSCINCINTR(0x20); 1058 value |= PLLE_SS_CNTL_SSCINC(0x01); 1059 value |= PLLE_SS_CNTL_SSCMAX(0x25); 1060 1061 writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); 1062 1063 value = readl(NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); 1064 value &= ~PLLE_SS_CNTL_SSCBYP; 1065 value &= ~PLLE_SS_CNTL_BYPASS_SS; 1066 writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); 1067 1068 udelay(1); 1069 1070 value = readl(NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); 1071 value &= ~PLLE_SS_CNTL_INTERP_RESET; 1072 writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); 1073 1074 udelay(1); 1075 1076 return 0; 1077} 1078 1079void clock_sor_enable_edp_clock(void) 1080{ 1081 u32 *reg; 1082 1083 /* uses PLLP, has a non-standard bit layout. */ 1084 reg = get_periph_source_reg(PERIPH_ID_SOR0); 1085 setbits_le32(reg, SOR0_CLK_SEL0); 1086} 1087 1088u32 clock_set_display_rate(u32 frequency) 1089{ 1090 /** 1091 * plld (fo) = vco >> p, where 500MHz < vco < 1000MHz 1092 * = (cf * n) >> p, where 1MHz < cf < 6MHz 1093 * = ((ref / m) * n) >> p 1094 * 1095 * Iterate the possible values of p (3 bits, 2^7) to find out a minimum 1096 * safe vco, then find best (m, n). since m has only 5 bits, we can 1097 * iterate all possible values. Note Tegra 124 supports 11 bits for n, 1098 * but our pll_fields has only 10 bits for n. 1099 * 1100 * Note values undershoot or overshoot target output frequency may not 1101 * work if the values are not in "safe" range by panel specification. 1102 */ 1103 u32 ref = clock_get_rate(CLOCK_ID_OSC); 1104 u32 divm, divn, divp, cpcon; 1105 u32 cf, vco, rounded_rate = frequency; 1106 u32 diff, best_diff, best_m = 0, best_n = 0, best_p; 1107 const u32 max_m = 1 << 5, max_n = 1 << 10, max_p = 1 << 3, 1108 mhz = 1000 * 1000, min_vco = 500 * mhz, max_vco = 1000 * mhz, 1109 min_cf = 1 * mhz, max_cf = 6 * mhz; 1110 int mux_bits, divider_bits, source; 1111 1112 for (divp = 0, vco = frequency; vco < min_vco && divp < max_p; divp++) 1113 vco <<= 1; 1114 1115 if (vco < min_vco || vco > max_vco) { 1116 printf("%s: Cannot find out a supported VCO for Frequency (%u)\n", 1117 __func__, frequency); 1118 return 0; 1119 } 1120 1121 best_p = divp; 1122 best_diff = vco; 1123 1124 for (divm = 1; divm < max_m && best_diff; divm++) { 1125 cf = ref / divm; 1126 if (cf < min_cf) 1127 break; 1128 if (cf > max_cf) 1129 continue; 1130 1131 divn = vco / cf; 1132 if (divn >= max_n) 1133 continue; 1134 1135 diff = vco - divn * cf; 1136 if (divn + 1 < max_n && diff > cf / 2) { 1137 divn++; 1138 diff = cf - diff; 1139 } 1140 1141 if (diff >= best_diff) 1142 continue; 1143 1144 best_diff = diff; 1145 best_m = divm; 1146 best_n = divn; 1147 } 1148 1149 if (best_n < 50) 1150 cpcon = 2; 1151 else if (best_n < 300) 1152 cpcon = 3; 1153 else if (best_n < 600) 1154 cpcon = 8; 1155 else 1156 cpcon = 12; 1157 1158 if (best_diff) { 1159 printf("%s: Failed to match output frequency %u, best difference is %u\n", 1160 __func__, frequency, best_diff); 1161 rounded_rate = (ref / best_m * best_n) >> best_p; 1162 } 1163 1164 debug("%s: PLLD=%u ref=%u, m/n/p/cpcon=%u/%u/%u/%u\n", 1165 __func__, rounded_rate, ref, best_m, best_n, best_p, cpcon); 1166 1167 source = get_periph_clock_source(PERIPH_ID_DISP1, CLOCK_ID_DISPLAY, 1168 &mux_bits, ÷r_bits); 1169 clock_ll_set_source_bits(PERIPH_ID_DISP1, mux_bits, source); 1170 clock_set_rate(CLOCK_ID_DISPLAY, best_n, best_m, best_p, cpcon); 1171 1172 return rounded_rate; 1173} 1174 1175void clock_set_up_plldp(void) 1176{ 1177 struct clk_rst_ctlr *clkrst = 1178 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; 1179 u32 value; 1180 1181 value = PLLDP_SS_CFG_UNDOCUMENTED | PLLDP_SS_CFG_DITHER; 1182 writel(value | PLLDP_SS_CFG_CLAMP, &clkrst->crc_plldp_ss_cfg); 1183 clock_start_pll(CLOCK_ID_DP, 1, 90, 3, 0, 0); 1184 writel(value, &clkrst->crc_plldp_ss_cfg); 1185} 1186 1187struct clk_pll_simple *clock_get_simple_pll(enum clock_id clkid) 1188{ 1189 struct clk_rst_ctlr *clkrst = 1190 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; 1191 1192 switch (clkid) { 1193 case CLOCK_ID_XCPU: 1194 case CLOCK_ID_EPCI: 1195 case CLOCK_ID_SFROM32KHZ: 1196 return &clkrst->crc_pll_simple[clkid - CLOCK_ID_FIRST_SIMPLE]; 1197 case CLOCK_ID_DP: 1198 return &clkrst->plldp; 1199 default: 1200 return NULL; 1201 } 1202} 1203 1204struct periph_clk_init periph_clk_init_table[] = { 1205 { PERIPH_ID_SBC1, CLOCK_ID_PERIPH }, 1206 { PERIPH_ID_SBC2, CLOCK_ID_PERIPH }, 1207 { PERIPH_ID_SBC3, CLOCK_ID_PERIPH }, 1208 { PERIPH_ID_SBC4, CLOCK_ID_PERIPH }, 1209 { PERIPH_ID_SBC5, CLOCK_ID_PERIPH }, 1210 { PERIPH_ID_SBC6, CLOCK_ID_PERIPH }, 1211 { PERIPH_ID_HOST1X, CLOCK_ID_PERIPH }, 1212 { PERIPH_ID_DISP1, CLOCK_ID_CGENERAL }, 1213 { PERIPH_ID_SDMMC1, CLOCK_ID_PERIPH }, 1214 { PERIPH_ID_SDMMC2, CLOCK_ID_PERIPH }, 1215 { PERIPH_ID_SDMMC3, CLOCK_ID_PERIPH }, 1216 { PERIPH_ID_SDMMC4, CLOCK_ID_PERIPH }, 1217 { PERIPH_ID_PWM, CLOCK_ID_PERIPH }, 1218 { PERIPH_ID_I2C1, CLOCK_ID_PERIPH }, 1219 { PERIPH_ID_I2C2, CLOCK_ID_PERIPH }, 1220 { PERIPH_ID_I2C3, CLOCK_ID_PERIPH }, 1221 { PERIPH_ID_I2C4, CLOCK_ID_PERIPH }, 1222 { PERIPH_ID_I2C5, CLOCK_ID_PERIPH }, 1223 { PERIPH_ID_I2C6, CLOCK_ID_PERIPH }, 1224 { -1, }, 1225}; 1226