/u-boot/drivers/serial/ |
H A D | serial_mvebu_a3700.c | 82 u32 divider, d1, d2; local 86 * Calculate divider 87 * baudrate = clock / 16 / divider 90 divider = DIV_ROUND_CLOSEST(plat->tbg_rate, baudrate * 16 * d1 * d2); 98 if (divider < 1) 99 divider = 1; 100 else if (divider > 1023) { 102 * If divider is too high for selected baudrate then set 103 * divider d1 to the maximal value 6. 106 divider 214 u32 new_divider, divider; local 325 u32 parent_rate, divider; local [all...] |
H A D | serial_bcm283x_mu.c | 61 u32 divider; local 66 divider = plat->clock / (baudrate * 8); 69 writel(divider - 1, ®s->baud);
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H A D | serial_pl01x.c | 152 unsigned int divider; local 166 divider = clock / temp; 171 writel(divider, ®s->pl011_ibrd);
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/u-boot/drivers/clk/imx/ |
H A D | clk-composite-8m.c | 35 struct clk_divider *divider = (struct clk_divider *)to_clk_divider(clk); local 43 (&composite->clk)->dev->name, parent_rate, divider->reg); 44 prediv_value = readl(divider->reg) >> divider->shift; 45 prediv_value &= clk_div_mask(divider->width); 48 NULL, divider->flags, 49 divider->width); 51 div_value = readl(divider->reg) >> PCG_DIV_SHIFT; 55 divider->flags, PCG_DIV_WIDTH); 91 struct clk_divider *divider local [all...] |
/u-boot/arch/x86/lib/ |
H A D | div64.c | 57 static u64 _64bit_divide(u64 dividend, u64 divider, u64 *rem_p) argument 62 * If divider is zero - let the rest of the system care about the 65 if (!divider) 66 return 1 / (u32)divider; 70 if (divider > MAX_32BIT_UINT) { 73 *rem_p = divider; 75 result = (u32)dividend / (u32)divider; 77 *rem_p = (u32)dividend % (u32)divider; 82 while (divider <= dividend) { 83 u64 locald = divider; [all...] |
/u-boot/drivers/clk/ |
H A D | clk-divider.c | 81 struct clk_divider *divider = to_clk_divider(clk); local 86 val = divider->io_divider_val; 88 val = readl(divider->reg); 90 val >>= divider->shift; 91 val &= clk_div_mask(divider->width); 93 return divider_recalc_rate(clk, parent_rate, val, divider->table, 94 divider->flags, divider->width); 160 struct clk_divider *divider = to_clk_divider(clk); local 165 value = divider_get_val(rate, parent_rate, divider [all...] |
H A D | clk_sandbox_ccf.c | 152 struct clk_divider *divider = (struct clk_divider *)to_clk_divider(clk); local 157 val = divider->io_divider_val; 158 val >>= divider->shift; 159 val &= clk_div_mask(divider->width); 161 return divider_recalc_rate(clk, parent_rate, val, divider->table, 162 divider->flags, divider->width); 249 /* The HW adds +1 to the divider value (2+1) is the divider */
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H A D | Makefile | 10 obj-$(CONFIG_$(SPL_TPL_)CLK_CCF) += clk.o clk-divider.o clk-mux.o clk-gate.o
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/u-boot/drivers/clk/nuvoton/ |
H A D | clk_npcm.c | 72 struct npcm_clk_div *divider = clk_data->clk_dividers; local 76 if (divider->id == id) 77 return divider; 78 divider++; 118 struct npcm_clk_div *divider; local 121 divider = npcm_clk_divider_get(priv->clk_data, clk->id); 122 if (!divider) 125 val = readl(priv->base + divider->reg); 126 div = (val & divider->mask) >> (ffs(divider 141 struct npcm_clk_div *divider; local [all...] |
/u-boot/arch/powerpc/cpu/mpc8xx/ |
H A D | speed.c | 23 uint divider = 1 << (((sccr & SCCR_DFBRG11) >> 11) * 2); local 41 gd->arch.brg_clk = gd->cpu_clk / divider;
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/u-boot/drivers/timer/ |
H A D | sp804_timer.c | 63 unsigned int divider = 1; local 70 case 0x0: divider = 1; break; 71 case 0x1: divider = 16; break; 72 case 0x2: divider = 256; break; 82 uc_priv->clock_rate = clk_get_rate(&base_clk) / divider; 84 /* keep divider, free-running, wrapping, no IRQs, 32-bit mode */
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/u-boot/drivers/spi/ |
H A D | kirkwood_spi.c | 115 u32 data, divider; local 134 divider = DIV_ROUND_UP(CFG_SYS_TCLK, hz); 135 if (divider < 16) { 136 /* This is the easy case, divider is less than 16 */ 137 spr = divider; 143 * Find the highest bit set in divider. This and the 148 sppr = fls(divider) - 4; 151 * As SPR only has 4 bits, we have to round divider up 155 divider = (divider [all...] |
/u-boot/drivers/clk/ti/ |
H A D | Makefile | 10 obj-$(CONFIG_CLK_TI_DIVIDER) += clk-divider.o
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/u-boot/arch/arm/mach-tegra/ |
H A D | clock.c | 248 * out the peripheral clock divider to use, in 7.1 binary format. 250 * @param divider_bits number of divider bits (8 or 16) 253 * Return: divider which should be used 258 u64 divider = parent_rate * 2; local 261 divider += rate - 1; 262 do_div(divider, rate); 264 if ((s64)divider - 2 < 0) 267 if ((s64)divider - 2 >= max_divider) 270 return divider - 2; 302 * Given the parent's rate and the divider i 309 get_rate_from_divider(unsigned long parent_rate, int divider) argument 388 int divider = clk_get_divider(divider_bits, divided_parent, local 416 adjust_periph_pll(enum periph_id periph_id, int source, int mux_bits, unsigned divider) argument 454 int divider; local [all...] |
/u-boot/arch/m68k/cpu/mcf532x/ |
H A D | speed.c | 55 int divider; local 59 divider = in_be16(&ccm->cdr) & CCM_CDR_LPDIV(0xF); 61 return (FREF / (3 * (1 << divider))); 64 return (FREF / (2 << divider)); 84 * div Desired system frequency divider 94 /* Check bounds of divider */ 103 /* Apply the divider to the system clock */
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/u-boot/drivers/mmc/ |
H A D | mxcmmc.c | 424 unsigned int divider; local 429 for (divider = 1; divider <= 0xF; divider++) { 432 x = (clk_in / (divider + 1)); 440 if (divider < 0x10) 449 writel((prescaler << 4) | divider, &host->base->clk_rate);
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/u-boot/drivers/clk/stm32/ |
H A D | clk-stm32h7.c | 435 u32 divider; local 437 /* get HSI divider value */ 438 divider = readl(®s->cr) & RCC_CR_HSIDIV_MASK; 439 divider = divider >> RCC_CR_HSIDIV_SHIFT; 441 return divider; 467 u32 divider; local 486 divider = 0; 488 divider = stm32_get_HSI_divider(regs); 490 log_debug("divider [all...] |
/u-boot/drivers/i2c/ |
H A D | fsl_i2c.c | 71 * frequency divider (I2C clock rate divided by I2C bus speed) to a value to be 82 * The values of the divider must be in increasing numerical order, i.e. 83 * fsl_i2c_speed_map[x+1].divider > fsl_i2c_speed_map[x].divider. 95 unsigned short divider; member in struct:__anon239 132 ushort divider = min(i2c_clk / speed, (uint)USHRT_MAX); local 137 * want the first divider that is equal to or greater than the 138 * calculated divider. 154 speed = i2c_clk / divider; /* Fake something */ 165 if (c_div > divider [all...] |
H A D | ast_i2c.c | 41 * Given desired divider ratio, return the value that needs to be set 316 ulong i2c_rate, divider; local 325 divider = i2c_rate / speed; 339 writel(get_clk_reg_val(divider), ®s->cactcr1);
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/u-boot/arch/arm/cpu/arm926ejs/mxs/ |
H A D | spl_mem_init.c | 148 /* Fractional divider for ref_emi is 33 ; 480 * 18 / 33 = 266MHz */ 149 const unsigned char divider = 33; local 151 /* Fractional divider for ref_emi is 21 ; 480 * 18 / 21 = 411MHz */ 152 const unsigned char divider = 21; local 161 /* Set fractional divider for ref_emi */ 162 writeb(CLKCTRL_FRAC_CLKGATE | (divider & CLKCTRL_FRAC_FRAC_MASK), 171 /* Set EMI clock divider for EMI clock to 411 / 2 = 205MHz */ 191 /* Set fractional divider for ref_cpu to 480 * 18 / 19 = 454MHz 207 /* CPU clock divider = 1 */
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/u-boot/drivers/sound/ |
H A D | hda_codec.c | 463 * @divider: Divider value (0 to disable the beep) 466 static int set_beep_divisor(struct hda_codec_priv *priv, uint divider) argument 469 hda_verb(priv->beep_nid, HDA_VERB_SET_BEEP, divider),
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/u-boot/drivers/ddr/marvell/a38x/ |
H A D | mv_ddr_plat.c | 854 u32 divider = 0; local 879 divider = cpu_freq / ddr_freq; 881 if (((cpu_freq % ddr_freq != 0) || (divider != 2 && divider != 3)) && 945 /* write the divider */ 946 dunit_write(0xe4268, (0x3f << 8), (divider << 8));
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/u-boot/drivers/ddr/marvell/axp/ |
H A D | ddr3_spd.c | 187 static u32 ddr3_div(u32 val, u32 divider, u32 sub); 1257 * divider - the divider 1262 u32 ddr3_div(u32 val, u32 divider, u32 sub) argument 1264 return val / divider + (val % divider > 0 ? 1 : 0) - sub;
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/u-boot/arch/arm/mach-omap2/ |
H A D | clocks-common.c | 272 u32 ddr_clk, sys_clk_khz, omap_rev, divider; local 291 divider = 4; 297 divider = 2; 300 ddr_clk = ddr_clk / divider / core_dpll_params->m2; 323 * DCC and clock divider settings for 4460.
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/u-boot/drivers/net/ |
H A D | mtk_eth.c | 1618 u32 divider; local 1623 divider = min_t(u32, DIV_ROUND_UP(MDC_MAX_FREQ, priv->mdc), MDC_MAX_DIVIDER); 1631 /* Configure MDC divider */ 1633 FIELD_PREP(PHY_MDC_CFG, divider)); 1832 /* Set MDC divider */
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