1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * Copyright (C) 2019 4 * Lukasz Majewski, DENX Software Engineering, lukma@denx.de 5 * 6 * Common Clock Framework [CCF] driver for Sandbox 7 */ 8 9#include <common.h> 10#include <dm.h> 11#include <clk.h> 12#include <malloc.h> 13#include <asm/clk.h> 14#include <clk-uclass.h> 15#include <dm/devres.h> 16#include <linux/bitops.h> 17#include <linux/clk-provider.h> 18#include <sandbox-clk.h> 19#include <linux/err.h> 20 21/* 22 * Sandbox implementation of CCF primitives necessary for clk-uclass testing 23 * 24 * --- Sandbox PLLv3 --- 25 */ 26struct clk_pllv3 { 27 struct clk clk; 28 u32 div_mask; 29 u32 div_shift; 30}; 31 32int sandbox_clk_enable_count(struct clk *clk) 33{ 34 struct clk *clkp = NULL; 35 int ret; 36 37 ret = clk_get_by_id(clk->id, &clkp); 38 if (ret) 39 return 0; 40 41 return clkp->enable_count; 42} 43 44static ulong clk_pllv3_get_rate(struct clk *clk) 45{ 46 unsigned long parent_rate = clk_get_parent_rate(clk); 47 48 return parent_rate * 24; 49} 50 51static const struct clk_ops clk_pllv3_generic_ops = { 52 .get_rate = clk_pllv3_get_rate, 53}; 54 55struct clk *sandbox_clk_pllv3(enum sandbox_pllv3_type type, const char *name, 56 const char *parent_name, void __iomem *base, 57 u32 div_mask) 58{ 59 struct clk_pllv3 *pll; 60 struct clk *clk; 61 char *drv_name = "sandbox_clk_pllv3"; 62 int ret; 63 64 pll = kzalloc(sizeof(*pll), GFP_KERNEL); 65 if (!pll) 66 return ERR_PTR(-ENOMEM); 67 68 pll->div_mask = div_mask; 69 clk = &pll->clk; 70 71 ret = clk_register(clk, drv_name, name, parent_name); 72 if (ret) { 73 kfree(pll); 74 return ERR_PTR(ret); 75 } 76 77 return clk; 78} 79 80U_BOOT_DRIVER(sandbox_clk_pll_generic) = { 81 .name = "sandbox_clk_pllv3", 82 .id = UCLASS_CLK, 83 .ops = &clk_pllv3_generic_ops, 84}; 85 86/* --- Sandbox PLLv3 --- */ 87/* --- Sandbox Gate --- */ 88struct clk_gate2 { 89 struct clk clk; 90 bool state; 91}; 92 93#define to_clk_gate2(_clk) container_of(_clk, struct clk_gate2, clk) 94 95static int clk_gate2_enable(struct clk *clk) 96{ 97 struct clk_gate2 *gate = to_clk_gate2(dev_get_clk_ptr(clk->dev)); 98 99 gate->state = 1; 100 return 0; 101} 102 103static int clk_gate2_disable(struct clk *clk) 104{ 105 struct clk_gate2 *gate = to_clk_gate2(dev_get_clk_ptr(clk->dev)); 106 107 gate->state = 0; 108 return 0; 109} 110 111static const struct clk_ops clk_gate2_ops = { 112 .enable = clk_gate2_enable, 113 .disable = clk_gate2_disable, 114 .get_rate = clk_generic_get_rate, 115}; 116 117struct clk *sandbox_clk_register_gate2(struct device *dev, const char *name, 118 const char *parent_name, 119 unsigned long flags, void __iomem *reg, 120 u8 bit_idx, u8 cgr_val, 121 u8 clk_gate2_flags) 122{ 123 struct clk_gate2 *gate; 124 struct clk *clk; 125 int ret; 126 127 gate = kzalloc(sizeof(*gate), GFP_KERNEL); 128 if (!gate) 129 return ERR_PTR(-ENOMEM); 130 131 gate->state = 0; 132 clk = &gate->clk; 133 clk->flags = flags; 134 135 ret = clk_register(clk, "sandbox_clk_gate2", name, parent_name); 136 if (ret) { 137 kfree(gate); 138 return ERR_PTR(ret); 139 } 140 141 return clk; 142} 143 144U_BOOT_DRIVER(sandbox_clk_gate2) = { 145 .name = "sandbox_clk_gate2", 146 .id = UCLASS_CLK, 147 .ops = &clk_gate2_ops, 148}; 149 150static unsigned long sandbox_clk_composite_divider_recalc_rate(struct clk *clk) 151{ 152 struct clk_divider *divider = (struct clk_divider *)to_clk_divider(clk); 153 struct clk_composite *composite = (struct clk_composite *)clk->data; 154 ulong parent_rate = clk_get_parent_rate(&composite->clk); 155 unsigned int val; 156 157 val = divider->io_divider_val; 158 val >>= divider->shift; 159 val &= clk_div_mask(divider->width); 160 161 return divider_recalc_rate(clk, parent_rate, val, divider->table, 162 divider->flags, divider->width); 163} 164 165static const struct clk_ops sandbox_clk_composite_divider_ops = { 166 .get_rate = sandbox_clk_composite_divider_recalc_rate, 167}; 168 169struct clk *sandbox_clk_composite(const char *name, 170 const char * const *parent_names, 171 int num_parents, void __iomem *reg, 172 unsigned long flags) 173{ 174 struct clk *clk = ERR_PTR(-ENOMEM); 175 struct clk_divider *div = NULL; 176 struct clk_gate *gate = NULL; 177 struct clk_mux *mux = NULL; 178 179 mux = kzalloc(sizeof(*mux), GFP_KERNEL); 180 if (!mux) 181 goto fail; 182 183 mux->reg = reg; 184 mux->shift = 24; 185 mux->mask = 0x7; 186 mux->num_parents = num_parents; 187 mux->flags = flags; 188 mux->parent_names = parent_names; 189 190 div = kzalloc(sizeof(*div), GFP_KERNEL); 191 if (!div) 192 goto fail; 193 194 div->reg = reg; 195 div->shift = 16; 196 div->width = 3; 197 div->flags = CLK_DIVIDER_ROUND_CLOSEST | flags; 198 199 gate = kzalloc(sizeof(*gate), GFP_KERNEL); 200 if (!gate) 201 goto fail; 202 203 gate->reg = reg; 204 gate->bit_idx = 28; 205 gate->flags = flags; 206 207 clk = clk_register_composite(NULL, name, 208 parent_names, num_parents, 209 &mux->clk, &clk_mux_ops, &div->clk, 210 &sandbox_clk_composite_divider_ops, 211 &gate->clk, &clk_gate_ops, flags); 212 if (IS_ERR(clk)) 213 goto fail; 214 215 return clk; 216 217fail: 218 kfree(gate); 219 kfree(div); 220 kfree(mux); 221 return ERR_CAST(clk); 222} 223 224/* --- Sandbox Gate --- */ 225/* The CCF core driver itself */ 226static const struct udevice_id sandbox_clk_ccf_test_ids[] = { 227 { .compatible = "sandbox,clk-ccf" }, 228 { } 229}; 230 231static const char *const usdhc_sels[] = { "pll3_60m", "pll3_80m", }; 232static const char *const i2c_sels[] = { "pll3_60m", "pll3_80m", }; 233 234static int sandbox_clk_ccf_probe(struct udevice *dev) 235{ 236 void *base = NULL; 237 u32 reg; 238 239 clk_dm(SANDBOX_CLK_PLL3, 240 sandbox_clk_pllv3(SANDBOX_PLLV3_USB, "pll3_usb_otg", "osc", 241 base + 0x10, 0x3)); 242 243 clk_dm(SANDBOX_CLK_PLL3_60M, 244 sandbox_clk_fixed_factor("pll3_60m", "pll3_usb_otg", 1, 8)); 245 246 clk_dm(SANDBOX_CLK_PLL3_80M, 247 sandbox_clk_fixed_factor("pll3_80m", "pll3_usb_otg", 1, 6)); 248 249 /* The HW adds +1 to the divider value (2+1) is the divider */ 250 reg = (2 << 19); 251 clk_dm(SANDBOX_CLK_ECSPI_ROOT, 252 sandbox_clk_divider("ecspi_root", "pll3_60m", ®, 19, 6)); 253 254 reg = 0; 255 clk_dm(SANDBOX_CLK_ECSPI0, 256 sandbox_clk_gate("ecspi0", "ecspi_root", ®, 0, 0)); 257 258 clk_dm(SANDBOX_CLK_ECSPI1, 259 sandbox_clk_gate2("ecspi1", "ecspi_root", base + 0x6c, 0)); 260 261 /* Select 'pll3_60m' */ 262 reg = 0; 263 clk_dm(SANDBOX_CLK_USDHC1_SEL, 264 sandbox_clk_mux("usdhc1_sel", ®, 16, 1, usdhc_sels, 265 ARRAY_SIZE(usdhc_sels))); 266 267 /* Select 'pll3_80m' */ 268 reg = BIT(17); 269 clk_dm(SANDBOX_CLK_USDHC2_SEL, 270 sandbox_clk_mux("usdhc2_sel", ®, 17, 1, usdhc_sels, 271 ARRAY_SIZE(usdhc_sels))); 272 273 reg = BIT(28) | BIT(24) | BIT(16); 274 clk_dm(SANDBOX_CLK_I2C, 275 sandbox_clk_composite("i2c", i2c_sels, ARRAY_SIZE(i2c_sels), 276 ®, CLK_SET_RATE_UNGATE)); 277 278 clk_dm(SANDBOX_CLK_I2C_ROOT, 279 sandbox_clk_gate2("i2c_root", "i2c", base + 0x7c, 0)); 280 281 return 0; 282} 283 284U_BOOT_DRIVER(sandbox_clk_ccf) = { 285 .name = "sandbox_clk_ccf", 286 .id = UCLASS_CLK, 287 .ops = &ccf_clk_ops, 288 .probe = sandbox_clk_ccf_probe, 289 .of_match = sandbox_clk_ccf_test_ids, 290}; 291