1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Copyright 2006,2009 Freescale Semiconductor, Inc. 4 * 5 * 2012, Heiko Schocher, DENX Software Engineering, hs@denx.de. 6 * Changes for multibus/multiadapter I2C support. 7 */ 8 9#include <common.h> 10#include <command.h> 11#include <i2c.h> /* Functional interface */ 12#include <log.h> 13#include <time.h> 14#include <asm/global_data.h> 15#include <asm/io.h> 16#include <asm/fsl_i2c.h> /* HW definitions */ 17#include <clk.h> 18#include <dm.h> 19#include <mapmem.h> 20#include <linux/delay.h> 21 22/* The maximum number of microseconds we will wait until another master has 23 * released the bus. If not defined in the board header file, then use a 24 * generic value. 25 */ 26#ifndef CFG_I2C_MBB_TIMEOUT 27#define CFG_I2C_MBB_TIMEOUT 100000 28#endif 29 30/* The maximum number of microseconds we will wait for a read or write 31 * operation to complete. If not defined in the board header file, then use a 32 * generic value. 33 */ 34#ifndef CFG_I2C_TIMEOUT 35#define CFG_I2C_TIMEOUT 100000 36#endif 37 38#define I2C_READ_BIT 1 39#define I2C_WRITE_BIT 0 40 41DECLARE_GLOBAL_DATA_PTR; 42 43#ifdef CONFIG_M68K 44#define CFG_FSL_I2C_BASE_ADDR CFG_SYS_MBAR 45#else 46#define CFG_FSL_I2C_BASE_ADDR CONFIG_SYS_IMMR 47#endif 48 49#if !CONFIG_IS_ENABLED(DM_I2C) 50static const struct fsl_i2c_base *i2c_base[4] = { 51 (struct fsl_i2c_base *)(CFG_FSL_I2C_BASE_ADDR + CONFIG_SYS_FSL_I2C_OFFSET), 52#ifdef CONFIG_SYS_FSL_I2C2_OFFSET 53 (struct fsl_i2c_base *)(CFG_FSL_I2C_BASE_ADDR + CONFIG_SYS_FSL_I2C2_OFFSET), 54#endif 55#ifdef CONFIG_SYS_FSL_I2C3_OFFSET 56 (struct fsl_i2c_base *)(CFG_FSL_I2C_BASE_ADDR + CONFIG_SYS_FSL_I2C3_OFFSET), 57#endif 58#ifdef CONFIG_SYS_FSL_I2C4_OFFSET 59 (struct fsl_i2c_base *)(CFG_FSL_I2C_BASE_ADDR + CONFIG_SYS_FSL_I2C4_OFFSET) 60#endif 61}; 62#endif 63 64/* I2C speed map for a DFSR value of 1 */ 65 66#ifdef __M68K__ 67/* 68 * Map I2C frequency dividers to FDR and DFSR values 69 * 70 * This structure is used to define the elements of a table that maps I2C 71 * frequency divider (I2C clock rate divided by I2C bus speed) to a value to be 72 * programmed into the Frequency Divider Ratio (FDR) and Digital Filter 73 * Sampling Rate (DFSR) registers. 74 * 75 * The actual table should be defined in the board file, and it must be called 76 * fsl_i2c_speed_map[]. 77 * 78 * The last entry of the table must have a value of {-1, X}, where X is same 79 * FDR/DFSR values as the second-to-last entry. This guarantees that any 80 * search through the array will always find a match. 81 * 82 * The values of the divider must be in increasing numerical order, i.e. 83 * fsl_i2c_speed_map[x+1].divider > fsl_i2c_speed_map[x].divider. 84 * 85 * For this table, the values are based on a value of 1 for the DFSR 86 * register. See the application note AN2919 "Determining the I2C Frequency 87 * Divider Ratio for SCL" 88 * 89 * ColdFire I2C frequency dividers for FDR values are different from 90 * PowerPC. The protocol to use the I2C module is still the same. 91 * A different table is defined and are based on MCF5xxx user manual. 92 * 93 */ 94static const struct { 95 unsigned short divider; 96 u8 fdr; 97} fsl_i2c_speed_map[] = { 98 {20, 32}, {22, 33}, {24, 34}, {26, 35}, 99 {28, 0}, {28, 36}, {30, 1}, {32, 37}, 100 {34, 2}, {36, 38}, {40, 3}, {40, 39}, 101 {44, 4}, {48, 5}, {48, 40}, {56, 6}, 102 {56, 41}, {64, 42}, {68, 7}, {72, 43}, 103 {80, 8}, {80, 44}, {88, 9}, {96, 41}, 104 {104, 10}, {112, 42}, {128, 11}, {128, 43}, 105 {144, 12}, {160, 13}, {160, 48}, {192, 14}, 106 {192, 49}, {224, 50}, {240, 15}, {256, 51}, 107 {288, 16}, {320, 17}, {320, 52}, {384, 18}, 108 {384, 53}, {448, 54}, {480, 19}, {512, 55}, 109 {576, 20}, {640, 21}, {640, 56}, {768, 22}, 110 {768, 57}, {960, 23}, {896, 58}, {1024, 59}, 111 {1152, 24}, {1280, 25}, {1280, 60}, {1536, 26}, 112 {1536, 61}, {1792, 62}, {1920, 27}, {2048, 63}, 113 {2304, 28}, {2560, 29}, {3072, 30}, {3840, 31}, 114 {-1, 31} 115}; 116#endif 117 118/** 119 * Set the I2C bus speed for a given I2C device 120 * 121 * @param base: the I2C device registers 122 * @i2c_clk: I2C bus clock frequency 123 * @speed: the desired speed of the bus 124 * 125 * The I2C device must be stopped before calling this function. 126 * 127 * The return value is the actual bus speed that is set. 128 */ 129static uint set_i2c_bus_speed(const struct fsl_i2c_base *base, 130 uint i2c_clk, uint speed) 131{ 132 ushort divider = min(i2c_clk / speed, (uint)USHRT_MAX); 133 134 /* 135 * We want to choose an FDR/DFSR that generates an I2C bus speed that 136 * is equal to or lower than the requested speed. That means that we 137 * want the first divider that is equal to or greater than the 138 * calculated divider. 139 */ 140#ifdef __PPC__ 141 u8 dfsr, fdr = 0x31; /* Default if no FDR found */ 142 /* a, b and dfsr matches identifiers A,B and C respectively in AN2919 */ 143 ushort a, b, ga, gb; 144 ulong c_div, est_div; 145 146#ifdef CONFIG_FSL_I2C_CUSTOM_DFSR 147 dfsr = CONFIG_FSL_I2C_CUSTOM_DFSR; 148#else 149 /* Condition 1: dfsr <= 50/T */ 150 dfsr = (5 * (i2c_clk / 1000)) / 100000; 151#endif 152#ifdef CONFIG_FSL_I2C_CUSTOM_FDR 153 fdr = CONFIG_FSL_I2C_CUSTOM_FDR; 154 speed = i2c_clk / divider; /* Fake something */ 155#else 156 debug("Requested speed:%d, i2c_clk:%d\n", speed, i2c_clk); 157 if (!dfsr) 158 dfsr = 1; 159 160 est_div = ~0; 161 for (ga = 0x4, a = 10; a <= 30; ga++, a += 2) { 162 for (gb = 0; gb < 8; gb++) { 163 b = 16 << gb; 164 c_div = b * (a + ((3 * dfsr) / b) * 2); 165 if (c_div > divider && c_div < est_div) { 166 ushort bin_gb, bin_ga; 167 168 est_div = c_div; 169 bin_gb = gb << 2; 170 bin_ga = (ga & 0x3) | ((ga & 0x4) << 3); 171 fdr = bin_gb | bin_ga; 172 speed = i2c_clk / est_div; 173 174 debug("FDR: 0x%.2x, ", fdr); 175 debug("div: %ld, ", est_div); 176 debug("ga: 0x%x, gb: 0x%x, ", ga, gb); 177 debug("a: %d, b: %d, speed: %d\n", a, b, speed); 178 179 /* Condition 2 not accounted for */ 180 debug("Tr <= %d ns\n", 181 (b - 3 * dfsr) * 1000000 / 182 (i2c_clk / 1000)); 183 } 184 } 185 if (a == 20) 186 a += 2; 187 if (a == 24) 188 a += 4; 189 } 190 debug("divider: %d, est_div: %ld, DFSR: %d\n", divider, est_div, dfsr); 191 debug("FDR: 0x%.2x, speed: %d\n", fdr, speed); 192#endif 193 writeb(dfsr, &base->dfsrr); /* set default filter */ 194 writeb(fdr, &base->fdr); /* set bus speed */ 195#else 196 uint i; 197 198 for (i = 0; i < ARRAY_SIZE(fsl_i2c_speed_map); i++) 199 if (fsl_i2c_speed_map[i].divider >= divider) { 200 u8 fdr; 201 202 fdr = fsl_i2c_speed_map[i].fdr; 203 speed = i2c_clk / fsl_i2c_speed_map[i].divider; 204 writeb(fdr, &base->fdr); /* set bus speed */ 205 206 break; 207 } 208#endif 209 return speed; 210} 211 212#if !CONFIG_IS_ENABLED(DM_I2C) 213static uint get_i2c_clock(int bus) 214{ 215 if (bus) 216 return gd->arch.i2c2_clk; /* I2C2 clock */ 217 else 218 return gd->arch.i2c1_clk; /* I2C1 clock */ 219} 220#endif 221 222static int fsl_i2c_fixup(const struct fsl_i2c_base *base) 223{ 224 const unsigned long long timeout = usec2ticks(CFG_I2C_MBB_TIMEOUT); 225 unsigned long long timeval = 0; 226 int ret = -1; 227 uint flags = 0; 228 229#ifdef CONFIG_SYS_FSL_ERRATUM_I2C_A004447 230 uint svr = get_svr(); 231 232 if ((SVR_SOC_VER(svr) == SVR_8548 && IS_SVR_REV(svr, 3, 1)) || 233 (SVR_REV(svr) <= CONFIG_SYS_FSL_A004447_SVR_REV)) 234 flags = I2C_CR_BIT6; 235#endif 236 237 writeb(I2C_CR_MEN | I2C_CR_MSTA, &base->cr); 238 239 timeval = get_ticks(); 240 while (!(readb(&base->sr) & I2C_SR_MBB)) { 241 if ((get_ticks() - timeval) > timeout) 242 goto err; 243 } 244 245 if (readb(&base->sr) & I2C_SR_MAL) { 246 /* SDA is stuck low */ 247 writeb(0, &base->cr); 248 udelay(100); 249 writeb(I2C_CR_MSTA | flags, &base->cr); 250 writeb(I2C_CR_MEN | I2C_CR_MSTA | flags, &base->cr); 251 } 252 253 readb(&base->dr); 254 255 timeval = get_ticks(); 256 while (!(readb(&base->sr) & I2C_SR_MIF)) { 257 if ((get_ticks() - timeval) > timeout) 258 goto err; 259 } 260 ret = 0; 261 262err: 263 writeb(I2C_CR_MEN | flags, &base->cr); 264 writeb(0, &base->sr); 265 udelay(100); 266 267 return ret; 268} 269 270static void __i2c_init(const struct fsl_i2c_base *base, int speed, int 271 slaveadd, int i2c_clk, int busnum) 272{ 273 const unsigned long long timeout = usec2ticks(CFG_I2C_MBB_TIMEOUT); 274 unsigned long long timeval; 275 276 writeb(0, &base->cr); /* stop I2C controller */ 277 udelay(5); /* let it shutdown in peace */ 278 set_i2c_bus_speed(base, i2c_clk, speed); 279 writeb(slaveadd << 1, &base->adr);/* write slave address */ 280 writeb(0x0, &base->sr); /* clear status register */ 281 /* start I2C controller */ 282 writeb(I2C_CR_MEN | I2C_CR_MIEN, &base->cr); 283 284 timeval = get_ticks(); 285 while (readb(&base->sr) & I2C_SR_MBB) { 286 if ((get_ticks() - timeval) < timeout) 287 continue; 288 289 if (fsl_i2c_fixup(base)) 290 debug("i2c_init: BUS#%d failed to init\n", 291 busnum); 292 293 break; 294 } 295} 296 297static int i2c_wait4bus(const struct fsl_i2c_base *base) 298{ 299 unsigned long long timeval = get_ticks(); 300 const unsigned long long timeout = usec2ticks(CFG_I2C_MBB_TIMEOUT); 301 302 while (readb(&base->sr) & I2C_SR_MBB) { 303 if ((get_ticks() - timeval) > timeout) 304 return -1; 305 } 306 307 return 0; 308} 309 310static int i2c_wait(const struct fsl_i2c_base *base, int write) 311{ 312 u32 csr; 313 unsigned long long timeval = get_ticks(); 314 const unsigned long long timeout = usec2ticks(CFG_I2C_TIMEOUT); 315 316 do { 317 csr = readb(&base->sr); 318 if (!(csr & I2C_SR_MIF)) 319 continue; 320 /* Read again to allow register to stabilise */ 321 csr = readb(&base->sr); 322 323 writeb(0x0, &base->sr); 324 325 if (csr & I2C_SR_MAL) { 326 debug("%s: MAL\n", __func__); 327 return -1; 328 } 329 330 if (!(csr & I2C_SR_MCF)) { 331 debug("%s: unfinished\n", __func__); 332 return -1; 333 } 334 335 if (write == I2C_WRITE_BIT && (csr & I2C_SR_RXAK)) { 336 debug("%s: No RXACK\n", __func__); 337 return -1; 338 } 339 340 return 0; 341 } while ((get_ticks() - timeval) < timeout); 342 343 debug("%s: timed out\n", __func__); 344 return -1; 345} 346 347static int i2c_write_addr(const struct fsl_i2c_base *base, u8 dev, 348 u8 dir, int rsta) 349{ 350 writeb(I2C_CR_MEN | I2C_CR_MIEN | I2C_CR_MSTA | I2C_CR_MTX 351 | (rsta ? I2C_CR_RSTA : 0), 352 &base->cr); 353 354 writeb((dev << 1) | dir, &base->dr); 355 356 if (i2c_wait(base, I2C_WRITE_BIT) < 0) 357 return 0; 358 359 return 1; 360} 361 362static int __i2c_write_data(const struct fsl_i2c_base *base, u8 *data, 363 int length) 364{ 365 int i; 366 367 for (i = 0; i < length; i++) { 368 writeb(data[i], &base->dr); 369 370 if (i2c_wait(base, I2C_WRITE_BIT) < 0) 371 break; 372 } 373 374 return i; 375} 376 377static int __i2c_read_data(const struct fsl_i2c_base *base, u8 *data, 378 int length) 379{ 380 int i; 381 382 writeb(I2C_CR_MEN | I2C_CR_MIEN | 383 I2C_CR_MSTA | ((length == 1) ? I2C_CR_TXAK : 0), 384 &base->cr); 385 386 /* dummy read */ 387 readb(&base->dr); 388 389 for (i = 0; i < length; i++) { 390 if (i2c_wait(base, I2C_READ_BIT) < 0) 391 break; 392 393 /* Generate ack on last next to last byte */ 394 if (i == length - 2) 395 writeb(I2C_CR_MEN | I2C_CR_MIEN | I2C_CR_MSTA | 396 I2C_CR_TXAK, &base->cr); 397 398 /* Do not generate stop on last byte */ 399 if (i == length - 1) 400 writeb(I2C_CR_MEN | I2C_CR_MIEN | I2C_CR_MSTA | 401 I2C_CR_MTX, &base->cr); 402 403 data[i] = readb(&base->dr); 404 } 405 406 return i; 407} 408 409static int __i2c_read(const struct fsl_i2c_base *base, u8 chip_addr, u8 *offset, 410 int olen, u8 *data, int dlen) 411{ 412 int ret = -1; /* signal error */ 413 414 if (i2c_wait4bus(base) < 0) 415 return -1; 416 417 /* Some drivers use offset lengths in excess of 4 bytes. These drivers 418 * adhere to the following convention: 419 * - the offset length is passed as negative (that is, the absolute 420 * value of olen is the actual offset length) 421 * - the offset itself is passed in data, which is overwritten by the 422 * subsequent read operation 423 */ 424 if (olen < 0) { 425 if (i2c_write_addr(base, chip_addr, I2C_WRITE_BIT, 0) != 0) 426 ret = __i2c_write_data(base, data, -olen); 427 428 if (ret != -olen) 429 return -1; 430 431 if (dlen && i2c_write_addr(base, chip_addr, 432 I2C_READ_BIT, 1) != 0) 433 ret = __i2c_read_data(base, data, dlen); 434 } else { 435 if ((!dlen || olen > 0) && 436 i2c_write_addr(base, chip_addr, I2C_WRITE_BIT, 0) != 0 && 437 __i2c_write_data(base, offset, olen) == olen) 438 ret = 0; /* No error so far */ 439 440 if (dlen && i2c_write_addr(base, chip_addr, I2C_READ_BIT, 441 olen ? 1 : 0) != 0) 442 ret = __i2c_read_data(base, data, dlen); 443 } 444 445 writeb(I2C_CR_MEN, &base->cr); 446 447 if (i2c_wait4bus(base)) /* Wait until STOP */ 448 debug("i2c_read: wait4bus timed out\n"); 449 450 if (ret == dlen) 451 return 0; 452 453 return -1; 454} 455 456static int __i2c_write(const struct fsl_i2c_base *base, u8 chip_addr, 457 u8 *offset, int olen, u8 *data, int dlen) 458{ 459 int ret = -1; /* signal error */ 460 461 if (i2c_wait4bus(base) < 0) 462 return -1; 463 464 if (i2c_write_addr(base, chip_addr, I2C_WRITE_BIT, 0) != 0 && 465 __i2c_write_data(base, offset, olen) == olen) { 466 ret = __i2c_write_data(base, data, dlen); 467 } 468 469 writeb(I2C_CR_MEN, &base->cr); 470 if (i2c_wait4bus(base)) /* Wait until STOP */ 471 debug("i2c_write: wait4bus timed out\n"); 472 473 if (ret == dlen) 474 return 0; 475 476 return -1; 477} 478 479static int __i2c_probe_chip(const struct fsl_i2c_base *base, uchar chip) 480{ 481 /* For unknown reason the controller will ACK when 482 * probing for a slave with the same address, so skip 483 * it. 484 */ 485 if (chip == (readb(&base->adr) >> 1)) 486 return -1; 487 488 return __i2c_read(base, chip, 0, 0, NULL, 0); 489} 490 491static uint __i2c_set_bus_speed(const struct fsl_i2c_base *base, 492 uint speed, int i2c_clk) 493{ 494 writeb(0, &base->cr); /* stop controller */ 495 set_i2c_bus_speed(base, i2c_clk, speed); 496 writeb(I2C_CR_MEN, &base->cr); /* start controller */ 497 498 return 0; 499} 500 501#if !CONFIG_IS_ENABLED(DM_I2C) 502static void fsl_i2c_init(struct i2c_adapter *adap, int speed, int slaveadd) 503{ 504 __i2c_init(i2c_base[adap->hwadapnr], speed, slaveadd, 505 get_i2c_clock(adap->hwadapnr), adap->hwadapnr); 506} 507 508static int fsl_i2c_probe_chip(struct i2c_adapter *adap, uchar chip) 509{ 510 return __i2c_probe_chip(i2c_base[adap->hwadapnr], chip); 511} 512 513static int fsl_i2c_read(struct i2c_adapter *adap, u8 chip_addr, uint offset, 514 int olen, u8 *data, int dlen) 515{ 516 u8 *o = (u8 *)&offset; 517 518 return __i2c_read(i2c_base[adap->hwadapnr], chip_addr, &o[4 - olen], 519 olen, data, dlen); 520} 521 522static int fsl_i2c_write(struct i2c_adapter *adap, u8 chip_addr, uint offset, 523 int olen, u8 *data, int dlen) 524{ 525 u8 *o = (u8 *)&offset; 526 527 return __i2c_write(i2c_base[adap->hwadapnr], chip_addr, &o[4 - olen], 528 olen, data, dlen); 529} 530 531static uint fsl_i2c_set_bus_speed(struct i2c_adapter *adap, uint speed) 532{ 533 return __i2c_set_bus_speed(i2c_base[adap->hwadapnr], speed, 534 get_i2c_clock(adap->hwadapnr)); 535} 536 537/* 538 * Register fsl i2c adapters 539 */ 540U_BOOT_I2C_ADAP_COMPLETE(fsl_0, fsl_i2c_init, fsl_i2c_probe_chip, fsl_i2c_read, 541 fsl_i2c_write, fsl_i2c_set_bus_speed, 542 CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, 543 0) 544#ifdef CONFIG_SYS_FSL_I2C2_OFFSET 545U_BOOT_I2C_ADAP_COMPLETE(fsl_1, fsl_i2c_init, fsl_i2c_probe_chip, fsl_i2c_read, 546 fsl_i2c_write, fsl_i2c_set_bus_speed, 547 CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, 548 1) 549#endif 550#ifdef CONFIG_SYS_FSL_I2C3_OFFSET 551U_BOOT_I2C_ADAP_COMPLETE(fsl_2, fsl_i2c_init, fsl_i2c_probe_chip, fsl_i2c_read, 552 fsl_i2c_write, fsl_i2c_set_bus_speed, 553 CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, 554 2) 555#endif 556#ifdef CONFIG_SYS_FSL_I2C4_OFFSET 557U_BOOT_I2C_ADAP_COMPLETE(fsl_3, fsl_i2c_init, fsl_i2c_probe_chip, fsl_i2c_read, 558 fsl_i2c_write, fsl_i2c_set_bus_speed, 559 CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, 560 3) 561#endif 562#else /* CONFIG_DM_I2C */ 563static int fsl_i2c_probe_chip(struct udevice *bus, u32 chip_addr, 564 u32 chip_flags) 565{ 566 struct fsl_i2c_dev *dev = dev_get_priv(bus); 567 568 return __i2c_probe_chip(dev->base, chip_addr); 569} 570 571static int fsl_i2c_set_bus_speed(struct udevice *bus, uint speed) 572{ 573 struct fsl_i2c_dev *dev = dev_get_priv(bus); 574 575 return __i2c_set_bus_speed(dev->base, speed, dev->i2c_clk); 576} 577 578static int fsl_i2c_of_to_plat(struct udevice *bus) 579{ 580 struct fsl_i2c_dev *dev = dev_get_priv(bus); 581 struct clk clock; 582 583 dev->base = map_sysmem(dev_read_addr(bus), sizeof(struct fsl_i2c_base)); 584 585 if (!dev->base) 586 return -ENOMEM; 587 588 dev->index = dev_read_u32_default(bus, "cell-index", -1); 589 dev->slaveadd = dev_read_u32_default(bus, "u-boot,i2c-slave-addr", 590 0x7f); 591 dev->speed = dev_read_u32_default(bus, "clock-frequency", 592 I2C_SPEED_FAST_RATE); 593 594 if (!clk_get_by_index(bus, 0, &clock)) 595 dev->i2c_clk = clk_get_rate(&clock); 596 else 597 dev->i2c_clk = dev->index ? gd->arch.i2c2_clk : 598 gd->arch.i2c1_clk; 599 600 return 0; 601} 602 603static int fsl_i2c_probe(struct udevice *bus) 604{ 605 struct fsl_i2c_dev *dev = dev_get_priv(bus); 606 607 __i2c_init(dev->base, dev->speed, dev->slaveadd, dev->i2c_clk, 608 dev->index); 609 return 0; 610} 611 612static int fsl_i2c_xfer(struct udevice *bus, struct i2c_msg *msg, int nmsgs) 613{ 614 struct fsl_i2c_dev *dev = dev_get_priv(bus); 615 struct i2c_msg *dmsg, *omsg, dummy; 616 617 memset(&dummy, 0, sizeof(struct i2c_msg)); 618 619 /* We expect either two messages (one with an offset and one with the 620 * actual data) or one message (just data) 621 */ 622 if (nmsgs > 2 || nmsgs == 0) { 623 debug("%s: Only one or two messages are supported.", __func__); 624 return -1; 625 } 626 627 omsg = nmsgs == 1 ? &dummy : msg; 628 dmsg = nmsgs == 1 ? msg : msg + 1; 629 630 if (dmsg->flags & I2C_M_RD) 631 return __i2c_read(dev->base, dmsg->addr, omsg->buf, omsg->len, 632 dmsg->buf, dmsg->len); 633 else 634 return __i2c_write(dev->base, dmsg->addr, omsg->buf, omsg->len, 635 dmsg->buf, dmsg->len); 636} 637 638static const struct dm_i2c_ops fsl_i2c_ops = { 639 .xfer = fsl_i2c_xfer, 640 .probe_chip = fsl_i2c_probe_chip, 641 .set_bus_speed = fsl_i2c_set_bus_speed, 642}; 643 644static const struct udevice_id fsl_i2c_ids[] = { 645 { .compatible = "fsl-i2c", }, 646 { /* sentinel */ } 647}; 648 649U_BOOT_DRIVER(i2c_fsl) = { 650 .name = "i2c_fsl", 651 .id = UCLASS_I2C, 652 .of_match = fsl_i2c_ids, 653 .probe = fsl_i2c_probe, 654 .of_to_plat = fsl_i2c_of_to_plat, 655 .priv_auto = sizeof(struct fsl_i2c_dev), 656 .ops = &fsl_i2c_ops, 657}; 658 659#endif /* CONFIG_DM_I2C */ 660