/u-boot/arch/mips/mach-ath79/qca953x/ |
H A D | clk.c | 35 u32 val, ctrl, xtal, pll, div; local 45 div = (val >> QCA953X_PLL_CPU_CONFIG_REFDIV_SHIFT) 47 pll = xtal / div; 50 div = (val >> QCA953X_PLL_CPU_CONFIG_NINT_SHIFT) 52 pll *= div; 53 div = (val >> QCA953X_PLL_CPU_CONFIG_OUTDIV_SHIFT) 55 if (!div) 56 div = 1; 57 pll >>= div; local 60 div 79 pll >>= div; local [all...] |
/u-boot/arch/mips/mach-ath79/ar933x/ |
H A D | clk.c | 35 u32 val, xtal, pll, div; local 43 div = (val >> AR933X_PLL_CPU_CONFIG_REFDIV_SHIFT) 45 pll = xtal / div; 48 div = (val >> AR933X_PLL_CPU_CONFIG_NINT_SHIFT) 50 pll *= div; 51 div = (val >> AR933X_PLL_CPU_CONFIG_OUTDIV_SHIFT) 53 if (!div) 54 div = 1; 55 pll >>= div; local 60 div [all...] |
/u-boot/drivers/clk/ |
H A D | clk-divider.c | 41 for (clkt = table; clkt->div; clkt++) 43 return clkt->div; 66 unsigned int div; local 68 div = _get_div(table, val, flags, width); 69 if (!div) { 76 return DIV_ROUND_UP_ULL((u64)parent_rate, div); 98 unsigned int div) 102 for (clkt = table; clkt->div; clkt++) 103 if (clkt->div == div) 97 clk_divider_is_valid_table_div(const struct clk_div_table *table, unsigned int div) argument 108 clk_divider_is_valid_div(const struct clk_div_table *table, unsigned int div, unsigned long flags) argument 118 clk_divider_get_table_val(const struct clk_div_table *table, unsigned int div) argument 129 _get_val(const struct clk_div_table *table, unsigned int div, unsigned long flags, u8 width) argument 146 unsigned int div, value; local 192 struct clk_divider *div; local [all...] |
H A D | clk-fixed-factor.c | 33 do_div(rate, fix->div); 43 unsigned int mult, unsigned int div) 55 fix->div = div; 71 unsigned int mult, unsigned int div) 76 div); 41 clk_hw_register_fixed_factor(struct device *dev, const char *name, const char *parent_name, unsigned long flags, unsigned int mult, unsigned int div) argument 69 clk_register_fixed_factor(struct device *dev, const char *name, const char *parent_name, unsigned long flags, unsigned int mult, unsigned int div) argument
|
/u-boot/drivers/clk/rockchip/ |
H A D | clk_rv1108.c | 34 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) 71 const struct pll_div *div) 77 uint vco_hz = OSC_HZ / 1000 * div->fbdiv / div->refdiv * 1000; 78 uint output_hz = vco_hz / div->postdiv1 / div->postdiv2; 81 pll, div->fbdiv, div->refdiv, div 70 rkclk_set_pll(struct rv1108_cru *cru, enum rk_clk_id clk_id, const struct pll_div *div) argument 152 uint8_t div; local 177 u32 div; local 196 u32 div, val; local 221 u32 div, val; local 247 u32 div, val; local 282 u32 div, val; local 310 u32 div, val; local 338 u32 div, val; local 350 u32 div, val; local 362 u32 div, val; local 420 u32 div, con; local 494 u32 div, con; local 513 int div; local [all...] |
H A D | clk_rk3588.c | 23 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) 258 u32 con, sel, div, rate, prate; local 263 div = (con & ACLK_TOP_ROOT_DIV_MASK) >> 271 return DIV_TO_RATE(prate, div); 274 div = (con & ACLK_LOW_TOP_ROOT_DIV_MASK) >> 282 return DIV_TO_RATE(prate, div); 628 u32 div, sel, con, prate; local 633 div = (con & CLK_SARADC_DIV_MASK) >> CLK_SARADC_DIV_SHIFT; 640 return DIV_TO_RATE(prate, div); 719 u32 sel, con, div, prate; local 787 int src_clk, div; local 873 u32 div, con, parent; local 894 u32 div; local 922 u32 div, sel, con, parent; local 973 int src_clk, div; local 1036 u32 div, sel, con, parent; local 1088 u32 i, conid, con, sel, div, best_div = 0, best_sel = 0; local 1198 u32 con, div; local 1226 int div; local 1266 u32 reg, con, fracdiv, div, src, p_src, p_rate; local 1328 u32 reg, clk_src, uart_src, div; local 1403 u32 con, div, src; local 1437 u32 clk_src, div; local 1916 int ret, div; local 2050 u32 con, div, sel, parent; local 2082 u32 div, sel; local [all...] |
H A D | clk_rk3368.c | 46 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) 94 const struct pll_div *div) 98 uint vco_hz = OSC_HZ / 1000 * div->nf / div->nr * 1000; 99 uint output_hz = vco_hz / div->no; 102 pll, div->nf, div->nr, div->no, vco_hz, output_hz); 109 ((div 93 rkclk_set_pll(struct rk3368_cru *cru, enum rk3368_pll_id pll_id, const struct pll_div *div) argument 164 u32 div, con, con_id, rate; local 227 u32 div = DIV_ROUND_UP(parent_rate, rate); local 259 u32 con_id, mux = 0, div = 0; local 331 u8 div; local 386 u32 div, val; local 434 u32 div, val; local [all...] |
H A D | clk_rk3308.c | 32 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) 182 u32 div, con, con_id; local 203 div = (con & CLK_I2C_DIV_CON_MASK) >> CLK_I2C_DIV_CON_SHIFT; 205 return DIV_TO_RATE(priv->dpll_hz, div); 248 u8 div; local 264 div = DIV_ROUND_UP(pll_rate, hz) - 1; 265 assert(div < 32); 267 div << MAC_DIV_SHIFT); 269 return DIV_TO_RATE(pll_rate, div); 292 u32 div, con, con_id; local 364 u32 div, con; local 392 u32 div, con; local 420 u32 div, con, con_id; local 479 u32 div, con; local 508 u32 div, pll_sel, con, con_id, parent; local 560 u32 div, pll_sel, vol_sel, con, parent; local 597 u32 i, div, best_div = 0, best_sel = 0; local 650 u32 div, con, parent = priv->dpll_hz; local 714 u32 div, con, parent = priv->dpll_hz; local 777 u32 div, con, parent = priv->vpll0_hz; local 832 u32 div, con, parent; local [all...] |
H A D | clk_rk3128.c | 30 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) 42 const struct pll_div *div) 48 uint vco_hz = OSC_HZ / 1000 * div->fbdiv / div->refdiv * 1000; 49 uint output_hz = vco_hz / div->postdiv1 / div->postdiv2; 52 pll, div->fbdiv, div->refdiv, div 41 rkclk_set_pll(struct rk3128_cru *cru, enum rk_clk_id clk_id, const struct pll_div *div) argument 79 pll_para_config(u32 freq_hz, struct pll_div *div) argument 285 uint div, mux; local 351 u32 div, con; local 396 u32 div, val; local 460 u32 div, con, parent; local [all...] |
/u-boot/arch/arm/mach-s5pc1xx/include/mach/ |
H A D | clk.h | 21 void set_mmc_clk(int dev_index, unsigned int div);
|
/u-boot/drivers/power/ |
H A D | sy8106a.c | 15 static u8 sy8106a_mvolt_to_cfg(int mvolt, int min, int max, int div) argument 22 return (mvolt - min) / div;
|
/u-boot/drivers/clk/ti/ |
H A D | clk-divider.c | 57 unsigned int div) 60 return div; 63 return __ffs(div); 66 return clk_divider_get_table_val(table, div); 68 return div - 1; 76 int div = DIV_ROUND_UP_ULL((u64)parent_rate, rate); local 78 for (clkt = table; clkt->div; clkt++) { 79 if (clkt->div == div) 80 return clkt->div; 56 _get_val(const struct clk_div_table *table, ulong flags, unsigned int div) argument 175 int div; local 188 int div; local 216 unsigned int div; local [all...] |
/u-boot/drivers/clk/renesas/ |
H A D | rcar-cpg-lib.c | 55 for (clkt = table; clkt->div; clkt++) 57 return clkt->div; 62 unsigned int div) 66 for (clkt = table; clkt->div; clkt++) 67 if (clkt->div == div) 76 u32 value, div; local 80 div = rcar_clk_get_table_div(table, value); 81 if (!div) 84 rate = parent_rate / div; 61 rcar_clk_get_table_val(const struct clk_div_table *table, unsigned int div) argument 95 u32 value = 0, div = 0; local [all...] |
/u-boot/drivers/clk/imx/ |
H A D | clk-composite-93.c | 93 struct clk_divider *div = NULL; local 108 div = kzalloc(sizeof(*div), GFP_KERNEL); 109 if (!div) 112 div->reg = reg; 113 div->shift = CCM_DIV_SHIFT; 114 div->width = CCM_DIV_WIDTH; 115 div->flags = CLK_DIVIDER_ROUND_CLOSEST | flags; 128 &div->clk, &clk_divider_ops, 139 kfree(div); [all...] |
H A D | clk-pllv3.c | 54 u32 div = (readl(pll->base) >> pll->div_shift) & pll->div_mask; local 56 return (div == 0) ? parent_rate * 22 : parent_rate * 20; 64 u32 div = (readl(pll->base) >> pll->div_shift) & pll->div_mask; local 65 u32 val = (div == 0) ? parent_rate * 22 : parent_rate * 20; 78 u32 div = (readl(pll->base) >> pll->div_shift) & pll->div_mask; local 80 return (div == 1) ? parent_rate * 22 : parent_rate * 20; 87 u32 val, div; local 90 div = 1; 92 div = 0; 98 val |= (div << pl 162 u32 div = readl(pll->base) & pll->div_mask; local 173 u32 val, div; local 210 u32 div = readl(pll->base) & pll->div_mask; local 228 u32 val, div; local [all...] |
H A D | clk-composite-8m.c | 126 struct clk_divider *div = NULL; local 141 div = kzalloc(sizeof(*div), GFP_KERNEL); 142 if (!div) 145 div->reg = reg; 146 div->shift = PCG_PREDIV_SHIFT; 147 div->width = PCG_PREDIV_WIDTH; 148 div->flags = CLK_DIVIDER_ROUND_CLOSEST | flags; 160 &mux->clk, &clk_mux_ops, &div->clk, 170 kfree(div); [all...] |
/u-boot/drivers/clk/mvebu/ |
H A D | armada-37xx-tbg.c | 58 unsigned int div[NUM_TBG]; member in struct:a37xx_tbgclk 73 unsigned int div; local 77 div = (val >> ptbg->refdiv_offset) & TBG_DIV_MASK; 78 if (div == 0) 79 div = 1; 82 div *= 1 << ((val >> ptbg->vcodiv_offset) & TBG_DIV_MASK); 84 return div; 128 unsigned int mult, div; local 131 div = tbg_get_div(reg, &tbg[i]); 133 priv->rates[i] = (xtal * mult) / div; [all...] |
/u-boot/arch/arm/mach-s5pc1xx/ |
H A D | clock.c | 133 unsigned long div; local 137 div = readl(&clk->div0); 140 apll_ratio = div & 0x7; 153 unsigned long div; local 157 div = readl(&clk->div0); 160 arm_ratio = (div >> 4) & 0x7; 162 apll_ratio = div & 0x1; 176 uint div, d0_bus_ratio; local 178 div = readl(&clk->div0); 180 d0_bus_ratio = (div >> 193 uint div, d1_bus_ratio, pclkd1_ratio; local 214 unsigned int div; local 243 unsigned int div; local 319 set_mmc_clk(int dev_index, unsigned int div) argument [all...] |
/u-boot/arch/arm/cpu/arm926ejs/mxs/ |
H A D | clock.c | 42 uint32_t clkctrl, clkseq, div; local 57 div = (clkctrl & CLKCTRL_CPU_DIV_XTAL_MASK) >> 59 return XTAL_FREQ_MHZ / div; 65 div = clkctrl & CLKCTRL_CPU_DIV_CPU_MASK; 66 return (PLL_FREQ_MHZ * PLL_FREQ_COEF / frac) / div; 74 uint32_t div; local 83 div = clkctrl & CLKCTRL_HBUS_DIV_MASK; 84 return mxs_get_pclk() / div; 92 uint32_t clkctrl, clkseq, div; local 100 div 123 uint32_t clkctrl, clkseq, div; local 149 uint32_t div; local [all...] |
/u-boot/arch/arm/cpu/armv7/s5p-common/ |
H A D | pwm.c | 51 unsigned int div; local 70 div = ((val >> 0) & 0xff) + 1; 72 div = ((val >> 8) & 0xff) + 1; 79 freq = tin_parent_rate / div / pre_div; 83 for (div = 2; div <= 16; div *= 2) { 84 if ((tin_parent_rate / (div << 16)) < freq) 85 return tin_parent_rate / div; 159 int s5p_pwm_init(int pwm_id, int div, in argument [all...] |
/u-boot/drivers/clk/nuvoton/ |
H A D | clk_npcm.c | 6 * Fout = ((Fin / PRE_DIV) / div) / POST_DIV 119 u32 val, div; local 126 div = (val & divider->mask) >> (ffs(divider->mask) - 1); 128 div = div + 1; 130 div = 1 << div; 133 div = div << 1; 135 return div; 138 npcm_clk_set_div(struct clk *clk, u32 div) argument 176 u32 div; local 252 u32 div; local [all...] |
/u-boot/drivers/adc/ |
H A D | stm32-adc-core.c | 33 * @div: prescaler division ratio 38 int div; member in struct:stm32h7_adc_ck_spec 67 int div; local 94 div = stm32h7_adc_ckmodes_spec[i].div; 99 if ((rate / div) <= STM32H7_ADC_MAX_CLK_RATE) 114 div = stm32h7_adc_ckmodes_spec[i].div; 119 if ((rate / div) <= STM32H7_ADC_MAX_CLK_RATE) 128 common->rate = rate / div; [all...] |
/u-boot/lib/ |
H A D | tiny-printf.c | 37 unsigned long div) 41 while (*num >= div) { 42 *num -= div; 165 unsigned long div; local 193 div = 1UL << (sizeof(long) * 8 - 4); 194 for (; div; div /= 0x10) 195 div_out(info, &num, div); 205 unsigned long div; local 246 div 36 div_out(struct printf_info *info, unsigned long *num, unsigned long div) argument [all...] |
/u-boot/arch/arm/cpu/armv7/bcm235xx/ |
H A D | clk-core.c | 97 debug("%s %s set rate %lu div %lu sel %d parent %lu\n", 98 __func__, c->name, c->rate, c->div, c->sel, 113 /* div and pll select */ 114 if (divider_exists(&cd->div)) { 115 reg = readl(base + cd->div.offset); 116 bitfield_replace(reg, cd->div.shift, cd->div.width, 117 c->div - 1); 118 writel(reg, base + cd->div.offset); 167 unsigned long new_rate = 0, div local 211 int div = 1; local [all...] |
/u-boot/arch/arm/cpu/armv7/bcm281xx/ |
H A D | clk-core.c | 97 debug("%s %s set rate %lu div %lu sel %d parent %lu\n", 98 __func__, c->name, c->rate, c->div, c->sel, 113 /* div and pll select */ 114 if (divider_exists(&cd->div)) { 115 reg = readl(base + cd->div.offset); 116 bitfield_replace(reg, cd->div.shift, cd->div.width, 117 c->div - 1); 118 writel(reg, base + cd->div.offset); 167 unsigned long new_rate = 0, div local 211 int div = 1; local [all...] |